fax id: 1078 Family CY62128V Family 128K x 8 Static RAM Features three-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. The CY62128V family is available in the standard 450-mil-wide SOIC, TSOP, and STSOP packages. * Low voltage range: -- 2.7V-3.6V (CY62128V) Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and the chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). -- 2.3V-2.7V (CY62128V25) * * * * * -- 1.6V-2.0V (CY62128V18) Low active power and standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Functional Description Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE 2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The CY62128V family is composed of three high-performance CMOS static RAMs organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Logic Block Diagram Pin Configurations Top View SOIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O0 INPUTBUFFER I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O2 I/O3 512x 256x 8 ARRAY I/O4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 62128V-2 I/O5 COLUMN DECODER CE1 CE2 WE I/O6 POWER DOWN I/O7 62128V-1 OE A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TSOP I Reverse Pinout Top View (not to scale) Cypress Semiconductor Corporation * A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE 62128V-3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 3901 North First Street 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 * TSOP I / STSOP Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 62128V-4 San Jose * CA 95134 * 408-943-2600 November 1996 - Revised April 20, 1998 CY62128V Family Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current.................................................... >200 mA Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................... 55C to +125C Operating Range Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +4.6V Ambient Temperature VCC 0C to +70C 1.6V to 3.6V -40C to +85C 1.6V to 3.6V Commercial DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Industrial DC Input Voltage[1].................................-0.5V to VCC + 0.5V Product Portfolio Power Dissipation (Commercial) VCC Range Product Min. Typ. [2] Operating (I cc) [2] Maximum Standby (ISB2) [2] Max. Speed Typ. CY62128V 2.7V 3.0V 3.6V 70 ns 20 mA 40 mA Typ. 0.4 A 100 A (15 A = LL) Maximum CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 mA 0.3 A 50 A (10 A = LL) CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 mA 0.3 A 30 A (10 A = LL) Electrical Characteristics Over the Operating Range CY62128V-70 Parameter Description Test Conditions Min. Typ.[2] Max. 2.4 Unit VOH Output HIGH Voltage VCC = Min., IOH = -1.0 mA V VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIX Input Load Current GND < VI < VCC -1 1 +1 A IOZ Output Leakage Current GND < VO < VCC, Output Disabled -1 1 +1 A ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 20 40 mA 15 300 A 0.4 100 A LL 15 A L 100 A LL 30 A 2 -0.5 Com'l L 0.4 V VCC +0.5V V LL Ind'l L LL ISB1 Automatic CE Power-Down Current-- TTL Inputs Max. VCC, CE > VIH, Com'l VIN > VIH or VIN < VIL, f = fMAX Ind'l L LL L LL ISB2 Automatic CE Power-Down Current-- CMOS Inputs Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Com'l Ind'l L Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25C. 2 CY62128V Family Electrical Characteristics Over the Operating Range CY62128V25-100 Parameter Description Test Conditions Min. 2.4 [2] Typ. Max. VOH Output HIGH Voltage VCC = Min., IOH = -0.1 mA VOL Output LOW Voltage VCC = Min., IOL = 0.1 mA VIH Input HIGH Voltage 2 VCC +0.5 VIL Input LOW Voltage -0.5 IIX Input Load Current IOZ Output Leakage Current ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L Automatic CE Power-Down Current-- TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX L Automatic CE Power-Down Current-- CMOS Inputs Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 L LL Indust'l Temp Range LL ISB1 ISB2 GND < VI < VCC GND < VO < VCC, Output Disabled CY62128V18-200 Min. Typ.[2] Max. 0.8* Vcc V 0.4 0.2 V 0.7* VCC VCC +0.3 V 0.8 -0.5 0.3* VCC V -1 1 +1 -1 0.1 +1 A -1 1 +1 -1 0.1 +1 A 15 20 10 15 mA 15 300 5 100 A 0.4 50 0.4 30 A 12 10 A 24 20 A LL LL Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Unit Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 Max. Unit 6 pF 8 pF CY62128V Family AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT 1.8V R2 50 pF GND 90% 10% < 5 ns < 5 ns INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 62128V-5 62128V-6 THEVENIN EQUIVALENT RTH OUTPUT V Parameters 3.3V 2.5V 1.8V Unit R1 1213 15909 10800 Ohms R2 1378 4487 4154 Ohms RTH 645 3500 3000 Ohms VTH 1.75V 0.55V 0.50V Volts Data Retention Characteristics (Over the Operating Range) Parameter Conditions[4] Description VDR VCC for Data Retention ICCDR Data Retention Current Min. Typ.[2] Max. 1.4 Com'l L LL Ind'l L LL tCDR[3] Chip Deselect to Data Retention Time tR Operation Recovery Time VCC = 1.6V CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V No input may exceed VCC+0.3V Unit V 0.4 10 A 10 A 20 A 20 A 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 1.8V VDR > 1.4 V tCDR 1.8V tR CE C62128V-7 Note: 4. No input may exceed VCC+0.3V. 4 CY62128V Family Switching Characteristics Over the Operating Range[5] CY62128V-70 Parameter Description Min. Max. CY62128V25-100 CY62128V18-200 Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[6] tHZOE 70 OE HIGH to High Z tLZCE CE LOW to Low Z 10 CE LOW to Power-Up 10 75 10 25 10 50 25 CE HIGH to Power-Down ns 125 ns ns 75 50 70 200 10 0 ns ns 75 0 100 ns ns 10 10 0 ns 200 100 35 10 [6, 7] CE HIGH to High Z 200 100 70 [6] tPU WRITE CYCLE 10 [6, 7] tHZCE tPD 100 70 ns ns 200 ns [8,9] tWC Write Cycle Time 70 100 200 ns tSCE CE LOW to Write End 60 100 190 ns tAW Address Set-Up to Write End 60 100 190 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 55 90 125 ns tSD Data Set-Up to Write End 30 60 100 ns tHD Data Hold from Write End 0 0 0 ns [6, 7] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z[6] 25 5 50 10 100 15 ns ns Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID 62128V-8 Notes: 5. Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE signals must be LOW and CE2 HIGH to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL, CE2=VIH. 11. WE is HIGH for read cycle. 5 CY62128V Family Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[11,12] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB 62128V-9 Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID 62128V-10 Notes: 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 6 CY62128V Family Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 15 tHZOE 62128V-11 Note: 15. During this period, the I/Os are in output state and input signals should not be applied. Truth Table CE1 CE2 OE WE H X X X High Z I/O0-I/O7 Power-Down Mode Standby (ISB) Power X L X X High Z Power-Down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) 7 CY62128V Family Ordering Information Speed (ns) 70 70 100 100 200 Ordering Code Package Name CY62128VL-70SC S34 CY62128VLL-70SC S34 CY62128VL-70ZC Z32 CY62128VLL-70ZC Z32 CY62128VL-70ZAC ZA32 CY62128VLL-70ZAC ZA32 CY62128VL-70ZRC ZR32 CY62128VLL-70ZRC ZR32 CY62128VL-70SI S34 CY62128VLL-70SI S34 CY62128VL-70ZI Z32 CY62128VLL-70ZI Z32 CY62128VL-70ZAI ZA32 CY62128VLL-70ZAI ZA32 CY62128VL-70ZRI ZR32 CY62128VLL-70ZRI ZR32 CY62128V25L-100SC S34 CY62128V25LL-100SC S34 CY62128V25L-100ZC Z32 CY62128V25LL-100ZC Z32 CY62128V25L-100ZAC ZA32 CY62128V25LL-100ZAC ZA32 CY62128V25L-100ZRC ZR32 CY62128V25LL-100ZRC ZR32 CY62128V25L-100SI S34 CY62128V25LL-100SI S34 CY62128V25L-100ZI Z32 CY62128V25LL-100ZI Z32 CY62128V25L-100ZAI ZA32 CY62128V25LL-100ZAI ZA32 CY62128V25L-100ZRI ZR32 CY62128V25LL-100ZRI ZR32 CY62128V18L-200SC S34 CY62128V18LL-200SC S34 CY62128V18L-200ZC Z32 CY62128V18LL-200ZC Z32 CY62128V18L-200ZAC ZA32 CY62128V18LL-200ZAC ZA32 CY62128V18L-200ZRC ZR32 CY62128V18LL-200ZRC ZR32 Package Type 32-Lead 450-Mil SOIC Operating Range Commercial 32-Lead TSOP Type 1 32-Lead STSOP Type 1 32-Lead Reverse TSOP 1 32-Lead 450-Mil SOIC Industrial 32-Lead TSOP Type 1 32-Lead STSOP Type 1 32-Lead Reverse TSOP 1 32-Lead 450-Mil SOIC Commercial 32-Lead TSOP Type 1 32-Lead STSOP Type 1 32-Lead Reverse TSOP 1 32-Lead 450-Mil SOIC Industrial 32-Lead TSOP Type 1 32-Lead STSOP Type 1 32-Lead Reverse TSOP 1 32-Lead 450-Mil SOIC 32-Lead TSOP Type 1 32-Lead STSOP Type 1 32-Lead Reverse TSOP 1 8 Commercial CY62128V Family Ordering Information (continued) Speed (ns) 200 Ordering Code Package Name CY62128V18L-200SI S34 CY62128V18LL-200SI S34 CY62128V18L-200ZI Z32 CY62128V18LL-200ZI Z32 CY62128V18L-200ZAI ZA32 CY62128V18LL-200ZAI ZA32 CY62128V18L-200ZRI ZR32 CY62128V18LL-200ZRI ZR32 Package Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 1 32-Lead STSOP Type 1 32-Lead Reverse TSOP 1 Document #: 38-00547-A 9 Operating Range Industrial CY62128V Family Package Diagrams 32-Lead (450 Mil) Molded SOIC S32 32-Lead Thin Small Outline Package Z32 10 CY62128V Family Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package ZA32 13.20 (.520) 13.60 (.535) 11.70 (.461) 11.90 (.469) 32-Lead Reverse Thin Small Outline Package ZR32 (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.