128K x 8 Static RAM
f
ax id: 1078
CY62128V Fami ly
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 1996 - Revised Apri l 20
,
1998
F
amily
Features
• Low voltage range:
—2.7V–3.6V (CY62128V)
—2.3V–2.7V (CY62128V25)
—1.6V–2.0V (CY62128V18)
• Low acti ve power and st andby power
• Easy memory expansion with CE and OE features
• TTL-compatible input s and outputs
• Aut om atic power-d own w hen deselected
• CMOS for optimum speed/power
Functional Description
The CY621 28V fami ly i s c omposed of t hree hi gh-per fo rmance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW chip
enable (CE) and active LOW output enable (OE) and
three-state drivers. These devices have an automatic pow-
er-down feature, reducing the power consumption by over 99%
when deselected. The CY62128V family is available in the
standard 450-mil-wide SOIC, TSOP, and STSOP packages.
Writing to the device is accomplished by taking chip enable
one (CE1) and write enable (WE) inputs LOW and the chip
enable two (CE2) input HIG H. Data on the eight I/O pins (I/O0
through I/O7) is then wri tten into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the mem or y location speci-
fied by the addre ss pins will appear on the I/O pins .
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) , or
during a write operati on (CE1 LOW , CE2 HIGH, and WE LOW).
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
2
I/O
1
I/O
2
I/O
3
512x256x8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A0
CE
1
62128V-1
62128V-2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I / STSOP
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
(not to scale)
Top View
Reve rs e Pin o ut
62128V-3 62128V-4
CY62128V Family
2
Maximum Ratings
(Abov e which the usefu l l ife may be imp air ed. For user guide-
li nes, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Appl ied..... ....... ....... ............ ........... .....55° C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)........................................... –0.5V to +4.6V
DC Voltag e Appli ed to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current................. ..... ............ .......... ....... . >200 mA
Notes:
1. VIL (min.) = -2.0V f or pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C .
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70° C 1.6V to 3.6V
Industrial –40°C to +85° C 1.6V to 3.6V
Pr oduc t Portf olio
VCC Range
P ower Dissipation (Commercial)
Operating (Icc)St andby (ISB2)
Product Min. Typ.[2] Max. Speed Typ.[2] Maximum Typ.[2] Maximum
CY62128V 2.7V 3.0V 3.6V 70 ns 20 mA 40 m A 0.4 µA 100 µA (15 µA = LL)
CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 m A 0.3 µA50 µA (10 µA = LL)
CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 m A 0.3 µA30 µA (10 µA = LL)
Electrical Characteristics Over the Ope rating Range
CY62128V-70
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Ou tput HI GH Vo ltage VCC = Min., I OH = –1.0 mA 2.4 V
VOL O utput LOW Voltage VCC = Min. , I OL = 2.1 mA 0.4 V
VIH Input HIGH Vol tage 2 VCC
+0.5V V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Load Current GND < VI < VCC –1 ±1 +1 µA
IOZ Output Leakage Current GND < VO < VCC, Output
Disabled –1 ±1 +1 µA
ICC VCC Operating Supply
Current VCC = Max.,
IOUT = 0 mA ,
f = fMAX = 1/t RC
Com’l L 20 40 mA
LL
Ind’l L
LL
ISB1 Automatic CE
Power-Down Current—
TTL In puts
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
Com’l L 15 300 µA
LL
Ind’l L
LL
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
Com’l L 0.4 100 µA
LL 15 µA
Ind’l L 100 µA
LL 30 µA
CY62128V Family
3
Electrical Characteristics Over the Ope rating Range
CY62128V25-100 CY62128V18-200
Parameter Description T est Conditions Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
VOH Ou tput HI GH Vo ltage VCC = Mi n ., IOH = –0.1 mA 2.4 0.8*
Vcc V
VOL O utput LOW Voltage VCC = M i n ., IOL = 0.1 mA 0.4 0.2 V
VIH Input HIGH Vol tage 2 VCC
+0.5 0.7*
VCC VCC
+0.3 V
VIL Input LOW Voltage –0.5 0.8 –0.5 0.3*
VCC V
IIX Input Load Current GND < VI < VCC –1 ±1 +1 –1 ±0.1 +1 µA
IOZ Output Leakage Current GND < VO < VCC, Output
Disabled –1 ±1 +1 –1 ±0.1 +1 µA
ICC VCC Operating Supply
Current VCC = Ma x .,
IOUT = 0 mA,
f = fMAX = 1/tRC
L15 20 10 15 mA
LL
ISB1 Automatic CE
Power-Down Current—
TTL In puts
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
L15 300 5 100 µA
LL
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
L 0.4 50 0.4 30 µA
LL 12 10 µA
Indust’l Temp Range LL 24 20 µA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitanc e TA = 25°C, f = 1 MHz,
VCC = 3.0V 6pF
COUT Output Capacitance 8 pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
CY62128V Family
4
AC Test Loads and Waveforms
1.8V
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
62128V–5 62128V–6
RTH
R1
Parameters 3.3V 2.5V 1.8V Unit
R1 1213 15909 10800 Ohms
R2 1378 4487 4154 Ohms
RTH 645 3500 3000 Ohms
VTH 1.75V 0.55V 0.50V Volts
Data Retention Characteristics (Ov er the Operating Range)
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC for Data Retentio n 1.4 V
ICCDR Dat a Retention Current Com’l L VCC = 1.6V
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
0.4 10 µA
LL 10 µA
Ind’l L 20 µA
LL 20 µA
tCDR[3] Chip Desel ect to Data Retention Time 0 ns
tROperation Recovery Time tRC ns
Data Retention Waveform
Note:
4. No input may exceed VCC+0.3V.
C62128V–7
1.8V1.8V
tCDR
VDR >1.4 V
DATA RETENTION MODE
tR
CE
VCC
CY62128V Family
5
Swi tch i ng C h ara cteri sti cs Over the Operating Range[5]
CY62128V-70 CY62128V25-100 CY62128V18-200
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 70 100 200 ns
tAA Address to Data Valid 70 100 200 ns
tOHA Data Hold from Address Change 10 10 10 ns
tACE CE LOW to Data Valid 70 100 200 ns
tDOE OE LOW to Data Valid 35 75 125 ns
tLZOE OE LOW to Low Z[6] 10 10 10 ns
tHZOE OE HIGH to High Z[6, 7] 25 50 75 ns
tLZCE CE LOW to Low Z[6] 10 10 10 ns
tHZCE CE HIGH to High Z[6, 7] 25 50 75 ns
tPU CE LOW to Pow er-Up 0 0 0 ns
tPD CE HIGH to Power-Do wn 70 100 200 ns
WRITE C YCLE[8,9]
tWC Write Cycl e Time 70 100 200 ns
tSCE CE LOW to Write End 60 100 190 ns
tAW Address Set-Up to Wr ite End 60 100 190 ns
tHA Address Ho ld f rom Writ e End 0 0 0 ns
tSA Address Set-Up to Wr ite Star t 0 0 0 ns
tPWE WE Pulse Width 55 90 125 ns
tSD Data Se t-Up to Writ e End 30 60 100 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE WE LOW to High Z[6, 7] 25 50 100 ns
tLZWE WE HIGH to Low Z[6] 510 15 ns
Swi tch i ng Waveform s
Notes:
5. Test conditions assume signal transition time of 5 ns or less timing reference le vels of 1.5V, input pulse le vels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100- pF l oad capaci tance .
6. At any given temperature and voltage condition, tHZCE is le ss than tLZCE, tHZOE is less than tLZOE, and t HZWE is less than tLZWE f or any given d e vice .
7. tHZOE, tHZCE, and t HZWE are sp ecified wi th CL = 5 pF as in part (b) of A C Test Loads . Transi tion is measured ± 200 mV f rom steady-stat e vo lt age.
8. The internal write time of the memory is defined b y the overlap of CE1 LO W, CE2 H IGH and WE LOW . CE1 and WE sign als must be LOW and CE2 HIGH to initiate
a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, O E LO W) is the sum of t HZWE and tSD.
10. Device is continuously selected. OE, CE = VIL, CE2=VIH.
11. WE is HIGH fo r r ead cycle .
Read Cycle No.1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
62128V–8
[10, 11]
CY62128V Family
6
Read Cycle No. 2 ( OE Controlled) [11,12]
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
Notes:
12. Address valid prior to or coincident with CE1 transi tion LO W and C E2 tr ansiti on HIG H.
13. Data I/O is high impedance if O E = VIH.
14. If CE1 goes HIGH or CE2 goes L OW s imultan eous ly with W E HI GH, the output remains in a high- impedan ce st ate.
Swi tch i ng Waveform s (continued)
62128V-9
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
62128V-10
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
CY62128V Family
7
Truth Table
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
Swi tch i ng Waveform s (continued)
62128V-11
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE15
CE1CE2OE WE I/O0–I/O7Mode Power
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
CY62128V Family
8
Ordering Information
Speed
(ns) Ordering Code Package
Name Pac kage Type Operating
Range
70 CY62128VL-70SC S34 32-Lead 450-Mil SOIC Commercial
CY62128VLL-70SC S34
CY62128VL-70ZC Z32 32-Lead TSOP Type 1
CY62128VLL-70ZC Z32
CY62128VL-70ZAC ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAC ZA32
CY62128VL-70ZRC ZR32 32-Lead Reve rse TSOP 1
CY62128VLL-70ZRC ZR32
70 CY62128VL-70SI S34 32-Lead 450-Mil SOIC Industrial
CY62128VLL-70SI S34
CY62128VL-70ZI Z32 32-Lead TSOP Type 1
CY62128VLL-70ZI Z32
CY62128VL-70ZAI ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAI ZA32
CY62128VL-70ZRI ZR32 32-Lead Reve rse TSOP 1
CY62128VLL-70ZRI ZR32
100 CY62128V25L-100SC S34 32-Lead 450-Mil SOIC Commercial
CY62128V25LL-100SC S34
CY62128V25L-100ZC Z32 32-Lead TSOP Type 1
CY62128V25LL-100ZC Z32
CY62128V25L-100ZAC ZA32 32-Lead STSOP Typ e 1
CY62128V25LL-100ZAC ZA32
CY62128V25L-100ZRC ZR32 32-Lead Rev erse TSOP 1
CY62128V25LL-100ZRC ZR32
100 CY62128V25L-100SI S34 32-Lead 450-Mil SOIC Industrial
CY62128V25LL-100SI S34
CY62128V25L-100ZI Z32 32-Lead TSOP Type 1
CY62128V25LL-100ZI Z32
CY62128V25L-100ZAI ZA32 32-Lead STSO P Type 1
CY62128V25LL-100ZAI ZA32
CY62128V25L-100ZRI ZR32 32-Lead Rev erse TSOP 1
CY62128V25LL-100ZRI ZR32
200 CY62128V18L-200SC S34 32-Lead 450-Mil SOIC Commercial
CY62128V18LL-200SC S34
CY62128V18L-200ZC Z32 32-Lead TSOP Type 1
CY62128V18LL-200ZC Z32
CY62128V18L-200ZAC ZA32 32-Lead STSOP Typ e 1
CY62128V18LL-200ZAC ZA32
CY62128V18L-200ZRC ZR32 32-Lead Rev erse TSOP 1
CY62128V18LL-200ZRC ZR32
CY62128V Family
9
Document #: 38- 00547-A
200 CY62128V18L-200SI S34 32-Lead 450-Mil SOIC Industrial
CY62128V18LL-200SI S34
CY62128V18L-200ZI Z32 32-Lead TSOP Type 1
CY62128V18LL-200ZI Z32
CY62128V18L-200ZAI ZA32 32-Lead STSO P Type 1
CY62128V18LL-200ZAI ZA32
CY62128V18L-200ZRI ZR32 32-Lead Rev erse TSOP 1
CY62128V18LL-200ZRI ZR32
Ordering Information (continued)
Speed
(ns) Ordering Code Package
Name Pac kage Type Operating
Range
CY62128V Family
10
Package Di ag ra ms
32-Lead (450 Mil) Molded SOIC S32
32-Lead Thin Small Outline Package Z32
CY62128V Family
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
32-Lead Reverse Thin Small O utline Package ZR32
Package Di ag ra ms (continued)
32-Lead Thin Small Outline Package ZA32
Shrunk
11.70 (.461)
11.90 (.469)
13.20 (. 520)
13.60 (. 535)
