AT25128B/AT25256B
SPI Serial EEPROM 128 Kbits (16,384 x 8)
and 256 Kbits (32,768 x 8)
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1):
Data sheet describes mode 0 operation
Low-Voltage Operation:
1.8V (VCC = 1.8V to 5.5V)
Industrial Temperature Range: -40°C to +85°C
20 MHz Clock Rate (5V)
64Byte Page Mode
Block Write Protection:
Protect 1/4, 1/2 or entire array
Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data
Protection
Self-Timed Write Cycle within 5 ms Maximum
ESD Protection > 4,000V
High Reliability:
Endurance: 1,000,000 write cycles
Data retention: 100 years
Green (Lead-free/Halide-free/RoHS Compliant) Package Options
Die Sale Options: Wafer Form and Bumped Wafers
Packages
8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 8-Ball VFBGA
© 2019 Microchip Technology Inc. DS20006193A-page 1
Table of Contents
Features.......................................................................................................................... 1
Packages.........................................................................................................................1
1. Package Types (not to scale).................................................................................... 4
2. Pin Description.......................................................................................................... 5
2.1. Chip Select (CS)...........................................................................................................................5
2.2. Serial Data Output (SO)............................................................................................................... 5
2.3. Write-Protect (WP)....................................................................................................................... 5
2.4. Ground (GND).............................................................................................................................. 5
2.5. Serial Data Input (SI)....................................................................................................................6
2.6. Serial Data Clock (SCK)...............................................................................................................6
2.7. Suspend Serial Input (HOLD).......................................................................................................6
2.8. Device Power Supply (VCC)......................................................................................................... 6
3. Description.................................................................................................................7
3.1. SPI Bus Master Connections to Serial EEPROMs.......................................................................7
3.2. Block Diagram.............................................................................................................................. 8
4. Electrical Characteristics........................................................................................... 9
4.1. Absolute Maximum Ratings..........................................................................................................9
4.2. DC and AC Operating Range.......................................................................................................9
4.3. DC Characteristics....................................................................................................................... 9
4.4. AC Characteristics......................................................................................................................10
4.5. SPI Synchronous Data Timimg.................................................................................................. 13
4.6. Electrical Specifications..............................................................................................................13
5. Device Operation.....................................................................................................15
5.1. Interfacing the AT25128B/AT25256B on the SPI Bus................................................................ 15
5.2. Device Opcodes......................................................................................................................... 16
5.3. Hold Function............................................................................................................................. 16
5.4. Write Protection..........................................................................................................................17
6. Device Commands and Addressing........................................................................ 18
6.1. STATUS Register Bit Definition and Function............................................................................ 18
6.2. Read STATUS Register (RDSR).................................................................................................19
6.3. Write Enable (WREN) and Write Disable (WRDI)........................................................................19
6.4. Write STATUS Register (WRSR)................................................................................................. 20
7. Read Sequence.......................................................................................................23
8. Write Sequence....................................................................................................... 24
8.1. Byte Write...................................................................................................................................24
8.2. Page Write..................................................................................................................................25
AT25128B/AT25256B
© 2019 Microchip Technology Inc. DS20006193A-page 2
8.3. Polling Routine........................................................................................................................... 25
9. Packaging Information.............................................................................................27
9.1. Package Marking Information.....................................................................................................27
10. Revision History.......................................................................................................37
The Microchip Web Site................................................................................................ 38
Customer Change Notification Service..........................................................................38
Customer Support......................................................................................................... 38
Product Identification System........................................................................................39
Microchip Devices Code Protection Feature................................................................. 39
Legal Notice...................................................................................................................40
Trademarks................................................................................................................... 40
Quality Management System Certified by DNV.............................................................41
Worldwide Sales and Service........................................................................................42
AT25128B/AT25256B
© 2019 Microchip Technology Inc. DS20006193A-page 3
1. Package Types (not to scale)
8-Lead SOIC/TSSOP
(Top View)
CS 1
2
3
4
8
7
6
5
SO
WP
GND
Vcc
HOLD
SCK
SI
CS
SO
WP
GND
Vcc
HOLD
SCK
SI
8-Pad UDFN
(Top View)
1
2
3
4 5
6
7
8
1
2
3
4
8
7
6
5
CS
SO
WP
GND
Vcc
HOLD
SCK
SI
8-Ball VFBGA
(Top View)
AT25128B/AT25256B
Package Types (not to scale)
© 2019 Microchip Technology Inc. DS20006193A-page 4
2. Pin Description
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name 8-Lead SOIC 8-Lead TSSOP 8-Pad UDFN(1)8-Ball VFBGA Function
CS 1 1 1 1 Chip Select
SO 2 2 2 2 Serial Data Output
WP(2)3 3 3 3 Write-Protect
GND 4 4 4 4 Ground
SI 5 5 5 5 Serial Data Input
SCK 6 6 6 6 Serial Data Clock
HOLD(2)7 7 7 7 Suspends Serial Input
VCC 8 8 8 8 Device Power Supply
Note: 
1. The exposed pad on this package can be connected to GND or left floating.
2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.
2.1 Chip Select (CS)
The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will
remain in a high-impedance state.
To ensure robust operation, the CS pin should follow VCC upon power-up. It is therefore recommended to
connect CS to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on
CS is required prior to any sequence being initiated.
2.2 Serial Data Output (SO)
The Serial Data Output (SO) pin is used to transfer data out of the AT25128B/AT25256B. During a read
sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).
2.3 Write-Protect (WP)
The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is
brought low and WPEN bit is set to a logic ‘1’, all write operations to the STATUS register are inhibited.
WP going low while CS is still low will interrupt a write operation to the STATUS register. If the internal
write cycle has already been initiated, WP going low will have no effect on any write operation to the
STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to a
logic ‘0’. This will allow the user to install the AT25128B/AT25256B in a system with the WP pin tied to
ground and still be able to write to the STATUS register. All WP pin functions are enabled when the
WPEN bit is set to a logic ‘1’.
2.4 Ground (GND)
The ground reference for the Device Power Supply (VCC). The Ground (GND) pin should be connected to
the system ground.
AT25128B/AT25256B
Pin Description
© 2019 Microchip Technology Inc. DS20006193A-page 5
2.5 Serial Data Input (SI)
The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses
and data. Data is latched on the rising edge of the Serial Data Clock (SCK).
2.6 Serial Data Clock (SCK)
The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the
AT25128B/AT25256B. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched
in on the rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling
edge of SCK.
2.7 Suspend Serial Input (HOLD)
The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the
AT25128B/AT25256B. When the device is selected and a serial sequence is underway, HOLD can be
used to pause the serial communication with the master device without resetting the serial sequence. To
pause, the HOLD pin must be brought low while the Serial Data Clock (SCK) pin is low. To resume serial
communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the Serial Data Input (SI) pin will be ignored while the Serial Data Output (SO) pin will
be in the highimpedance state.
2.8 Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at
invalid VCC voltages may produce spurious results and should not be attempted.
AT25128B/AT25256B
Pin Description
© 2019 Microchip Technology Inc. DS20006193A-page 6
3. Description
The AT25128B/AT25256B provides 131,072/262,144 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 16,384/32,768 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where lowpower and
lowvoltage operation are essential. The device is available in space-saving 8lead SOIC, 8lead TSSOP,
8pad UDFN and 8ball VFBGA packages. All packages operate from 1.8V to 5.5V.
3.1 SPI Bus Master Connections to Serial EEPROMs
SPI Master:
Microcontroller
Slave 0
AT25XXX
Data Clock (SCK)
Data Output (SO)
Data Input (SI)
CS3 CS2 CS1 CS0
SI SO SCK
CS
Slave 1
AT25XXX
SI SO SCK
Slave 2
AT25XXX
SI SO SCK
Slave 3
AT25XXX
SI SO SCK
CS
CSCS
AT25128B/AT25256B
Description
© 2019 Microchip Technology Inc. DS20006193A-page 7
3.2 Block Diagram
GND
Memory
System Control
Module
High-Voltage
Generation
Circuit
Address Register
and Counter
Write Protection
Control
VCC
SCK
SI
Power-on
Reset
Generator
Row Decoder
Data Register
SO
Pause
Operation
Control
Register Bank:
STATUS Register
Data Output
Buffer
CS
WP
HOLD
1 page
EEPROM Array
Column Decoder
AT25128B/AT25256B
Description
© 2019 Microchip Technology Inc. DS20006193A-page 8
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Operating temperature -55°C to +125°C
Storage temperature -65°C to +150°C
Voltage on any pin with respect to ground -1.0V to +7.0V
VCC 6.25V
DC output current 5.0 mA
ESD protection > 4 kV
Note:  Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
4.2 DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT25128B/AT25256B
Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C
VCC Power Supply Low-Voltage Grade 1.8V to 5.5V
4.3 DC Characteristics
Table 4-2. DC Characteristics(1)
Parameter Symbol Minimum Typical Maximum Units Conditions
Supply Voltage VCC1 1.8 5.5 V
Supply Voltage VCC2 2.5 5.5 V
Supply Voltage VCC3 4.5 5.5 V
Supply Current ICC1 9.0 10.0 mA VCC = 5.0V at 20 MHz,
SO = Open, Read
Supply Current ICC2 5.0 7.0 mA VCC = 5.0V at 10 MHz,
SO = Open, Read, Write
Supply Current ICC3 2.2 3.5 mA VCC = 5.0V at 1 MHz,
SO = Open, Read, Write
Standby Current ISB1 0.2 3.0 µA VCC = 1.8V, CS = VCC
AT25128B/AT25256B
Electrical Characteristics
© 2019 Microchip Technology Inc. DS20006193A-page 9
...........continued
Parameter Symbol Minimum Typical Maximum Units Conditions
Standby Current ISB2 0.5 3.0 µA VCC = 2.5V, CS = VCC
Standby Current ISB3 2.0 5.0 µA VCC = 5.0V, CS = VCC
Input Leakage IIL -3.0 3.0 µA VIN = 0V to VCC
Output Leakage IOL -3.0 3.0 µA VIN = 0V to VCC,
TAC = 0°C to +70°C
Input
Low-Voltage
VIL(2)-1.0 VCC x 0.3 V
Input
High-Voltage
VIH(2)VCC x 0.7 VCC + 0.5 V
Output
Low-Voltage
VOL1 0.4 V 3.6V ≤ VCC ≤ 5.5V IOL = 3.0 mA
Output
High-Voltage
VOH1 VCC - 0.8 V 3.6V ≤ VCC ≤ 5.5V IOH = -1.6 mA
Output
Low-Voltage
VOL2 0.2 V 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA
Output
High-Voltage
VOH2 VCC - 0.2 V 1.8V ≤ VCC ≤ 3.6V IOH = -100 µA
Note: 
1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.8V to 5.5V
(unless otherwise noted).
2. VIL min and VIH max are reference only and are not tested.
4.4 AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter Symbol Minimum Maximum Units Conditions
SCK Clock Frequency fSCK 0 20 MHz VCC = 4.5V to 5.5V
0 10 MHz VCC = 2.5V to 5.5V
0 5 MHz VCC = 1.8V to 5.5V
Input Rise Time tRI 2000 ns VCC = 4.5V to 5.5V
2000 ns VCC = 2.5V to 5.5V
2000 ns VCC = 1.8V to 5.5V
AT25128B/AT25256B
Electrical Characteristics
© 2019 Microchip Technology Inc. DS20006193A-page 10
...........continued
Parameter Symbol Minimum Maximum Units Conditions
Input Fall Time tFI 2000 ns VCC = 4.5V to 5.5V
2000 ns VCC = 2.5V to 5.5V
2000 ns VCC = 1.8V to 5.5V
SCK High Time tWH 20 ns VCC = 4.5V to 5.5V
40 ns VCC = 2.5V to 5.5V
80 ns VCC = 1.8V to 5.5V
SCK Low Time tWL 20 ns VCC = 4.5V to 5.5V
40 ns VCC = 2.5V to 5.5V
80 ns VCC = 1.8V to 5.5V
CS High Time tCS 100 ns VCC = 4.5V to 5.5V
100 ns VCC = 2.5V to 5.5V
200 ns VCC = 1.8V to 5.5V
CS Setup Time tCSS 100 ns VCC = 4.5V to 5.5V
100 ns VCC = 2.5V to 5.5V
200 ns VCC = 1.8V to 5.5V
CS Hold Time tCSH 100 ns VCC = 4.5V to 5.5V
100 ns VCC = 2.5V to 5.5V
200 ns VCC = 1.8V to 5.5V
Data In Setup Time tSU 5 ns VCC = 4.5V to 5.5V
10 ns VCC = 2.5V to 5.5V
20 ns VCC = 1.8V to 5.5V
Data In Hold Time tH5 ns VCC = 4.5V to 5.5V
10 ns VCC = 2.5V to 5.5V
20 ns VCC = 1.8V to 5.5V
HOLD Setup Time tHD 5 ns VCC = 4.5V to 5.5V
10 ns VCC = 2.5V to 5.5V
20 ns VCC = 1.8V to 5.5V
HOLD Hold Time tCD 5 ns VCC = 4.5V to 5.5V
10 ns VCC = 2.5V to 5.5V
20 ns VCC = 1.8V to 5.5V
AT25128B/AT25256B
Electrical Characteristics
© 2019 Microchip Technology Inc. DS20006193A-page 11
...........continued
Parameter Symbol Minimum Maximum Units Conditions
Output Valid tV0 20 ns VCC = 4.5V to 5.5V
0 40 ns VCC = 2.5V to 5.5V
0 80 ns VCC = 1.8V to 5.5V
Output Hold Time tHO 0 ns VCC = 4.5V to 5.5V
0 ns VCC = 2.5V to 5.5V
0 ns VCC = 1.8V to 5.5V
HOLD to Output Low Z tLZ 0 25 ns VCC = 4.5V to 5.5V
0 50 ns VCC = 2.5V to 5.5V
0 100 ns VCC = 1.8V to 5.5V
HOLD to Output High Z tHZ 25 ns VCC = 4.5V to 5.5V
50 ns VCC = 2.5V to 5.5V
100 ns VCC = 1.8V to 5.5V
Output Disable Time tDIS 25 ns VCC = 4.5V to 5.5V
50 ns VCC = 2.5V to 5.5V
100 ns VCC = 1.8V to 5.5V
Write Cycle Time tWC 5 ms VCC = 4.5V to 5.5V
5 ms VCC = 2.5V to 5.5V
5 ms VCC = 1.8V to 5.5V
Note: 
1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
AT25128B/AT25256B
Electrical Characteristics
© 2019 Microchip Technology Inc. DS20006193A-page 12
4.5 SPI Synchronous Data Timimg
tDIS
tHO
tCSH
tCS
tV
tH
VOH
VOL
High
Impedance
Valid Data In
tWH
VIH
VIH
VIL
tCSS
tWL
SCK
SI
SO
CS
VIL
VIH
VIL
tSU
High
Impedance
4.6 Electrical Specifications
4.6.1 Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT25128B/AT25256B should monotonically rise
from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.6.1.1 Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT25128B/AT25256B includes a Power-on Reset (POR) circuit. Upon power-up, the
device will not respond to any instructions until the VCC level crosses the internal voltage threshold (VPOR)
that brings the device out of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has
reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is
greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the
first instruction to the device. See Table 4-4 for the values associated with these power-up parameters.
Table 4-4. Power-Up Conditions(1)
Symbol Parameter Min. Max. Units
tPUP Time required after VCC is stable before the device can accept instructions 100 µs
VPOR Power-on Reset Threshold Voltage 1.5 V
tPOFF Minimum time at VCC = 0V between power cycles 0.03 ms
Note: 
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT25128B/AT25256B drops below
the maximum VPOR level specified, it is recommended that a full-power cycle sequence be performed by
first driving the VCC pin to GND in less than 1 ms, waiting at least the minimum tPOFF time and then
performing a new power-up sequence in compliance with the requirements defined in this section.
AT25128B/AT25256B
Electrical Characteristics
© 2019 Microchip Technology Inc. DS20006193A-page 13
4.6.2 Pin Capacitance
Table 4-5. Pin Capacitance(1,2)
Symbol Test Condition Max. Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V
Note: 
1. This parameter is characterized but is not 100% tested in production.
2. Applicable over recommended operating range from: TA = 25°C, fSCK = 1.0 MHz, VCC = 5.0V
(unless otherwise noted).
4.6.3 EEPROM Cell Performance Characteristics
Table 4-6. EEPROM Cell Performance Characteristics
Operation Test Condition Min. Max. Units
Write Endurance(1)TA = 25°C, VCC = 3.3V,
Page Write mode
1,000,000 Write Cycles
Data Retention(1)TA = 55°C 100 Years
Note: 
1. Performance is determined through characterization and the qualification process.
4.6.4 Software Reset
The SPI interface of the AT25128B/AT25256B can be reset by toggling the CS input. If the CS line is
already in the active state, it must complete a transition from the inactive state (≥VIH) to the active state
(≤VIL) and then back to the inactive state (≥VIH) without sending clocks on the SCK line. Upon completion
of this sequence, the device will be ready to receive a new opcode on the SI line.
4.6.5 Device Default State at Power-Up
The AT25128B/AT25256B default state upon power-up consists of:
Standby Power mode
A high-to-low-level transition on CS is required to enter active state
Write Enable Latch (WEL) bit in the STATUS register = 0
Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command
Device is not selected
Not in Hold condition
WPEN, BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the
fact that they are nonvolatile values
4.6.6 Device Default Condition
The AT25128B/AT25256B is shipped from Microchip to the customer with the EEPROM array set to an all
FFh data pattern (logic ‘1’ state). The Write-Protect Enable bit in the STATUS register is set to logic ‘0
(the ability of the EEPROM array to write is dictated by the values of the Block WriteProtect bits while the
STATUS register’s ability to write is controlled by the WEL bit). The Block Write Protection bits in the
STATUS register are set to logic ‘0’ (no write protection selected).
AT25128B/AT25256B
Electrical Characteristics
© 2019 Microchip Technology Inc. DS20006193A-page 14
5. Device Operation
The AT25128B/AT25256B is controlled by a set of instructions that are sent from a host controller,
commonly referred to as the SPI Master. The SPI Master communicates with the AT25128B/AT25256B
via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial
Data Input (SI), and Serial Data Output (SO).
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI
bus. The AT25128B/AT25256B supports the two most common modes, SPI Modes 0 and 3. With SPI
Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the
inactive state (when the SPI Master is in Standby mode and not transferring any data). SPI Mode 0 is
defined as a low SCK while CS is not asserted (at VCC) and SPI Mode 3 has SCK high in the inactive
state. The SCK Idle state must match when the CS is deasserted both before and after the
communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with a solid
line on SCK while CS is inactive and Mode 3 with a dotted line.
Figure 5-1. SPI Mode 0 and Mode 3
SO
SI
SCK
CS
MSB LSB
MSB LSB
Mode 0
Mode 3
Mode 0
Mode 3
5.1 Interfacing the AT25128B/AT25256B on the SPI Bus
Communication to and from the AT25128B/AT25256B must be initiated by the SPI Master device, such
as a microcontroller. The SPI Master device must generate the serial clock for the AT25128B/AT25256B
on the Serial Data Clock (SCK) pin. The AT25128B/AT25256B always operates as a slave due to the fact
that the SCK is always an input.
5.1.1 Selecting the Device
The AT25128B/AT25256B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin
will remain in a highimpedance state.
5.1.2 Sending Data to the Device
The AT25128B/AT25256B uses the SI pin to receive information. All instructions, addresses and data
input bytes are clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the
first rising edge of the SCK line after the CS has been asserted.
AT25128B/AT25256B
Device Operation
© 2019 Microchip Technology Inc. DS20006193A-page 15
5.1.3 Receiving Data from the Device
Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is
latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the
Read from Memory Array (READ) and Read STATUS Register (RDSR) instructions. See Read Sequence
for more details.
5.2 Device Opcodes
5.2.1 Serial Opcode
After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte
contains the opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes
that the AT25128B/AT25256B will respond to.
5.2.2 Invalid Opcode
If an invalid opcode is received, no data will be shifted into AT25128B/AT25256B and the SO pin will
remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the
serial communication.
5.3 Hold Function
The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without
having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the
internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the
operation and the write cycle will continue to completion.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by
asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse,
then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will
remain in the Hold mode as long as the HOLD pin and CS pin are asserted.
While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the
SCK pin will be ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in
the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the
SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end
until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been
started will be aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0
state.
AT25128B/AT25256B
Device Operation
© 2019 Microchip Technology Inc. DS20006193A-page 16
Figure 5-2. Hold Mode
HOLD
SCK
CS
Hold HoldHold
Figure 5-3. Hold Timing
HOLD
SO
SCK
CS
tCD tCD
tHD
tHD
t
LZ
tHZ
5.4 Write Protection
The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin
is brought low and WPEN bit is a logic ‘1’, all write operations to the STATUS register are inhibited. The
WP pin going low while CS is still low will interrupt a Write STATUS Register (WRSR). If the internal write
cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS
register. The WP pin function is blocked when the WPEN bit in the STATUS register is a logic ‘0’. This will
allow the user to install the AT25128B/AT25256B device in a system with the WP pin tied to ground and
still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to
a logic ‘1’.
AT25128B/AT25256B
Device Operation
© 2019 Microchip Technology Inc. DS20006193A-page 17
6. Device Commands and Addressing
The AT25128B/AT25256B is designed to interface directly with the synchronous Serial Peripheral
Interface (SPI). The AT25128B/AT25256B utilizes an 8bit instruction register. The list of instructions and
their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with
the MSb first and start with a hightolow CS transition.
Table 6-1. Instruction Set for the AT25128B/AT25256B
Instruction Name Instruction Format Operates On Operation Description
WREN 0000 X110 STATUS Register Set Write Enable Latch (WEL)
WRDI 0000 X100 STATUS Register Reset Write Enable Latch (WEL)
RDSR 0000 X101 STATUS Register Read STATUS Register
WRSR 0000 X001 STATUS Register Write STATUS Register
READ 0000 X011 Memory Array Read from Memory Array
WRITE 0000 X010 Memory Array Write to Memory Array
6.1 STATUS Register Bit Definition and Function
The AT25128B/AT25256B includes an 8bit STATUS register. The STATUS register bits modulate various
features of the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific
instructions that are detailed in the following sections.
Table 6-2. STATUS Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEL RDY/BSY
Table 6-3. STATUS Register Bit Definition
Bit Name Type Description
7 WPEN Write-Protect Enable R/W 0See Table 6-5 (Factory Default)
1See Table 6-5 (Factory Default)
6:4 RFU Reserved for Future Use R 0Reads as zeros when the device is not in a write
cycle
1Reads as ones when the device is in a write cycle
3:2 BP1
BP0
Block Write Protection R/W 00 No array write protection (Factory Default)
01 Quarter array write protection (see Table 6-4)
10 Half array write protection (see Table 6-4)
11 Entire array write protection (see Table 6-4)
1 WEL Write Enable Latch R/W 0Device is not write enabled (Power-up Default)
1Device is write enabled
AT25128B/AT25256B
Device Commands and Addressing
© 2019 Microchip Technology Inc. DS20006193A-page 18
...........continued
Bit Name Type Description
0 RDY/BSY Ready/Busy Status R 0Device is ready for a new sequence
1Device is busy with an internal operation
6.2 Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy
and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block
Write Protection (BP<1:0>) bits indicate the extent of memory array protection employed. The STATUS
register is read by asserting the CS pin, followed by sending in a 05h opcode on the SI pin. Upon
completion of the opcode, the device will return the 8bit STATUS register value on the SO pin.
Figure 6-1. RDSR Waveform
SO
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STATUS Register Data Out
High-Impedance
SI
MSB
RDSR Opcode (05h)
0 0 0 0 0 1 0 1
MSB
D7 D6 D5 D4 D3 D2 D1
D0
6.3 Write Enable (WREN) and Write Disable (WRDI)
Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the
Write Enable (WREN) instruction and the Write Disable (WRDI) instruction. These functions change the
status of the WEL bit in the STATUS register.
6.3.1 Write Enable Instruction (WREN)
The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write
STATUS Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by
sending a WREN (06h) instruction to the AT25128B/AT25256B. First, the CS pin is driven low to select the
device and then a WREN instruction is clocked in on the SI pin. Then the CS pin can be driven high and
the WEL bit will be updated in the STATUS register to a logic ‘1’. The device will powerup in the write
disable state (WEL = 0).
AT25128B/AT25256B
Device Commands and Addressing
© 2019 Microchip Technology Inc. DS20006193A-page 19
Figure 6-2. WREN Timing
6.3.2 Write Disable Instruction (WRDI)
To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h)
disables all programming modes by setting the WEL bit to a logic ‘0’. The WRDI instruction is independent
of the status of the WP pin.
Figure 6-3. WRDI Timing
SO
SCK
CS
High-Impedance
SI
MSB
WRDI Opcode (04h)
0 0 0 0 0 1 0 0
0 1 2 3 4 5 6 7
6.4 Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the
STATUS register. Before a WRSR instruction can be initiated, a WREN instruction must be executed to set
the WEL to logic ‘1’. Upon completion of a WREN instruction, a WRSR instruction can be executed.
Note:  The WRSR instruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only
bit 7, bit 3 and bit 2 can be changed via the WRSR instruction. These modifiable bits are the Write Protect
Enable (WPEN) and Block Protect (BP<1:0>) bits. These three bits are nonvolatile bits that have the
same properties and functions as regular EEPROM cells. Their values are retained while power is
removed from the device.
AT25128B/AT25256B
Device Commands and Addressing
© 2019 Microchip Technology Inc. DS20006193A-page 20
The AT25128B/AT25256B will not respond to commands other than a RDSR after a WRSR instruction until
the self-timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the
STATUS register is reset to logic ‘0’.
Figure 6-4. WRSR Waveform
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STATUS Register Data In
High-Impedance
MSB
WRSR Opcode (01h)
0 0 0 0 0 0 0 1
MSB
D7 X X X D3
D2
X
X
SO
SI
t
WC
(1)
Note: 
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
6.4.1 Block Write-Protect Function
The WRSR instruction allows the user to select one of four possible combinations as to how the memory
array will be inhibited from writing through changing the Block Write-Protect bits (BP<1:0>). The four
levels of array protection are:
None of the memory array is protected.
Upper quarter (¼) address range is write-protected meaning the highest order address bits are read-
only.
Upper half (½) address range is write-protected meaning the highest order address bits are read-
only.
All of the memory array is write-protected meaning all address bits are read-only.
The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.
Table 6-4. Block Write-Protect Bits
Level STATUS Register Bits Write-Protected/ReadOnly Address Range
BP1 BP0 AT25128B AT25256B
00 0 None None
1(1/4) 0 1 3000h-3FFFh 6000h-7FFFh
2(1/2) 1 0 2000h-3FFFh 4000h – 7FFFh
3(All) 1 1 0000h-3FFFh 0000h – 7FFFh
AT25128B/AT25256B
Device Commands and Addressing
© 2019 Microchip Technology Inc. DS20006193A-page 21
6.4.2 Write-Protect Enable Function
The WRSR instruction also allows the user to enable or disable the Write-Protect (WP) pin through the use
of the Write-Protect Enable (WPEN) bit. When the WPEN bit is set to logic ‘0’, the ability to write the
EEPROM array is dictated by the values of the Block Write-Protect (BP<1:0>) bits. The ability to write the
STATUS register is controlled by the WEL bit. When the WPEN bit is set to logic ‘1’, the STATUS register
is read-only.
Hardware Write Protection is enabled when both the WP pin is low and the WPEN bit has been set to a
logic ‘1’. When the device is Hardware WriteProtected, writes to the STATUS register, including the Block
WriteProtect , WEL and WPEN bits, and to the sections in the memory array selected by the Block
WriteProtect bits are disabled. When Hardware Write Protection is enabled, writes are only allowed to
sections of the memory that are not blockprotected.
Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is a logic ‘0’. When
Hardware Write Protection is disabled, writes are only allowed to sections of the memory that are not
blockprotected. Refer to Table 6-5 for additional information.
Note:  When the WPEN bit is Hardware WriteProtected, it cannot be set back to a logic ‘0’ as long as
the WP pin is held low.
Table 6-5. WPEN Operation
WPEN WP
Pin
WEL Protected Blocks Unprotected Blocks STATUS Register
0x0 Protected Protected Protected
0x1 Protected Writable Writable
1Low 0Protected Protected Protected
1Low 1Protected Writable Protected
xHigh 0Protected Protected Protected
xHigh 1Protected Writable Writable
AT25128B/AT25256B
Device Commands and Addressing
© 2019 Microchip Technology Inc. DS20006193A-page 22
7. Read Sequence
Reading the AT25128B/AT25256B via the SO pin requires the following sequence. After the CS line is
pulled low to select a device, the READ (03h) instruction is transmitted via the SI line followed by the
16bit address to be read. Refer to Table 7-1 for the address bits for AT25128B/AT25256B.
Table 7-1. AT25128B/AT25256B Address Bits
Address AT25128B AT25256B
ANA13–A0A14–A0
Don’t Care Bits A15–A14 A15
Upon completion of the 16bit address, any data on the SI line will be ignored. The data (D7D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highestorder address bit is
reached, the address counter will rollover to the lowestorder address bit allowing the entire memory to be
read in one continuous read cycle regardless of the starting address.
Figure 7-1. Read Waveform
SO
SI
SCK
MSB MSB
2 310
00000011
6 754 10 1198 12 27 2823 26252421 2219 20 29 30 31
READ Opcode (03h)
AAAA AAAAA
MSB MSB
DDDDDDDDDD
Address Bits A15-A0
Data Byte 1
High-Impedance
CS
AT25128B/AT25256B
Read Sequence
© 2019 Microchip Technology Inc. DS20006193A-page 23
8. Write Sequence
In order to program the AT25128B/AT25256B, two separate instructions must be executed. First, the
device must be write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write
sequences described in this section may be executed.
Note:  If the device is not Write Enabled (WREN), the device will ignore the WRITE instruction and will
return to the standby state when CS is brought high. A new CS assertion is required to reinitiate
communication.
The address of the memory location(s) to be programmed must be outside the protected address field
location selected by the block write protection level. During an internal write cycle, all commands will be
ignored except the RDSR instruction. Refer to Table 8-1 for the address bits for AT25128B/AT25256B.
Table 8-1. AT25128B/AT25256B Address Bits
Address AT25128B AT25256B
ANA13–A0A14–A0
Don’t Care Bits A15–A14 A15
8.1 Byte Write
A Byte Write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low
to select the device, the WRITE (02h) instruction is transmitted via the SI line followed by the 16bit
address and the data (D7D0) to be programmed. Programming will start after the CS pin is brought high.
The lowtohigh transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time
(Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25128B/AT25256B is automatically
returned to the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle.
Figure 8-1. Byte Write
SO
SI
SCK
CS
MSB MSB
2 310
00000010
6 754 10 1198 12 3129 3025 28272623 2421 22
WRITE Opcode (02h)
High-Impedance
AAAA AAAAA
MSB
D7 D6 D5 D4 D3 D2 D1 D0
Address Bits A15-A0 Data In
t
WC
(1)
Note: 
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
AT25128B/AT25256B
Write Sequence
© 2019 Microchip Technology Inc. DS20006193A-page 24
8.2 Page Write
A Page Write sequence allows up to 64 bytes to be written in the same write cycle, provided that all bytes
are in the same row of the memory array. Partial Page Writes of less than 64 bytes are allowed. After
each byte of data is received, the six lowest order address bits are internally incremented following the
receipt of each data byte. The higher order address bits are not incremented and retain the memory array
page location. If more bytes of data are transmitted that what will fit to the end of that memory row, the
address counter will rollover to the beginning of the same row. Nevertheless, creating a rollover event
should be avoided as previously loaded data in the page could become unintentionally altered. The
AT25128B/AT25256B is automatically returned to the Write Disable state (WEL = 0) at the completion of
a write cycle.
Figure 8-2. Page Write
SO
SI
SCK
MSB MSB
2 310
00000010
6 754 98 3129 3025 28272623 2421 22
WRITE Opcode (02h)
High-Impedance
A A A A AA
MSB
DDDDDDDD
Address Bits A15-A0 Data In Byte 1
MSB
DDDDDDDD
Data In Byte 64
CS
t
WC
(1)
Note: 
1. This instruction initiates a selftimed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
8.3 Polling Routine
A polling routine can be implemented to optimize timesensitive applications that would not prefer to wait
the fixed maximum write cycle time (tWC). This method allows the application to know immediately when
the write cycle has completed to start a subsequent operation.
Once the internally-timed write cycle has started, a polling routine can be initiated. This involves
repeatedly sending Read STATUS Register (RDSR) instruction to determine if the device has completed
its self-timed internal write cycle. If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still
in progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSR commands can
be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction.
Only the Read STATUS Register (RDSR) instruction is enabled during the write cycle.
AT25128B/AT25256B
Write Sequence
© 2019 Microchip Technology Inc. DS20006193A-page 25
Figure 8-3. Polling Flowchart
Send Valid
Write
Protocol
Deassert
CS to VCC to
Initiate a
Write Cycle
Send RDSR
Instruction
to the Device
Continue to
Next Operation
NO
YES
Does
RDY/BSY
= 0?
AT25128B/AT25256B
Write Sequence
© 2019 Microchip Technology Inc. DS20006193A-page 26