PI2DDR3212 14 bit 2:1 DDR3 Switch Features Description II14 bit 2:1 switch that supports up to 5Gbps DDR3 signals This 14-bit DDR switch is designed for 1.5V or 1.8V supply voltage, SSTL_15 or SSTL_18 signaling and CMOS select input signals. It is designed for DDR2 or DDR3 memory bus with speed up to 5Gbps. IIVDD 1.5V or 1.8V +/- 10% IISEL and Global Enable II220 A typ. operating current PI2DDR3212 has a 1:2 demux or 2:1 mux topology. All 14-bit channels can be switched to one of the two ports simultaneously with the SEL input. This device also allows all ports to be disconnected. IIHigh impedance and low Coff channel output when disabled or deselected IILow RON: 8 typical PI2DDR3212 uses Pericom's proprietary high speed switch technology providing consistent high bandwidth across all channels, with very little insertion loss, cross-talk, and bit to bit skew. II3dB Bandwidth: 2.7GHz IILow insertion loss: -0.6dB (0f1GHz) IILow cross-talk for high speed channels: It is available in a 52-pin TQFN 3.5x9x0.4mm package and 48-pin TFBGA 4.5x4.5x0.8mm package. The 48-pin version is pin compatible with CBTW28DD14. -18dB typ. (0<f<2GHz) IILow bit-to-bit skew 20ps Max IIESD: 2KV HBM IISSTL_15 or SSTL_18 signaling IIPackaging (Pb-free and Green) aa 52 pin TQFN (3.5x9x0.4mm) aa 48 pin TFBGA (4.5x4.5x0.8mm)pin compatible with CBTW28DD14 52 51 50 49 48 B13 C13 B12 C12 GND Pin Configuration (52-pin TQFN) 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 B11 C11 B10 C10 B9 C9 B8 C8 B7 C7 VDD B6 C6 B5 C5 B4 C4 B3 C3 B2 C2 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 C0 B0 C1 B1 GND GND EN A13 A12 A11 VDD A10 A9 A8 A7 GND A6 A5 A4 A3 VDD A2 A1 A0 SEL GND 1 www.pericom.com P-0.1 07/06/12