High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
1 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date Remark
2.0 Initial issue with new naming rule Jan.20,2005
2.1 Remove 48PIN TSOP(I)/48PIN BGA(6*7mm) Jun.12,2006
2.2 Remove 48 Mini BGA 6*8 mm package type
Add 48 Mini BGA 6*7 mm package type Jul.05,2010
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
2 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
GENERAL DESCRIPTION
The CS16LV20483 is a high performance, high speed, super low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and operates from a wide
range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a typical CMOS standby current of
0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion
is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE) and
three-state output drivers.
The CS16LV20483 has an automatic power down feature, reducing the power
consumption significantly when chip is deselected. The CS16LV20483 is available in
JEDEC standard 44-pin TSOP 2, 48 Mini BGA 6*7mm.
FEATURES
Low operation voltage : 2.7 ~ 3.6V
Ultra low power consumption :
Vcc = 3.0V 2mA 1MHz (Max.) operating current
0.50uA (Typ.) CMOS standby current
High speed access time : 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible, fully static operation
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
Product Family
Product Family Operating
Temp
Vcc.
Range Speed (ns) Standby
(Typ.) Package Type
44 TSOP 2
48 Mini BGA 6*7mm
0~70oC 55/70 0.50 uA
(Vcc = 3.0V) Dice
44 TSOP 2
48 Mini BGA 6*7mm
CS16LV20483
-40~85oC
2.7~3.6
55/70 0.8 uA
(Vcc= 3.0V) Dice
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
3 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
4 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
PIN DESCRIPTIONS
Name Type Function
A0 A16 Input Address inputs for selecting one of the 131,072 x 16 bit words in the RAM
/CE Input
/CE is active LOW. Chip enable must be active when data read from or write
to the device. If chip enable is not active, the device is deselected and in a
standby power mode. The DQ pins will be in high impedance state when the
device is deselected.
/WE Input
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE Input
The output enable input is active LOW. If the output enable is active while
the chip is selected and the write enable is inactive, data will be present on
the DQ pins and they will be enabled. The DQ pins will be in the high
impedance state when /OE is inactive.
/LB and /UB Input Lower byte and upper byte data input/output control pins.
DQ0~DQ15 I/O These 16 bi-directional ports are used to read data from or write data into the
RAM.
Vcc Power Power Supply
Gnd Power Ground
TRUTH TABLE
MODE /CE /WE /OE /LB /UB DQ0~7 DQ8~15 Vcc Current
X X X H H
Standby H X X X X High Z High Z I
CCSB, ICCSB1
Output
Disabled L H H X X High Z High Z I
CC
L L D
OUT D
OUT I
CC
H L High Z D
OUT I
CC Read L H L
L H D
OUT High Z I
CC
L L D
IN D
IN I
CC
H L X D
IN I
CC Write L L X
L H D
IN X I
CC
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
5 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Parameter Rating Unit
VTERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V
TBIAS Temperature Under Bias -40 to +125 OC
TSTG Storage Temperature -60 to +150 OC
PT Power Dissipation 1.0 W
IOUT DC Output Current 25 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to 70oC , Vcc = 3.0V )
Parameter
Name Parameter Test Conduction MIN TYP(1) MAX Unit
VIL Guaranteed Input
Low Voltage (2)
-0.5 0.8 V
VIH Guaranteed Input
High Voltage (2)
2.0 Vcc+0.2 V
IIL Input Leakage
Current
VCC=MAX, VIN=0 to VCC -1 1 uA
IOL Output Leakage
Current
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC -1 1 uA
VOL Output Low Voltage V
CC=MAX, IOL = 2mA 0.4 V
VCC=MIN, IOH = -1mA 2.4
V
OH Output High Voltage
IOH = -100uA V
CC -0.2
V
ICC Operating Power
Supply Current
/CE=VIL, IDQ=0mA,
F=FMAX
(3)
25 mA
ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA, 1 mA
ICCSB1 Standby Current
-CMOS
/CE VCC-0.2V, VIN
VCC-0.2V or VIN 0.2V
0.5 4 uA
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC.
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
6 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70oC 2.7V ~ 3.6V
Industrial -40~85oC 2.7V ~ 3.6V
1. Overshoot : Vcc +2.0V in case of pulse width 20ns.
2. Undershoot : - 2.0V in case of pulse width 20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC)
Parameter
Name Parameter Test Conduction MIN TYP(1) MAX Unit
VDR VCC for Data
Retention
/CE VCC-0.2V, V
IN VCC-0.2V
or VIN 0.2V 1.5 V
ICCDR Data Retention
Current
/CE VCC-0.2V, VCC =1.5V
V
IN VCC-0.2V or VIN 0.2V 0.3 2 uA
TCDR Chip Deselect to
Data Retention Time 0 ns
tR Operation Recovery
Time
See Retention Waveform t
RC
(2) ns
1. Vcc = 3.0V, TA = + 25oC.
2. tRC (2)= Read Cycle Time.
CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol Parameter Conditions MAX. Unit
CIN Input Capacitance
VIN=0V 6 pF
CDQ Input/Output CapacitanceV
I/O=0V 8 pF
1. This parameter is guaranteed and not tested.
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
7 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS
Input Pulse Levels Vcc/0V WAVEFORMS INPUTS OUTPUTS
Input Rise and Fall Times 5ns MUST BE STEADY MUST BE STEADY
Input and Output Timing
Reference Level 0.5Vcc
Output Load See FIGURE 1A
and 1B
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A FIGURE 1B
667
TERMINAL EQUIVALENT
OUTPUT1.73V
GND
V
CC
5ns5ns
10%
90%90%
10%
ALL INPUT PULSES
FIGURE 2
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
8 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3V )
< READ CYCLE >
-55 -70 JEDEC
Parameter
Name
Parameter
Name
Description
MIN MAX MIN MAX
Unit
tAVAX t
RC Read Cycle Time
55 70 ns
tAVQV t
AA Address Access Time
55 70 ns
tELQV t
ACS Chip Select Access Time
(/CE)
55 70 ns
tBA t
BA Data Byte Control Access Time
(/LB, /UB)
55 70 ns
tGLQV t
OE Output Enable to Output Valid
30 35 ns
tELQX t
CLZ Chip Select to Output Low Z
(/CE)
10 10 ns
tBE t
BE Data Byte Control to Output Low
Z (/LB, /UB)
0 0 ns
tGLQX t
OLZ Output Enable to Output in Low Z5 5 ns
tEHQZ t
CHZ Chip Deselect to Output in High Z
(/CE)
0 20 0 25 ns
tBDO t
BDO Data Byte Control to Output High
Z (/LB, /UB)
0 20 0 25 ns
tGHQZ t
OHZ Output Disable to Output in High
Z
0 20 0 25 ns
tAXOX t
OH Out Disable to Address Change 10 10 ns
Note: 1.) /WE is high in read Cycle. 2.) Device is continuously selected when /CE = VIL.
3.) Address valid prior to or coincident with CE transition low. 4.) /OE = VIL. 5.) Transition is
measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
9 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
SWITCHING WAVEFORMS (READ CYCLE)
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
10 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3V )
< WRITE CYCLE >
-55 -70 JEDEC
Parameter
Name
Parameter
Name
Description
MIN MAX MIN MAX
Unit
tAVAX t
WC Write Cycle Time
55 70 ns
tE1LWH t
CW Chip Select to End of Write
45 60 ns
tAVWL t
AS Address Setup Time
0 0 ns
tAVWH t
AW Address Valid to End of Write
45 60 ns
tWLWH t
WP Write Pulse Width
40 55 ns
tWHAX t
WR1 Write Recovery Time (/CE, /WE)
0 0 ns
tBW t
BW Data Byte Control to End of Write
(/LB, /UB)
45 60 ns
tWLQZ t
WHZ Write to Output in High Z
20 25 ns
tDVWH t
DW Data to Write Time Overlap
25 30 ns
tWHDX t
DH Data Hold from Write Time
0 0 ns
tWHOX t
OW End of Write to Output Active
5 10 ns
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
11 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
SWITCHING WAVEFORMS (WRITE CYCLE)
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
12 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. T
AS is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All
signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. T
WR is measured from the earliest of /CE or /WE or (/UB and ,or /LB) going high at the
end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the
/WE transition, output remain in a high impedance state.
6. /OE is continuously low (/OE = VIL ).
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If /CE is low during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. T CW is measured from the later of /CE going low to the end of write.
High Speed Super Low Power SRAM
128k Word x 16 bit CS16LV20483
13 Rev. 2.2
Chiplus reserves the right to change product or specification without notice.
ORDER INFORMATION
Note: Package material code "R# meets ROHS
