Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. C
12/03/09
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS63WV1024BLL
IS64WV1024BLL
128K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time:
12 ns: 3.3V + 10%
15 ns: 2.5V – 3.6V
• High-performance, low-power CMOS process
• CMOS Low Power Operation
50 mW (typical) operating current
25 µW (typical) standby current
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE options
•CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Packages available:
– 32-pin TSOP (Type II)
– 32-pin sTSOP (Type I)
– 48-Ball miniBGA (6mm x 8mm)
– 32-pin 300-mil SOJ
• Lead-free available
DESCRIPTION
The ISSI IS63/64WV1024BLL is a very high-speed, low
power, 131,072-word by 8-bit CMOS static RAM. The
IS63/64WV1024BLL is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 25 µW (typical) with CMOS input levels.
The IS63/64WV1024BLL operates from a single VDD
power supply. The IS63/64WV1024BLL is available in
32-pin TSOP (Type II), 32-pin sTSOP (Type I), 48-Ball
miniBGA (6mm x 8mm), and 32-pin SOJ (300-mil)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
JANUARY 2010
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
VDD Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin sTSOP (Type I) (H)
PIN CONFIGURATION
48-mini BGA (B) (6 mm x 8 mm)
PIN CONFIGURATION
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
1 2 3 4 5 6
A
B
C
D
E
F
G
H
NC OE A2 A6 A7 NC
I/O
1
NC A1 A5 CE I/O
8
I/O
2
NC A0 A4 NC I/O
7
GND NC NC A3 NC V
DD
V
DD
NC NC NC NC GND
I/O
3
NC A14 A11 I/O
5
I/O
6
I/O
4
NC A15 A12 WE A8
NC A10 A16 A13 A9 NC
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
3
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation VDD Current
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
OPERATING RANGE (VDD)
Range Ambient Temperature VDD (15 ns) VDD (12 ns)
Commercial 0°C to +70°C 2.5V-3.6V 3.3V + 10%
Industrial –40°C to +85°C 2.5V-3.6V 3.3V + 10%
Automotive –40°C to +125°C 2.5V-3.6V 3.3V + 10%
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.5 W
VDD VDD Related to GND -0.2 to +3.9 V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.5V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 2.3 — V
VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –2 2 µA
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 10%
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD –2 2 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –2 2 µA
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width < 10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
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Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12 ns -15 ns
Symbol Parameter Test Conditions Options Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max.,
COM.
—35 —30 mA
Supply Current IOUT = 0 mA, f = fMAX
IND.
—45 —40
AUTO —60 —50
typ.
(2)
—20 —20
ICC1Operating Supply VDD = Max.,
COM.
—5 —5 mA
Current Iout = 0mA, f = 0
IND.
—5 —5
AUTO —5 —5
ISB1TTL Standby Current VDD = Max.,
COM.
—3 —3 mA
(TTL Inputs) VIN = VIH or VIL
IND.
—4 —4
CE ≥ VIH, f = 0 AUTO —4 —4
ISB2CMOS Standby VDD = Max.,
COM.
—20 —20 uA
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
IND.
—50 —50
VIN ≥ VDD – 0.2V, or
AUTO
—75 —75
VIN ≤ 0.2V, f = 0 typ.
(2)
—6 —6
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=2.5V, TA=25oC. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
AC TEST CONDITIONS
Parameter Unit Unit
(2.5V-3.6V) (3.3V + 10%)
Input Pulse Level 0V to VDD V 0V to VDD V
Input Rise and Fall Times 1.5ns 1.5ns
Input and Output Timing VDD/2 VDD/2 + 0.05
and Reference Level (VRef)
Output Load See Figures 1a and 1b See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
30 pF
Including
jig and
scope
Zo=50Ω
OUTPUT VRef
50Ω
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
2.5V
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1-800-379-4774
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Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 12 — 15 — ns
tAA Address Access Time — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — ns
tACE CE Access Time — 12 — 15 ns
tDOE OE Access Time — 6 — 7 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — ns
tHZOE
(2)
OE to High-Z Output 0 6 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — ns
tHZCE
(2)
CE to High-Z Output 0 6 0 6 ns
tPU CE to Power Up Time 0 — 0 — ns
tPD CE to Power Down Time — 12 — 15 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1.
2. Tested with the loading specified in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA
t OHA
t RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
DOUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
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Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-12 ns -15 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 12 — 15 — ns
tSCE CE to Write End 9 — 10 — ns
tAW Address Setup Time to 9 — 10 — ns
Write End
tHA Address Hold from 0 — 0 — ns
Write End
tSA Address Setup Time 0 — 0 — ns
tPWE
1
(1)
WE Pulse Width (OE High) 9 — 10 — ns
tPWE
2
(2)
WE Pulse Width (OE Low) 11 — 12 — ns
tSD Data Setup to Write End 9 — 9 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 6 — 7 ns
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1a.
2. Tested with the loading specified in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
AC WAVEFORMS
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.com —
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11
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
DATA RETENTION WAVEFORM (CE Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Operations Min. Typ.
(1)
Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 1.8 — 3.6 V
IDR Data Retention Current VDD = 1.8V, CE ≥ VDD – 0.2V
COM.
—620 µA
IND.
—650
AUTO.— 6 75
tSDR Data Retention Setup Time See Data Retention Waveform 0 — — ns
tRDR Recovery Time See Data Retention Waveform tRC —— ns
Note:
1. Typical values are measured at V
DD
= 2.5V, T
A
= 25
O
C. Not 100% tested.
V
DD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
12 IS63WV1024BLL-12TI 32-pin TSOP (Type II)
IS63WV1024BLL-12TLI 32-pin TSOP (Type II), Lead-free
IS63WV1024BLL-12HI sTSOP (Type I) (8mm x13.4mm)
IS63WV1024BLL-12HLI sTSOP (Type I) (8mm x13.4mm), Lead-free
IS63WV1024BLL-12JI 32-pin SOJ (300-mil)
IS63WV1024BLL-12JLI 32-pin SOJ (300-mil), Lead-free
IS63WV1024BLL-12BI mBGA(6mmx8mm)
IS63WV1024BLL-12BLI mBGA(6mmx8mm), Lead-free
Automotive Range (A3): –40°C to +85°C
Speed (ns) Order Part No. Package
15 (12*) IS64WV1024BLL-15TA3 32-pin TSOP (Type II)
IS64WV1024BLL-15TLA3 32-pin TSOP (Type II), Lead-free
IS64WV1024BLL-15HA3 sTSOP (Type I) (8mm x13.4mm)
IS64WV1024BLL-15HLA3 sTSOP (Type I) (8mm x13.4mm), Lead-free
IS64WV1024BLL-15BA3 mBGA(6mmx8mm)
IS64WV1024BLL-15BLA3 mBGA(6mmx8mm), Lead-free
Note:
1. Speed = 12ns for VDD = 3.3V + 10%. Speed = 15ns for VDD = 2.5V-3.6V.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
13
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
14
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
15
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/12/2008
Package Outline
16
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/03/09
IS63WV1024BLL
IS64WV1024BLL
