Low Power, Selectable Gain
Differential ADC Driver, G = 1, 2, 3
Data Sheet
ADA4950-1/ADA4950-2
Rev. B Document Feedback
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FEATURES
High performance at low power
High speed
−3 dB bandwidth of 750 MHz, G = 1
0.1 dB flatness to 210 MHz, VOUT, dm = 2 V p-p, RL, dm = 200 Ω
Slew rate: 2900 V/µs, 25% to 75%
Fast 0.1% settling time of 9 ns
Low power: 9.5 mA per amplifier
Low harmonic distortion
108 dB SFDR @ 10 MHz
98 dB SFDR @ 20 MHz
Low output voltage noise: 9.2 nV/√Hz, G = 1, RTO
±0.2 mV typical input offset voltage
Selectable differential gains of 1, 2, and 3
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Input common-mode range shifted down by 1 VBE
Wide supply range: +3 V to ±5 V
Available in 16-lead and 24-lead LFCSP packages
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The ADA4950-1/ADA4950-2 are gain-selectable versions of the
ADA4932-1/ADA4932-2 with on-chip feedback and gain resistors.
They are ideal choices for driving high performance ADCs as single-
ended-to-differential or differential-to-differential amplifiers. The
output common-mode voltage is user adjustable by means of an
internal common-mode feedback loop, allowing the ADA4950-1/
ADA4950-2 output to match the input of the ADC. The internal
feedback loop also provides exceptional output balance as well
as suppression of even-order harmonic distortion products.
Differential gain configurations of 1, 2, and 3 are easily realized
with internal feedback networks that are connected externally
to set the closed-loop gain of the amplifier.
The ADA4950-1/ADA4950-2 are fabricated using the Analog
Devices, Inc., proprietary silicon-germanium (SiGe) complementary
bipolar process, enabling them to achieve low levels of distortion and
noise at low power consumption. The low offset and excellent
dynamic performance of the ADA4950-x make it well suited for
a wide variety of data acquisition and signal processing applications.
FUNCTIONAL BLOCK DIAGRAMS
+INB
+INA
–INA
–INB
–OUT
PD
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
–V
S
–V
S
–V
S
–V
S
07957-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4950-1
Figure 1. ADA4950-1
07957-002
2
1
3
4
5
6
18
17
16
15
14
13
+INA2
+INB2
+V
S1
+V
S1
–INB1
–INA1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
–INB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–INA2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 +INB1
24 +INA1
ADA4950-2
Figure 2. ADA4950-2
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
HARMONIC DI S TORTION (dBc)
FREQUENCY (MHz)
V
OUT,dm
= 2V p-p
0.1 1 10 100
HD2, ±5V
HD3, ±5V
HD2, ±2.5V
HD3, ±2.5V
07957-025
Figure 3. Harmonic Distortion vs. Frequency at Various Supplies
The devices are available in a Pb-free, 3 mm × 3 mm, 16-lead
LFCSP (ADA4950-1, single) or a Pb-free, 4 mm × 4 mm, 24-lead
LFCSP (ADA4950-2, dual). The pinout has been optimized to
facilitate PCB layout and minimize distortion. The ADA4950-1/
ADA4950-2 are specified to operate over the −40°C to +105°C
temperature range; both operate on supplies from +3 V to ±5 V.
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Operation ............................................................................. 3
5 V Operation ............................................................................... 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 16
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Applications Information .............................................................. 19
Analyzing an Application Circuit ............................................ 19
Selecting the Closed-Loop Gain ............................................... 19
Estimating the Output Noise Voltage ...................................... 19
Calculating the Input Impedance for an Application
Circuit .......................................................................................... 20
Input Common-Mode Voltage Range ..................................... 22
Input and Output Capacitive AC Coupling ............................ 22
Input Signal Swing Considerations .......................................... 22
Setting the Output Common-Mode Voltage .......................... 22
Layout, Grounding, and Bypassing .............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/15—Rev. A to Rev. B
Changed CP-16-2 to CP-16-21 ......................................... Universal
Changes to Figure 1 .......................................................................... 1
Changes to Figure 5 .......................................................................... 8
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
3/13—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
5/09—Revision 0: Initial Version
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 3 of 26
SPECIFICATIONS
±5 V OPERATION
TA = 25°C, +VS = 5 V, −V S = −5 V, VOCM = 0 V, G = 1, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications
refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 52 for signal definitions.
Differential Inputs to VOUT, dm Performance
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth VOUT, dm = 0.1 V p-p 750 MHz
−3 dB Large-Signal Bandwidth VOUT, dm = 2.0 V p-p 350 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 2.0 V p-p, RL = 200 Ω
ADA4950-1 210 MHz
ADA4950-2 230 MHz
Slew Rate VOUT, dm = 2 V p-p, 25% to 75% 2900 V/µs
Settling Time to 0.1% VOUT, dm = 2 V step 9 ns
Overdrive Recovery Time VIN = 0 V to 5 V ramp, G = 2 20 ns
NOISE/HARMONIC PERFORMANCE See Figure 51 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p
1 MHz −108 dBc
10 MHz −107 dBc
20 MHz −98 dBc
50 MHz −80 dBc
Third Harmonic VOUT, dm = 2 V p-p
1 MHz −126 dBc
10 MHz −105 dBc
20 MHz −99 dBc
50 MHz −84 dBc
IMD3 f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p −94 dBc
Voltage Noise (Referred to Output) f = 1 MHz
Gain = 1 9.2 nV/√Hz
Gain = 2 12.5 nV/√Hz
Gain = 3 16.6 nV/√Hz
Crosstalk (ADA4950-2)
f = 10 MHz; Channel 2 active, Channel 1
output
−87
dB
INPUT CHARACTERISTICS
Offset Voltage (Referred to Input) V+DIN = V−DIN = VOCM = 0 V −2.5 ±0.2 +2.5 mV
TMIN to TMAX variation –3.7 µV/°C
Input Capacitance Single-ended at package pin 0.5 pF
Input Common-Mode Voltage Range Directly at internal amplifier inputs, not
external input terminals
−VS + 0.2 to
+VS − 1.8
V
CMRR
DC, ∆V
OUT, dm
/∆V
IN, cm
, ∆V
IN, cm
= ±1 V
−64
−49
dB
Open-Loop Gain 64 66 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT, single-ended output,
RL = 1 kΩ
–VS + 1.4 to
+VS – 1.4
−VS + 1.2 to
+VS − 1.2
V
Linear Output Current 200 kHz, RL, dm = 10 Ω, SFDR = 69 dB 114 mA peak
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 2 V p-p, 1 MHz;
see Figure 50 for output balance test circuit
−62 dB
Gain Error Gain = 1 0.5 1.2 %
Gain = 2 1.0 1.9 %
Gain = 3 0.8 1.7 %
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 4 of 26
VOCM to VOUT, cm Performance
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth VOUT, cm = 100 mV p-p 250 MHz
−3 dB Large-Signal Bandwidth VOUT, cm = 2 V p-p 105 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 430 V/µs
Input Voltage Noise (Referred to Input) f = 1 MHz 9.8 nV/√Hz
VOCM INPUT CHARACTERISTICS
Input Voltage Range –VS + 1.2 to
+VS – 1.2
V
Input Resistance 22 26 32 kΩ
Input Offset Voltage V+DIN = V−DIN = 0 V −6 +0.8 +6 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −60 −49 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.98 1.0 1.01 V/V
General Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.0 11 V
Quiescent Current per Amplifier 8.8 9.5 10.1 mA
TMIN to TMAX variation 31 µA/°C
Powered down 0.7 1.0 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p −96 −84 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤(+VS – 2.5) V
Enabled ≥(+VS – 1.8) V
Turn-Off Time
600
ns
Turn-On Time 28 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V −1.0 +0.2 +1.0 µA
Disabled PD = 0 V −250 −180 −140 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 5 of 26
5 V OPERATION
TA = 25°C, +VS = 5 V, −V S = 0 V, V OCM = 2.5 V, G = 1, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications
refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 52 for signal definitions.
Differential Inputs to VOUT, dm Performance
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth VOUT, dm = 0.1 V p-p 770 MHz
−3 dB Large-Signal Bandwidth VOUT, dm = 2.0 V p-p 320 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 2.0 V p-p, RL = 200 Ω
ADA4950-1 220 MHz
ADA4950-2 160 MHz
Slew Rate VOUT, dm = 2 V p-p, 25% to 75% 2200 V/µs
Settling Time to 0.1% VOUT, dm = 2 V step 10 ns
Overdrive Recovery Time VIN = 0 V to 2.5 V ramp, G = 2 19 ns
NOISE/HARMONIC PERFORMANCE See Figure 51 for distortion test circuit
Second Harmonic
V
OUT, dm
= 2 V p-p
1 MHz −108 dBc
10 MHz −107 dBc
20 MHz −98 dBc
50 MHz −82 dBc
Third Harmonic VOUT, dm = 2 V p-p
1 MHz −124 dBc
10 MHz −114 dBc
20 MHz −99 dBc
50 MHz −83 dBc
IMD3 f1 = 30 MHz, f2 = 30.1 MHz, VOUT, dm = 2 V p-p −94 dBc
Voltage Noise (Referred to Input) f = 1 MHz
Gain = 1 9.2 nV/√Hz
Gain = 2 12.5 nV/√Hz
Gain = 3 16.6 nV/√Hz
Crosstalk (ADA4950-2) f = 10 MHz; Channel 2 active, Channel 1
output
−87 dB
INPUT CHARACTERISTICS
Offset Voltage (Referred to Input) V+DIN = V−DIN = VOCM = 2.5 V −4 ±0.4 +4 mV
TMIN to TMAX variation −3.7 µV/°C
Input Capacitance
Single-ended at package pin
0.5
pF
Input Common-Mode Voltage Range Directly at internal amplifier inputs, not
external input terminals
–VS + 0.2 to
+VS – 1.8
V
CMRR DC, ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −64 −49 dB
Open-Loop Gain 64 66 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT, single-ended output,
R
L
= 1 kΩ
–VS + 1.2 to
+V
S
– 1.2
–VS + 1.1 to
+V
S
– 1.1
V
Linear Output Current
200 kHz, R
L, dm
= 10 Ω, SFDR = 67 dB
70
mA peak
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V p-p, 1 MHz;
see Figure 50 for output balance test circuit
−62 dB
Gain Error Gain = 1 0.5 1.2 %
Gain = 2 1.0 1.9 %
Gain = 3 0.8 1.7 %
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 6 of 26
VOCM to VOUT, cm Performance
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small-Signal Bandwidth VOUT, cm = 100 mV p-p 240 MHz
−3 dB Large-Signal Bandwidth VOUT, cm = 2 V p-p 90 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 380 V/µs
Input Voltage Noise (Referred to Input) f = 1 MHz 9.8 nV/√Hz
VOCM INPUT CHARACTERISTICS
Input Voltage Range –VS + 1.2 to
+VS – 1.2
V
Input Resistance 22 26 32 kΩ
Input Offset Voltage V+DIN = V−DIN = 2.5 V −6.5 +1.0 +6.5 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −60 −49 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.98 1.0 1.01 V/V
General Performance
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 3.0 11 V
Quiescent Current per Amplifier 8.4 8.9 9.6 mA
TMIN to TMAX variation 31 µA/°C
Powered down 0.6 0.9 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V p-p −96 −84 dB
POWER-DOWN (PD)
PD Input Voltage Powered down ≤(+VS – 2.5) V
Enabled ≥(+VS – 1.8) V
Turn-Off Time
600
ns
Turn-On Time 29 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V −1.0 +0.2 +1.0 µA
Disabled PD = 0 V −100 −65 −40 µA
OPERATING TEMPERATURE RANGE −40 +105 °C
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 7 of 26
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage 11 V
Power Dissipation
See Figure 4
Input Current, +INx, −INx, PD ±5 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range
ADA4950-1 −40°C to +105°C
ADA4950-2 −40°C to +105°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p printed circuit board, as
described in EIA/JESD51-7.
Table 8. Thermal Resistance
Package Type θJA θJC Unit
ADA4950-1, 16-Lead LFCSP (Exposed Pad) 91 28 °C/W
ADA4950-2, 24-Lead LFCSP (Exposed Pad) 65 16 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4950-x package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4950-x. Exceeding a junction temper-
ature of 150°C for an extended period can result in changes in
the silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive. The quiescent power is the voltage between
the supply pins (VS) times the quiescent current (IS). The power
dissipated due to the load drive depends upon the particular
application. The power dissipated due to the load drive is calcu-
lated by multiplying the load current by the associated voltage
drop across the device. RMS voltages and currents must be used
in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on
a JEDEC standard 4-layer board with the exposed pad soldered
to a PCB pad that is connected to a solid plane.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–40 –20 020 40
07957-004
60 80 100
AMBI ENT T E M P E RATURE (°C)
MAXIMUM POWER DISSIPATIO N (W)
ADA4950-2
ADA4950-1
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
for a 4-Layer Board
ESD CAUTION
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 8 of 26
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. SOLDER THE EX P OSE D P ADDLE O N THE BACK OF
THE PACKAGE TO A GRO UND P LANE O R TO A
POWER PLANE.
+INB
+INA
–INA
–INB
–OUT
PD
+OUT
VOCM
+VS
+VS
+VS
+VS
–VS
–VS
–VS
–VS
07957-005
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADA4950-1
TOP VIEW
(Not to Scal e)
Figure 5. ADA4950-1 Pin Configuration
07957-006
2
1
3
4
5
6
18
17
16
15
14
13
+INA2
+INB2
+V
S1
+V
S1
–INB1
–INA1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
–INB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–INA2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 +INB1
24 +INA1
ADA4950-2
TOP VIEW
(No t t o Scal e)
NOTES
1. SOLDER THE EX P OSE D P ADDLE O N THE BACK O F
THE P ACKAGE TO A GRO UND P LANE O R TO A
POWER PLANE.
Figure 6. ADA4950-2 Pin Configuration
Table 9. ADA4950-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 +INB Positive Input B, 250 Ω Input. Use alone for G = 2 or tie to +INA for G = 3.
2 +INA Positive Input A, 500 Ω Input. Use alone for G = 1 or tie to +INB for G = 3.
3 −INA Negative Input A, 500 Ω Input. Use alone for G = 1 or tie to −INB for G = 3.
4 −INB Negative Input B, 250 Ω Input. Use alone for G = 2 or tie to −INA for G = 3.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output.
11 −OUT Negative Output.
12 PD Power-Down Pin.
13 to 16 −VS Negative Supply Voltage.
17 (EPAD) Exposed Paddle (EPAD) Solder the exposed paddle on the back of the package to a ground plane or to a power plane.
Table 10. ADA4950-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −INA1 Negative Input A, Amplifier 1, 500 Ω Input. Use alone for G = 1 or tie to –INB1 for G = 3.
2 −INB1 Negative Input B, Amplifier 1, 250 Ω Input. Use alone for G = 2 or tie to –INA1 for G = 3.
3, 4 +VS1 Positive Supply Voltage, Amplifier 1.
5 +INB2 Positive Input B, Amplifier 2, 250 Ω Input. Use alone for G = 2 or tie to +INA2 for G = 3.
6 +INA2 Positive Input A, Amplifier 2, 500 Ω Input. Use alone for G = 1 or tie to +INB2 for G = 3.
7 −INA2 Negative Input A, Amplifier 2, 500 Ω Input. Use alone for G = 1 or tie to –INB2 for G = 3.
8 −INB2 Negative Input B, Amplifier 2, 250 Ω Input. Use alone for G = 2 or tie to –INA2 for G = 3.
9, 10 +VS2 Positive Supply Voltage, Amplifier 2.
11 VOCM2 Output Common-Mode Voltage, Amplifier 2.
12 +OUT2 Positive Output, Amplifier 2.
13 −OUT2 Negative Output, Amplifier 2.
14 PD2 Power-Down Pin, Amplifier 2.
15, 16 −VS2 Negative Supply Voltage, Amplifier 2.
17 VOCM1 Output Common-Mode Voltage, Amplifier 1.
18 +OUT1 Positive Output, Amplifier 1.
19
−OUT1
Negative Output, Amplifier 1.
20 PD1 Power-Down Pin, Amplifier 1.
21, 22 −VS1 Negative Supply Voltage, Amplifier 1.
23 +INB1 Positive Input B, Amplifier 1, 250 Ω Input. Use alone for G = 2 or tie to +INA1 for G = 3.
24 +INA1 Positive Input A, Amplifier 1, 500 Ω Input. Use alone for G = 1 or tie to +INB1 for G = 3.
25 (EPAD) Exposed Paddle (EPAD) Solder the exposed paddle on the back of the package to a ground plane or to a power plane.
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 9 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −V S = −5 V, VOCM = 0 V, G = 1, RT = 53.6 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. Refer to Figure 49
for test setup. Refer to Figure 52 for signal definitions.
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100
FREQUENCY (MHz) 1000
07957-007
NORMALIZED CLOSED-LOOP GAIN (dB)
V
OUT, dm
= 100mV p - p
G = 1, R
T
= 53.6Ω
G = 2, R
T
= 57.6Ω
G = 3, R
T
= 61.9Ω
Figure 7. Small-Signal Frequency Response for Various Gains
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100
FREQUENCY (MHz) 1000
07957-008
CLOSED-LOOP GAI N ( dB)
V
S
= ±5V
V
S
= ±2. 5V
V
OUT, dm
= 100mV p - p
Figure 8. Small-Signal Frequency Response for Various Supplies
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100
FREQUENCY (MHz) 1000
07957-009
CLOSED-LOOP GAI N ( dB)
T
A
= –40° C
T
A
= +25°C
T
A
= +105°C
V
OUT, dm
= 100mV p - p
Figure 9. Small-Signal Frequency Response for Various Temperatures
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100 1000
07957-010
NORMALIZED CLOSED-LOOP GAIN (dB)
V
OUT, dm
= 2V p-p
G = 1, R
T
= 53.6Ω
G = 2, R
T
= 57.6Ω
G = 3, R
T
= 61.9Ω
FREQUENCY (MHz)
Figure 10. Large-Signal Frequency Response for Various Gains
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100 1000
07957-011
CLOSED-LOOP GAI N ( dB)
V
OUT, dm
= 2V p-p
V
S
= ±5V
V
S
= ±2. 5V
FREQUENCY (MHz)
Figure 11. Large-Signal Frequency Response for Various Supplies
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100 1000
07957-012
CLOSED-LOOP GAI N ( dB)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
T
A
= –40° C
T
A
= +25°C
T
A
= +105°C
Figure 12. Large-Signal Frequency Response for Various Temperatures
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 10 of 26
110 100 1000
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
07957-013
CLOSED-LOOP GAI N ( dB)
FREQUENCY (MHz)
V
OUT, dm
= 100mV p - p
R
L
= 1kΩ
R
L
= 200Ω
Figure 13. Small-Signal Frequency Response at Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100
FREQUENCY (MHz) 1000
07957-014
CLOSED-LOOP GAI N ( dB)
V
OUT, dm
= 100mV p - p
V
OCM
= –2.5V DC
V
OCM
= 0V
V
OCM
= +2. 5V DC
Figure 14. Small-Signal Frequency Response for Various VOCM Levels
110 100
FREQUENCY (MHz) 1000
07957-015
CLOSED-LOOP GAI N ( dB)
V
OUT, dm
= 100mV p - p
–8
–6
–4
–2
0
2
4
C
L
= 0pF
C
L
= 0.9pF
C
L
= 1.8pF
C
L
= 2.7pF
Figure 15. Small-Signal Frequency Response at Various Capacitive Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100 1000
07957-016
CLOSED-LOOP GAI N ( dB)
V
OUT, dm
= 2V p-p
R
L
= 1kΩ
R
L
= 200Ω
FREQUENCY (MHz)
Figure 16. Large-Signal Frequency Response at Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100
FREQUENCY (MHz) 1000
07957-017
CLOSED-LOOP GAI N ( dB)
V
OUT, dm
= 2V p-p
V
OCM
= –2.5V DC
V
OCM
= 0V
V
OCM
= +2. 5V DC
Figure 17. Large-Signal Frequency Response for Various VOCM Levels
–8
–6
–4
–2
0
2
4
110 100 1000
07957-018
CLOSED-LOOP GAI N ( dB)
FREQUENCY (MHz)
V
OUT, dm
= 2V p-p
C
L
= 0pF
C
L
= 0.9pF
C
L
= 1.8pF
C
L
= 2.7pF
Figure 18. Large-Signal Frequency Response at Various Capacitive Loads
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 11 of 26
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
110 100 1000
CLOSED-LOOP GAIN (dB)
07957-019
V
OUT, dm
= 100mV p - p
FREQUENCY (MHz)
ADA4950-1, R
L
=1kΩ
ADA4950-1, R
L
= 200Ω
ADA4950-2, AMP 1, R
L
=1kΩ
ADA4950-2, AMP 1, R
L
=200Ω
ADA4950-2, AMP 2, R
L
=1kΩ
ADA4950-2, AMP 2, R
L
=200Ω
Figure 19. 0.1 dB Flatness, Small-Signal Frequency Response for Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100
FREQUENCY (MHz) 1000
07957-020
V
OCM
GAI N ( dB)
V
OCM
(AC) = 100mV p-p
V
OCM
= –2.5V DC
V
OCM
= 0V
V
OCM
= +2. 5V DC
Figure 20. VOCM Small-Signal Frequency Response at Various DC Levels
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
HARMO NI C DISTORTI ON (d Bc)
FREQUENCY (MHz)
HD2, R
L, dm
=1kΩ
HD3, R
L, dm
=1kΩ
HD2, R
L, dm
= 200Ω
HD3, R
L, dm
= 200Ω
V
OUT, dm
= 2V p-p
0.1 1 10 100
07957-021
Figure 21. Harmonic Distortion vs. Frequency at Various Loads
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
110 100 1000
CLOSED-LOOP GAIN (dB)
ADA4950-1, R
L
=1kΩ
ADA4950-1, R
L
= 200Ω
ADA4950-2, AMP 1, R
L
=1kΩ
ADA4950-2, AMP 1, R
L
=200Ω
ADA4950-2, AMP 2, R
L
=1kΩ
ADA4950-2, AMP 2, R
L
=200Ω
07957-022
V
OUT, dm
= 2V p-p
FREQUENCY (MHz)
Figure 22. 0.1 dB Flatness, Large-Signal Frequency Response for Various Loads
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
110 100 1000
07957-023
V
OCM
GAI N ( dB)
V
OCM
(AC) = 2V p-p
V
OCM
= –2.5V DC
V
OCM
= 0V
V
OCM
= +2. 5V DC
FREQUENCY (MHz)
Figure 23. VOCM Large-Signal Frequency Response at Various DC Levels
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
HARMO NI C DISTORTI ON (d Bc)
FREQUENCY (MHz)
VOUT, dm = 2V p-p
0.1 1 10 100
HD2, G = 1
HD3, G = 1
HD2, G = 2
HD3, G = 2
HD2, G = 3
HD3, G = 3
07957-024
Figure 24. Harmonic Distortion vs. Frequency at Various Gains
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 12 of 26
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
HARMO NI C DISTORTI ON (d Bc)
FREQUENCY (MHz)
VOUT, dm =2V p-p
0.1110100
HD2, ±5V
HD3, ±5V
HD2, ±2.5V
HD3, ±2.5V
07957-025
Figure 25. Harmonic Distortion vs. Frequency at Various Supplies
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–4 –3 –2 –1 0 1 2 3 4
HARMONIC DISTORTION (dBc)
V
OCM
(V)
V
OUT, dm
= 2V p-p
HD2 AT 10M Hz
HD3 AT 10M Hz
HD2 AT 30M Hz
HD3 AT 30M Hz
07957-026
Figure 26. Harmonic Distortion vs. VOCM at Various Frequencies, ±5 V Supplies
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
HARMO NI C DISTORTI ON (d Bc)
FREQUENCY (MHz)
HD2, V
OUT, dm
=2V p-p
HD3, V
OUT, dm
=2V p-p
HD2, V
OUT, dm
=4V p-p
HD3, V
OUT, dm
=4V p-p
0.1 1 10 100
07957-027
Figure 27. Harmonic Distortion vs. Frequency at Various VOUT, dm
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
012345678910 11 12 13 14
HARMO NI C DISTORTI ON (d Bc)
V
OUT, dm
(V p-p)
V
OCM
= 0V
HD2, ±5V
HD3, ±5V
HD2, ±2.5V
HD3, ±2.5V
07957-028
Figure 28. Harmonic Distortion vs. VOUT, dm, f = 10 MHz
–120
–110
–100
–90
–80
–70
–60
–50
–40
1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
HARMO NI C DISTORTI ON (d Bc)
V
OCM
(V)
V
OUT, dm
= 2V p-p
HD2 AT 10M Hz
HD3 AT 10M Hz
HD2 AT 30M Hz
HD3 AT 30M Hz
07957-029
Figure 29. Harmonic Distortion vs. VOCM at Various Frequencies, 5 V Supply
–140
–120
–130
–110
–100
–90
–80
–70
–60
–50
SPURI OUS- FREE DY NAM IC RANG E ( dBc)
FREQUENCY (MHz)
VOUT, dm = 2V p-p
0.11 10 100
RL, dm =200Ω
RL, dm =1kΩ
07957-030
Figure 30. Spurious-Free Dynamic Range vs. Frequency at Various Loads
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 13 of 26
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5
NORM ALIZED SP E CTRUM ( dB)
FREQUENCY (MHz)
VOUT, dm = 2V p-p
07957-031
Figure 31. 30 MHz Intermodulation Distortion
–65
–63
–59
–57
–61
–55
–51
–53
–45
–47
–49
110 100 1000
CMRR (dB)
FREQUENCY (MHz)
07957-032
R
L, dm
= 200Ω
V
IN
= 2V p-p
Figure 32. CMRR vs. Frequency
–70
–60
–50
–40
–30
–20
–10
0
1M 10M 100M 1G
OUT P UT BAL ANCE ( dB)
FREQUENCY ( Hz )
V
OUT, dm
=2V
p-p
07957-033
Figure 33. Output Balance vs. Frequency
80
–80
–60
–40
–20
0
20
40
60
90
–270
–225
–180
–135
–90
–45
0
45
1k 10k 100k 1M 10M 100M 1G 10G
GAI N ( dB)
PHASE ( Degrees)
FREQUENCY ( Hz )
GAIN
PHASE
07957-240
Figure 34. Open-Loop Gain and Phase vs. Frequency
–120
–100
–80
–60
–40
–20
0
110 100 1000
PSRR (dB)
FREQUENCY (MHz)
PSRR–
PSRR+
07957-035
R
L, dm
= 200Ω
V
IN, dm
= 100mV p - p
Figure 35. PSRR vs. Frequency
–140
–120
–100
–80
–60
–40
–20
0
110 100 1000
CROSS TAL K ( dB)
FREQUENCY (MHz)
AMPLIFIER 2 TO
AMPLIFIER 1
AMPLIFIER 1 TO
AMPLIFIER 2
07957-036
R
L, dm
= 200Ω
V
IN, dm
= 2V p-p
Figure 36. Crosstalk vs. Frequency, ADA4950-2
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 14 of 26
–60
–50
–40
–30
–20
–10
0
110 100 1000
S-PARAMETERS (dB)
FREQUENCY (MHz)
07957-037
R
L, dm
= 200Ω
V
IN, dm
= 100mV p - p
INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION
OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION
S11: SINGL E-ENDED-TO-SINGLE-ENDED
S22: DIFFERENTI AL-TO-DIFFERENTIAL
S11
S22
Figure 37. Return Loss (S11, S22) vs. Frequency
1
10
100
1000
110 100 1k 10k 100k 1M 10M
OUTPUT VOLTAGE NOISE DENSITY (nV/√Hz)
FREQUENCY (Hz)
07957-038
G = 1
G = 2
G = 3
Figure 38. Voltage Noise Spectral Density for Various Gains,
Referred to Output
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0 5 10 15 20 25 30
NORMALIZEDOUTPUT VOLTAGE (V)
TIME (ns)
G = 1
G = 2
G = 3
07957-039
Figure 39. Small-Signal Pulse Response for Various Gains
0.1
1
10
100
1k
0.1 110 100 1k
CLOSED-LOOP OUTPUT
IMPEDANCE MAGNITUDE (Ω)
FREQUENCY (MHz)
+OUT
–OUT
V
OUT, dm
07957-040
Figure 40. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1
15
10
5
0
–5
–10
–15 00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
07957-041
VOLTAGE (V)
TIME (µs)
2 × VIN
VOUT, dm
Figure 41. Overdrive Recovery, G = 2
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0 5 10 15 20 25 30
NORMALIZEDOUTPUT VOLTAGE (V)
TIME (ns)
07957-042
G = 3
G = 2
G = 1
Figure 42. Large-Signal Pulse Response for Various Gains
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 15 of 26
–0.10
–0.05
0
0.05
0.10
0 5 10 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (ns)
C
L
= 0pF
C
L
= 0.9pF
C
L
= 1.8pF
C
L
= 2.7pF
07957-043
Figure 43. Small-Signal Pulse Response for Various Capacitive Loads
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0 5 10 15 20 25 30
OUTPUT COMMON-MODE VOL T AGE (V)
TIME (ns)
07957-044
Figure 44. VOCM Small-Signal Pulse Response
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–5 0 5 10 15 20 25 30 35 40
ERROR ( %)
VOLTAGE (V)
TIME (n s)
OUTPUT
INPUT
ERROR
07957-045
Figure 45. Settling Time
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0 5 10 15 20 25 30
OUTPUT VOLTAGE (V)
TIME (n s)
C
L
= 0pF
C
L
= 0.9pF
C
L
= 1.8pF
C
L
= 2.7pF
07957-046
Figure 46. Large-Signal Pulse Response for Various Capacitive Loads
–1.5
–1.0
–0.5
0.5
0
1.0
1.5
0510 15 20 25 30
OUTPUT COMMON-MODE VOL T AGE (V)
TIME (ns)
07957-047
Figure 47. VOCM Large-Signal Pulse Response
–1
1
0
2
3
4
5
6
–0.2
0.2
0
0.4
0.6
0.8
1.0
1.2
0 1 2 3 4 5 6 7 8
NONINVERTING OUTPUT VOLTAGE (V)
PD PIN VOLTAGE (V)
TIME (ms)
07957-048
PD PI N INPUT
(SHOWN INVERTED
FOR CLARITY)
VOCM = +1V DC
Figure 48. PD Response Time
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 16 of 26
TEST CIRCUITS
ADA4950-x
1kΩ
+5
V
500Ω
500Ω
50Ω
500Ω
500Ω
V
OCM
53.6Ω
V
IN
0.1µF
–5V
250Ω
NC
250Ω
NC
25.5Ω
DC-COUPLED
SOURCE
07957-049
Figure 49. Equivalent Basic Test Circuit, G = 1
ADA4950-x
+5V
500Ω
500Ω
500Ω
500Ω
V
OCM
56.2Ω
–5V
250Ω
49.9Ω
49.9Ω
NC
250Ω
DIFFERENTIAL NETWORK
ANALYZER SOURCE
DIFFERENTIAL NETWORK
ANALYZER RECEIVER
NC
56.2Ω
50Ω
50Ω
07957-051
49.9Ω
49.9Ω
Figure 50. Test Circuit for Output Balance, CMRR
ADA4950-x
261Ω
442Ω
CT
200Ω
2:1
442Ω
0.1µF
0.1µF
+5
V
500Ω
500Ω
50Ω
500Ω
500Ω
V
OCM
53.6Ω
V
IN
0.1µF
–5V
250Ω
NC
250Ω
NC
25.5Ω
DC-COUPLED
LOW-PASS
FILTER
SOURCE
07957-252
DUAL
FILTER
50Ω
Figure 51. Test Circuit for Distortion Measurements
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 17 of 26
TERMINOLOGY
+IN
–IN +OUT
–OUT
+INA
+INB
–INB
–INA
V
OCM
R
GA
500Ω V
OUT, dm
R
L, dm
ADA4950-x
07957-152
R
GB
250Ω
R
GB
250Ω
R
F
500Ω
R
F
500Ω
R
GA
500Ω
Figure 52. Signal and Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or equiv-
alently, output differential node voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT output terminals with respect to a common ground
reference.
The input differential voltage is defined in different ways,
depending upon the selected gain.
For G = 1
VIN, dm = (+INA − (−INA))
where +INA and −INA refer to the voltages at the +INA and
−INA input terminals with respect to a common ground
reference (input terminals +INB and −INB are floating).
For G = 2
VIN, dm = (+INB − (−INB))
where +INB and −INB refer to the voltages at the +INB and
−INB input terminals with respect to a common ground
reference (input terminals +INA and −INA are floating).
For G = 3, input terminals +INA and +INB are connected
together, and input terminals −INA and −INB are connected
together.
VIN, dm = (+INAB − (−INAB))
where +INAB and −INAB refer to the voltages at the connection
of input terminals +INA and +INB and at the connection of
input terminals −INA and −INB with respect to a common
ground reference.
Common-Mode Voltage
Common-mode voltage refers to the average of two node
voltages with respect to the local ground reference. The output
common-mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Output Balance
Output balance is a measure of how close the output differential
signals are to being equal in amplitude and opposite in phase.
Any imbalances in amplitude or phase produce an undesired
common-mode signal at the amplifier output. Output balance
error is defined as the magnitude of the output common-mode
voltage divided by the magnitude of the output differential
mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
∆
∆
=
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 18 of 26
THEORY OF OPERATION
The ADA4950-x differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions and an
additional input, VOCM. Like an op amp, it relies on high open-loop
gain and negative feedback to force these outputs to the desired
voltages. The ADA4950-x behaves much like a standard voltage
feedback op amp and facilitates single-ended-to-differential
conversions, common-mode level shifting, and amplifications
of differential signals. Like an op amp, the ADA4950-x has high
input impedance at its internal input terminals (to the right of
the internal gain resistors) and low output impedance. Because
it uses voltage feedback, the ADA4950-x manifests a nominally
constant gain bandwidth product.
Two feedback loops are used to control the differential and
common-mode output voltages. The differential feedback loop,
set with on-chip feedback and gain resistors, controls only the
differential output voltage. The common-mode feedback loop is
internal to the actual amplifier and controls only the common-
mode output voltage. This architecture makes it easy to set the
output common-mode level to any arbitrary value within the
specified limits. The output common-mode voltage is forced, by
the internal common-mode feedback loop, to be equal to the
voltage applied to the VOCM input.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results in
differential outputs that are very close to the ideal of being
identical in amplitude and that are exactly 180° apart in phase.
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 19 of 26
APPLICATIONS INFORMATION
ANALYZING AN APPLICATION CIRCUIT
The ADA4950-x uses high open-loop gain and negative feedback
to force its differential and common-mode output voltages in
such a way as to minimize the differential and common-mode
error voltages. The differential error voltage is defined as the
voltage between the differential inputs labeled +INx and −INx
(see Figure 52). For most purposes, this voltage can be assumed
to be 0. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can
also be assumed to be 0. Starting from these principles, any
application circuit can be analyzed.
SELECTING THE CLOSED-LOOP GAIN
Using the approach described in the Analyzing an Application
Circuit section, the differential gain of the circuit in Figure 52
can be determined by
G
F
dmIN
dmOUT
R
R
V
V=
,
,
where the input resistors (RG) and the feedback resistors (RF) on
each side are equal.
For G = 1, the +INA and −INA inputs are used, and the +INB
and −INB inputs are left floating. The differential gain in this
case is calculated as follows:
1
500
500 =
Ω
Ω
==
G
F
R
R
G
For G = 2, the +INB and −INB inputs are used, and the +INA
and −INA inputs are left floating. The differential gain in this
case is calculated as follows:
2
250
500 =
Ω
Ω
==
G
F
R
R
G
For G = 3, the +INA and +INB inputs are connected together,
and the −INA and −INB inputs are connected together. The
differential gain in this case is calculated as follows:
3
250||500
500 =
ΩΩ
Ω
==
G
F
R
R
G
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4950-x can be estimated
using the noise model in Figure 53. The values of RG depend on
the selected gain. The input-referred noise voltage density, vnIN,
is modeled as a differential input, and the noise currents, inIN− and
inIN+, appear between each input and ground. The output voltage
due to vnIN is obtained by multiplying vnIN by the noise gain, GN
(defined in the GN equation that follows Table 13). The noise
currents are uncorrelated with the same mean-square value,
and each produces an output voltage that is equal to the noise
current multiplied by the associated feedback resistance. The
noise voltage density at the VOCM pin is vnCM. When the feedback
networks have the same feedback factor, as is true in most cases,
the output noise due to vnCM is common mode. Each of the four
resistors contributes (4kTRxx)1/2. The noise from the feedback
resistors appears directly at the output, and the noise from the
gain resistors appears at the output multiplied by RF/RG. Table 11
summarizes the input noise sources, the multiplication factors,
and the output-referred noise density terms.
ADA4950-x
+
RF2
vnOD
vnCM
VOCM
vnIN
RF1
RG2
RG1 vnRF1
vnRF2
vnRG1
vnRG2
inIN+
inIN–
07957-053
Figure 53. Noise Model
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Differential Input
v
nIN
v
nIN
G
N
v
nO1
= G
N
(v
nIN
)
Inverting Input inIN− inIN− × (RF2) 1 vnO2 = (inIN−)(RF2)
Noninverting Input inIN+ inIN+ × (RF1) 1 vnO3 = (inIN+)(RF1)
VOCM Input vnCM vnCM 0 vnO4 = 0 V
Gain Resistor, RG1 vnRG1 (4kTRG1)1/2 RF1/RG1 vnO5 = (RF1/RG1)(4kTRG1)1/2
Gain Resistor, RG2 vnRG2 (4kTRG2)1/2 RF2/RG2 vnO6 = (RF2/RG2)(4kTRG2)1/2
Feedback Resistor, RF1 vnRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor, RF2 vnRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 20 of 26
Table 12. Differential Input, DC-Coupled
Nominal Linear Gain RF (Ω) RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
1 500 500 1000 9.25
2 500 250 500 12.9
3 500 250||500 333 16.6
Table 13. Single-Ended, Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Linear Gain RF (Ω) RG1 (Ω) RT (Ω) (Std 1%) RIN, se (Ω) RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
1 500 500 53.6 667 526 9.07
2 500 250 57.6 375 277 12.2
3 500 250||500 61.9 267 194 15.0
1 RG2 = RG1 + (RS||RT).
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +INx and −INx by the appropriate output
factor, where:
( )
21
Nββ
G+
=2
is the circuit noise gain.
G1
F1
G1
1
RR
R
β+
=
and
G2
F2
G2
2
RR
R
β+
=
are the feedback factors.
When the feedback factors are matched, RF1/RG1 = RF2/RG2,
β1 = β2 = β, and the noise gain becomes
G
F
NR
R
β
G+== 1
1
Note that the output noise from VOCM goes to 0 in this case. The
total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
∑
=
=
8
1i
2
nOinOD
vv
Table 12 and Table 13 list the three available gain settings,
associated resistor values, input impedance, and output noise
density for both balanced and unbalanced input configurations.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 54, the input impedance (RIN, dm) is
RIN, dm = (RG + RG) = 2 × RG
The value of RG depends on the selected gain.
+VS
–VS
+IN
–IN
RF
RF
VOCM
RG
RG
VOUT, dm
VIN, dm
07957-054
ADA4950-x
Figure 54. ADA4950-x Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 55),
the input impedance is
( )
+×
−
=
F
G
F
G
seIN
RR
R
R
R
2
1
,
ADA4950-x
RLVOUT, dm
+VS
–VS
RG
RG
RF
RF
VOCM
RIN, se
07957-055
Figure 55. ADA4950-x with Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
is for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, RG. The common-mode voltage at the
amplifier input terminals can be easily determined by noting
that the voltage at the inverting input is equal to the noninverting
output voltage divided down by the voltage divider that is formed
by RF and RG in the lower loop. This voltage is present at both
input terminals due to negative voltage feedback and is in phase
with the input signal, thus reducing the effective voltage across
RG in the upper loop and partially bootstrapping RG.
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 21 of 26
Terminating a Single-Ended Input
This section describes how to properly terminate a single-ended
input to the ADA4950-x with a gain of 1, RF = 500 Ω, and RG =
500 Ω. An example using an input source with a terminated output
voltage of 1 V p-p and source resistance of 50 Ω illustrates the
steps that must be followed. Note that because the terminated
output voltage of the source is 1 V p-p, the open-circuit output
voltage of the source is 2 V p-p. The source shown in Figure 56
indicates this open-circuit voltage.
1. The input impedance is calculated using the following
formula:
Ω667
)
500500
(
2500
1
500
)
(
2
1
,
=
+×
−
=
+
×
−
=
F
G
F
G
se
IN
R
R
R
R
R
RS
50Ω
VS
2V p-p
RIN, se
667Ω
ADA4950-x
RLVOUT, dm
+VS
–VS
RG
500Ω
RG
500Ω
RF
500Ω
RF
500Ω
VOCM
07957-156
Figure 56. Calculating Single-Ended Input Impedance, RIN
2. To match the 50 Ω source resistance, calculate the
termination resistor, RT, using RT||667 Ω = 50 Ω. The
closest standard 1% value for RT is 53.6 Ω.
ADA4950-x RLVOUT, dm
+VS
–VS
RS
50Ω
RG
500Ω
RG
500Ω
RF
500Ω
RF
500Ω
VOCM
VS
2V p-p
RIN, se
50Ω
RT
53.6Ω
07957-157
Figure 57. Adding Termination Resistor, RT
3. Figure 57 shows that the effective RG in the upper feedback
loop is now greater than the RG in the lower loop due to the
addition of the termination resistors. To compensate for the
imbalance of the gain resistors, add a correction resistor (RTS)
in series with RG in the lower loop. RTS is the Thevenin
equivalent of the source resistance, RS, and the termination
resistance, RT, and is equal to RS||RT.
RTS = RTH = RS||RT = 25.9 Ω
R
S
50Ω
V
S
2V p-p
R
T
53.6Ω
R
TH
25.9Ω
V
TH
1.03V p-p
07957-052
Figure 58. Calculating the Thevenin Equivalent
Note that VTH is greater than 1 V p-p, which was obtained
with RT = 50 Ω. The modified circuit with the Thevenin
equivalent (closest 1% value used for RTH) of the terminated
source and RTS in the lower feedback loop is shown in
Figure 59.
ADA4950-x
R
L
V
OUT, dm
+V
S
–V
S
R
TH
25.5Ω
R
G
500Ω
R
G
500Ω
R
F
500Ω
R
F
500Ω
V
OCM
V
TH
1.03V p-p
R
TS
25.5Ω
07957-059
Figure 59. Thevenin Equivalent and Matched Gain Resistors
Figure 59 presents a tractable circuit with matched feedback
loops that can be easily evaluated.
It is useful to point out two effects that occur with a terminated
input. The first is that the value of RG is increased in both loops,
lowering the overall closed-loop gain. The second is that VTH is
a little larger than 1 V p-p, as it would be if RT = 50 Ω. These two
effects have opposite impacts on the output voltage, and for
large resistor values in the feedback loops (~1 kΩ), the effects
essentially cancel each other out. For small RF and RG, or high
gains, however, the diminished closed-loop gain is not canceled
completely by the increased VTH. This can be seen by evaluating
Figure 59.
The desired differential output in this example is 1 V p-p
because the terminated input signal is 1 V p-p and the closed-
loop gain = 1. The actual differential output voltage, however, is
equal to (1.03 V p-p)(500/525.5) = 0.98 V p-p.
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 22 of 26
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4950-x input common-mode voltage range is shifted
down by approximately one VBE, in contrast to other ADC
drivers with centered input ranges such as the ADA4939-x. The
downward-shifted input common-mode range is especially
suited to dc-coupled, single-ended-to-differential, and single-
supply applications.
For ±5 V operation, the input common-mode voltage range at the
summing nodes of the amplifier is specified as −4.8 V to +3.2 V.
With a 5 V supply, the input common-mode voltage range at the
summing nodes of the amplifier is specified as +0.2 V to +3.2 V.
To avoid nonlinearities, the voltage swing at the +INx and −INx
terminals must be confined to these ranges.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Although the ADA4950-x is well suited to dc-coupled applica-
tions, it is nonetheless possible to use it in ac-coupled circuits.
Input ac coupling capacitors can be inserted between the source
and RG. This ac coupling blocks the flow of the dc common-
mode feedback current and causes the ADA4950-x dc input
common-mode voltage to equal the dc output common-mode
voltage. The ac coupling capacitors must be placed in both
loops to keep the feedback factors matched. Output ac coupling
capacitors can be placed in series between each output and its
respective load.
INPUT SIGNAL SWING CONSIDERATIONS
The input terminals of fully differential amplifiers with external
gain and feedback resistors connect directly to the amplifier
summing nodes; the common-mode voltage swing at these
terminals is generally smaller than the input and output swings.
In most linear applications, the summing node voltages do not
approach levels that result in the forward-biasing of the internal
ESD protection diodes on the amplifier inputs.
Signals at the inputs of the ADA4950-x are applied to the input
side of the gain resistors, and, if caution is not exercised, these
signals can be large enough to forward-bias the ESD protection
diodes. The four inputs that make up the differential signal paths
each have four ESD diodes in series to the negative supply and
one diode to the positive supply; the VOCM input has one ESD
diode to each supply. Figure 60 illustrates the ESD protection
circuitry.
ADA4950-x
+
V
S
–V
S
500Ω
500Ω
500Ω
500Ω
250Ω
V
OCM
250Ω
07957-253
×1
×4
×1
×4
×1
×4
×1
×1
×1
×4
Figure 60. Input ESD Protection Circuitry
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4950-x is internally biased with a vol-
tage divider comprising two 50 kΩ resistors across the supplies,
with a tap at a voltage approximately equal to the midsupply
point, [(+VS) + (−VS)]/2. Because of this internal divider, the
VOCM pin sources and sinks current, depending on the externally
applied voltage and its associated source resistance. Relying on
the internal bias results in an output common-mode voltage
that is within approximately 100 mV of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider be used with source resistance less
than 100 Ω. If an external voltage divider consisting of equal
resistor values is used to set VOCM to midsupply with greater
accuracy than produced internally, higher values can be used
because the external resistors are placed in parallel with the
internal resistors. The input VOCM offset listed in the Specifications
section assumes that the VOCM input is driven by a low impedance
voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC; however, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ to a voltage
of nominally midsupply. If multiple ADA4950-x devices share
one ADC reference output, a buffer may be necessary to drive
the parallel inputs.
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 23 of 26
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4950-x is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4950-x as possible. The
thermal resistance, θJA, is specified for the device, including the
exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD51-7.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency
ceramic chip capacitors. It is recommended that two parallel
bypass capacitors (1000 pF and 0.1 μF) be used for each supply.
Place the 1000 pF capacitor closer to the device. Farther away,
provide low frequency bulk bypassing using 10 μF tantalum
capacitors from each supply to ground.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance. When
routing differential signals over a long distance, keep PCB
traces close together, and twist any differential wiring to
minimize loop area. Doing this reduces radiated energy and
makes the circuit less susceptible to interference.
1.30
0.80
0.80
1.30
07957-056
Figure 61. Recommended PCB Thermal Attach Pad (Dimensions in Millimeters)
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
07957-057
Figure 62. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
ADA4950-1/ADA4950-2 Data Sheet
Rev. B | Page 24 of 26
HIGH PERFORMANCE ADC DRIVING
The ADA4950-x is ideally suited for broadband dc-coupled
applications. The circuit in Figure 63 shows a front-end
connection for an ADA4950-1 driving an AD9245 ADC,
with dc coupling on the ADA4950-1 input and output. (The
AD9245 achieves its optimum performance when driven
differentially.) The ADA4950-1 eliminates the need for a
transformer to drive the ADC and performs a single-ended-to-
differential conversion and buffering of the driving signal.
The ADA4950-1 is configured with a single 3.3 V supply and a
gain of 2 for a single-ended input to differential output. The
57.6 Ω termination resistor, in parallel with the single-ended
input impedance of 375 Ω, provides a 50 Ω termination for the
source. The additional 26.7 Ω Thevenin resistance added to the
inverting input balances the parallel impedance of the 50 Ω
source and the termination resistor driving the noninverting
input. The required Thevenin bias voltage of 0.27 VDC applied
to the lower loop is obtained by scaling the VREF output of the
AD9245 and buffering it with the AD8031.
In this example, the 50 Ω signal generator has a 1 V p-p unipolar
open-circuit output voltage, and 0.5 V p-p output voltage when
terminated in 50 Ω. The VOCM input is bypassed for noise reduc-
tion and set externally with 1% resistors to maximize output
dynamic range on the tight 3.3 V supply.
Because the inputs are dc-coupled, dc common-mode current
flows in the feedback loops, and a nominal dc level of 0.76 V is
present at the amplifier input terminals. A fraction of the output
signal is also present at the input terminals as a common-mode
signal; its level is equal to the ac output swing at the noninverting
output, divided down by the feedback factor of the lower loop. In
this example, this ripple is 0.5 V p-p × [276.7/(276.7 + 500)] =
0.18 V p-p. This ac signal is riding on the 0.76 V dc level, producing
a voltage swing between 0.67 V and 0.85 V at the input terminals.
This is well within the specified limits of 0.2 V to 1.5 V.
With an output common-mode voltage of 1.65 V, each ADA4950-1
output swings between 1.4 V and 1.9 V, opposite in phase, provid-
ing a gain of 2 and a 1 V p-p differential signal to the ADC input.
The differential RC section between the ADA4950-1 output and
the ADC provides single-pole low-pass filtering and extra buffering
for the current spikes that are output from the ADC input when
its SHA capacitors are discharged.
The AD9245 is configured for a 1 V p-p full-scale input by
connecting its SENSE pin to VREF, as shown in Figure 63.
33Ω
33Ω
50Ω
57.6Ω
0.1µF
20pF
VIN–
VIN+
AGND
AVDD
AD9245
VREF SENSE
10µF +
0.1µF
V
OUT, dm
= 1V p-p
V
OUT, cm
= +1.65V
1.0V p-p
UNIPOLAR
SIGNAL
SOURCE
ADA4950-1
+3.3
V
500Ω
500Ω
500Ω
500Ω
250Ω
NC
250Ω
NC
26.7Ω
0.1µF
0V
1.0V
0.5V
V
OCM
10kΩ
10kΩ
0.1µF
0.1µF
866Ω
1.0kΩ
0.1µF
AD8031
0.1µF 10µF +
07957-254
Figure 63. ADA4950-1 Driving an AD9245 ADC with Unipolar DC-Coupled Input and Output, Gain = 2
Data Sheet ADA4950-1/ADA4950-2
Rev. B | Page 25 of 26
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12 13
4
EXPOSED
PAD
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.50
0.40
0.30
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS M O-220-WEE D.
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad (CP-16-21)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-220-WG GD-8.
BOTTOM VIEWTOP VIEW
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0. 05 M AX
0.02 NO M
0.203 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FO R P ROPE R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-18-2012-A
0.30
0.25
0.20
PIN 1
INDICATOR
0.20 M I N
2.40
2.30 SQ
2.20
EXPOSED
PAD
Figure 65. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad (CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Ordering Quantity
Branding
ADA4950-1YCPZ-R2 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-21 250 H1L
ADA4950-1YCPZ-RL −40°C to +105°C 16-Lead LFCSP_WQ CP-16-21 5,000 H1L
ADA4950-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-21 1,500 H1L
ADA4950-1YCP-EBZ Evaluation Board
ADA4950-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP_WQ CP-24-14 250
ADA4950-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP_WQ CP-24-14 5,000
ADA4950-2YCPZ-R7 −40°C to +105°C 24-Lead LFCSP_WQ CP-24-14 1,500
ADA4950-2YCP-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
