TOP (Ver. 1.3) NM7010B+ Datasheet NM7010B+ Datasheet (c)2007 WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at http://www.wiznet.co.kr 0/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. Data Description Ver. 1.0 OCTOBER , 2006 Ver. 1.1 June 29, 2007 Add SPI signal Pin description(A14-A11) Ver.1.2 July 24, 2007 PHY Chip Change (RTL8201CP -> IP101A) For more information, refer to NM7010B+ schematic. Ver.1.3 January 9, 2008 Release with NM7010B+ Launching NM7010B+ Datasheet Revision TOP Document History Information Add power consumption in Feature 2/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an answer as soon as possible. NM7010B+ Datasheet If you have something to ask about WIZnet Products, Write down your question on TOP WIZnet's Online Technical Support 3/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. Introduction .................................................................................5 1.1. Features ..................................................................................5 1.2. Block Diagram ...........................................................................5 2. Pin Assignments & descriptions ....................................................... 6 2.1. Pin Assignments .........................................................................6 2.2. Power & Ground .........................................................................7 2.3. MCU Interfaces ..........................................................................8 2.4. Network status & LEDs ............................................................... 10 2.5. Miscellaneous Signals ................................................................ 10 3. Timing Diagrams......................................................................... 11 3.1. Reset Timing ......................................................................... 11 3.2. Register/Memory READ Timing ..................................................... 12 3.3. Register/Memory WRITE Timing .................................................... 13 3.4. SPI Timing .............................................................................. 14 4. 5. 6. 7. Dimensions ................................................................................ 15 Connector Specification ............................................................... 16 Schematic .................................................................................. 17 Partlists ..................................................................................... 19 NM7010B+ Datasheet 1. TOP Table of Contents 4/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. (IP101A), MAG-JACK (RJ45 with X'FMR) with other glue logics. It can be used as a component and no effort is required to interface W3150A+ and PHY chip. The NM7010B+ is an ideal option for users who want to develop their Internet enabling systems rapidly. NM7010B+ consists of W3150A+, Ethernet PHY and MAG-JACK. TCP/IP, MAC protocol layer: W3150A+ Physical layer: Ethernet PHY Connector: MAG-JACK NM7010B+ Datasheet NM7010B+ is the network module that includes W3150A+ (TCP/IP hardwired chip), Ethernet PHY TOP 1. Introduction 1.1. Features Supports 10/100 Base TX Supports half/full duplex operation Supports auto-negotiation and auto crossover detection IEEE 802.3/802.3u Complaints Operates 3.3V with 5V I/O signal tolerance Supports network status indicator LEDs Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP Includes Hardware Ethernet protocols: DLC, MAC Supports 4 independent connections simultaneously Supports MCU bus Interface and SPI Interface Supports Direct/Indirect mode bus access Supports Socket API for easy application programming Interfaces with Two 2.0mm pitch 2 * 14 header pin Maximum Power Consumption is 160mA at 3.3V 1.2. Block Diagram 5/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. Pin Assignments I : Input O : Output I/O : Bi-directional Input and output P : Power NM7010B+ Datasheet 2.1. TOP 2. Pin Assignments & descriptions 6/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 2.2. Power & Ground Type Pin No. Description VCC P JP1 : 1 , JP2 : 24 Power : 3.3 V power supply GND P JP1 : 8, JP1 : 13, Ground JP1 : 24, JP2 : 1 JP2 : 4, JP2 : 7 JP2 : 13, JP2 : 14 NM7010B+ Datasheet Symbol JP2 : 23 7/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP Symbol Type A14 I Pin No. JP1 : 7 Description ADDRESS PIN OR SCLK(Serial Clock) This pin is used to select a register or memory. When asserting SPI_EN pin high, this pin is used to SPI Clock signal Pin. A13 I JP1 : 10 NM7010B+ Datasheet 2.3. MCU Interfaces ADDRESS PIN or /SS (Slave Select) * This pin is used to select a register or memory. When asserting SPI_EN pin high, this pin is used to SPI Slave Select signal Pin. In only SPI Mode, this pin is active low A12 I JP1 : 9 ADDRESS PIN or MOSI (Master Out Slave In) * This pin is used to select a register or memory. When asserting SPI_EN pin high, this pin is used to SPI MOSI signal pin. A11 I/O JP1 : 12 ADDRESS PIN or MISO (Master In Slave Out) * This pin is used to select a register or memory. When asserting SPI_EN pin high, this pin is used to SPI MISO signal pin. A10~A8 A7~A0 I I JP1 : 11, JP1 : 14 Address JP1 : 15 Used as Address[10-8] pin JP1 : 16 ~ JP1 : 23 Address Used as Address[7-0] pin D7~D0 I/O JP2 : 21, JP2 : 22 Data JP2 : 19, JP2 : 20 8 bit-wide data bus JP2 : 17, JP2 : 18 JP2 : 15, JP2 : 16 /CS I JP1 : 5 Module Select : Active low. /CS of W3150A+ /RD I JP1 : 4 Read Enable : Active low. /RD of W3150A+ /WR I JP1 : 3 Write Enable : Active low /WR of W3150A+ 8/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. O JP1 : 2 Interrupt : Active low TOP /INT After reception or transmission it indicates that the By writing values to the Interrupt Status Register of W3150A+ the interrupt will be cleared. All interrupts can be masked by writing values to the IMR of W3150A+ (Interrupt Mask Register). For more details refer to the W3150A+ Datasheet NM7010B+ Datasheet W3150A+ requires MCU attention. 9/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP You can observe the network status using MAC-JACK LEDs. LED interface can be extended to the LED of the main board. Symbol L_COL Type O Pin No. JP2 : 6 Description Collision LED : Active low when collisions occur. Link 100/ACT LED : Active low when linked by 100 L_100ACT O JP2 : 8 NM7010B+ Datasheet 2.4. Network status & LEDs Base TX, and blinking when transmitting or receiving data. L_10ACT O JP2 : 10 L_DUPX O JP2 : 11 L_LINK O JP2 : 12 Link 10/ACT LED : Active low when linked by 10 Base T, and blinking when transmitting or receiving data. Full Duplex LED : Active low when in full duplex operation. Active high when in half duplex operation. Link LED : Active low when linked 2.5. Miscellaneous Signals Symbol Type Pin No. Description Reset : Active low /RESET I JP2 : 2 Reset W3150A, RTL8201BL chip. For complete reset function this pin must be asserted low for at least 10ms. SPI Enable This pin selects Enable/disable W3150A+ SPI Mode This pin is internally pulled low for previous W3150A users. Even if there is no signal SPI_EN I JP2 : 9 connection to this pin, it asserts low internally. So change to new version + W3150A including SPI interface, there is no effort to change previous board design. Low = Disable W3150A+ SPI Mode High = Enable W3150A+ SPI Mode NC - JP1 : 6, 25, 26, 27, 28 Not Connect JP2 : 3, 5, 9, 25, 26, 27, 28 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. 10/19 TOP 3. Timing Diagrams NM7010B+ Datasheet NM7010B+ provides following interfaces of W3150A+ -. Direct/Indirect mode bus access -. SPI access Reset Timing 3.1. Symbol Parameter tRST Reset Cycle Time tRLC /RESET to internal PLOCK Min Max 2 us - - 10 ms 11/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 3.2. Register/Memory READ Timing NM7010B+ Datasheet Symbol Parameter Min Max 80 ns - tRC Read Cycle Time tCVO /CS to Valid Output - 80 ns tRVO /RD to Valid Output - 80 ns tCLZ /CS to Low-Z Output 0 ns - tRLZ /RD to Low-Z Output 0 ns - tCHZ /CS to High-Z Output - 1 ns tRHZ /RD to High-Z Output - 1 ns 12/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 3.3. Register/Memory WRITE Timing NM7010B+ Datasheet Symbol Parameter Min Max tWC Write Cycle Time 70 ns - tCW /CS to Write End 70 ns - tWP /WR Pulse width 63 ns - tSD /WR low to SD valid - 14 ns tHD Data Hold from Write End 0 ns - 13/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 3.4. SPI Timing NM7010B+ Datasheet Description Mode Min 1 /SS low to SCLK Slave 21 ns - 2 Input setup time Slave 7 ns - 3 Input hold time Slave 28 ns - 4 Output time Slave 7 ns 14 ns 5 Output hold time Slave 21 ns - 6 SLKC time Slave 70 ns setup Max 14/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 4. Dimensions NM7010B+ Datasheet Symbols Dimensions (mm) A 48.0 B 4.0 C 25.0 D 22.4 E 18.4 F 1.0 G 2.0 H 2.0 I 16.0 J 13.4 15/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 5. Connector Specification NM7010B+ Datasheet UNIT:mm 16/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 6. Schematic NM7010B+ Datasheet 17/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP [ Parts Revision History ] + Parts Before W3150A + RTL8201CP R1 : 4.7K OHM ARRAY R4 : 1K OHM R8 : 2K OHM 1% U3 : RTL8201CP After W3150A+ + IP101A-LF R1 : Not mounted R4 : Not mounted R8 : 6.2K OHM 1% U3 : IP101A-LF NM7010B+ Datasheet Description If you have the hardware having previous parts, refer to the NM7010B+ datasheet V1.1 for the usage. For more stable operation, we recommend using the part revised hardware. 18/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved. TOP 7. Partlists Q.ty Reference Part Tech. Characteristics Package 1 1 CP1 22uF 16Vmin 10% EIA/IECQ 3528 2 1 CP2 2.2uF 10Vmin 10% EIA/IECQ 3216 3 1 CP3 10uF 10Vmin 10% EIA/IECQ 3216 0.1uF 50V-20% Ceramic CASE 0603 50V-20% Ceramic CASE 0603 C1,C2,C3,C4,C5, NM7010B+ Datasheet Item C6,C7,C8,C9,C10, 4 17 C11,C12,C14,C15, C17,C18,C19 5 2 C13,C16 18pF 6 1 D1 1SS181 Switching Diode 2 JP2,JP1 SC-59 2X14 28PIN 2mm DIP 7 STRAIGHT Header 2 X 14 2mm pitch 8 2 L3,L1 120R Chip Ferrite Bead 120R@100MHz 300mA CASE 0603 9 1 L2 4.7uH Chip Ferrite Inductor 4.7uH, 50mA CASE 0805 10 0 R4 1K NOT MOUNTED 11 1 R6 1.5K 1/10W-5% SMD CASE 0603 12 1 R8 6.2K 1% 1/10W-1% SMD CASE 0603 13 2 R12,R3 200 1/10W-5% SMD CASE 0603 14 4 R5,R7,R9,R11 51 1% 1/10W-1% SMD CASE 0603 15 1 R10 4.7K 1/10W-5% SMD CASE 0603 16 1 R2 4.7K Chip Array(0603 X 4) 50V-5% SMD Chip-Array CASE 1206 17 0 R1 4.7K Chip Array(0603 X 4) NOT MOUNTED 18 1 U1 W3150A 19 1 U3 IP101A 1 U2 + LQFP64 LQFP48 RD1-125BAG1A MAG20 21 Transformer + RJ45 JACK 1 Y1 25MHz Crystal Holder Type, CL=18pF ATS-25U NM7010B+ REV1.0 FR4 22 1 1.6T 4LAYER PRINTED CIRCUIT BOARD 19/19 (c) Copyright 2007 WIZnet Co., Inc. All rights reserved.