PL135-27
Low Power, 1.62V to 3.63V, 10MHz to
40MHz, 1:2 Oscillator Fanout Buffer
Revision 2.0
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • US A • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September
8, 2014
Revision 2.0
tcghelp@micrel.com or (408) 955-1690
General Description
The PL135-27 is an advanced oscillator fanout buffer
design for high performance, low-power, small form-factor
applicat ions. T he PL135-2 7 accepts a fundam ental cr ystal
input of 10MHz to 40MHz and produces two LVCMOS
outputs of the same fr eque nc y. The PL13 5-27 is desi gned
to fit in a sm a ll 2mm × 1.3mm DFN pack age and off ers the
best phase noise, jitter performance and lowest power
consumption of any comparable IC.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• Advanced oscillator des ign f or wide frequency coverage
• Two LVCMOS outputs
• 8mA output drive strength
• Input/output frequency: 10MHz to 40MHz fundamental
crystal
• Very low jitter and phase noise
• Low current consumption
• Single 1.62V to 3.63V power supply
• Availa b le in 2.0mm × 1.3mm DFN-6L, GREEN/RoHS-
compliant package
Block Diagram
Micrel, Inc.
PL135-27
, 2014 2 Revision 2.0
Ordering Information
Part Number Ambient Temperature Range Marking
(1)
Package
PL135-27GC-R 0°C to +70°C J27
LLL 6-Pin 2.0mm × 1.3mm DFN
PL135-27GI-R -40°C to +85°C
Note:
1. LLL designat es l ot number.
Pin Configuration
6-Lead DFN
Pin Description
Pin Number
DFN-6L Pin Name Type Pin Description
1 XIN I Crystal input
2 CLK1 O Clock output
3 GND P GND connection
4 CLK0 O Clock output
5 VDD P VDD connection
6 XOUT O Crystal output
Micrel, Inc.
PL135-27
, 2014 3 Revision 2.0
Absolute Maximum Ratings(2)
Supply Voltage (VDD) .................................... –0.5V to +4.6V
Output Voltage (VOUT) ............................ –0.5V to VDD+0.5V
Storage Temperature (TS) ......................... –65°C to +150°C
Operating Ratings(3)
Suppl y Voltage (VDD) ................................ +1.62V to +3.63V
Ambient Temperature (TA) .......................... –40°C to +85°C
AC Electrical Characteristics
VDD = 1.8V ±10%, 2.5V ±10% or 3.3V ±10%; CL = 15pF; TA = -40°C to +85°C, unless otherwise noted
Symbol Parameter Condition Min. Typ. Max. Units
FX Crystal Input Frequency Fundamental crystal 10 40 MHz
tSETTLE Settling Time At Power-Up (VDD > 1.62V) 2 ms
dF/dVDD VDD Sensitivity Frequency vs. VDD, ±10% -0.5 0.5 ppm
tR Output Rise Time 10/90% VDD, VDD=3.3V 2 3 ns
tF Output Fall Time 90/10% VDD, VDD=3.3V 2 3 ns
tSKEW Output to Output Skew 500 ps
D-C Duty Cycle 45 50 55 %
Notes:
2. Exceeding the absolute maximum ratings may damage the device.
3. The device is not guarant eed to function outside its operati ng ratings.
DC Electrical Characteristics
VDD = 1.8V ±10%, 2.5V ±10% or 3.3V ±10%; CL = 15pF; TA = -40°C to +85°C, unless otherwise noted
Symbol Parameter Condition Min. Typ. Max. Units
IDD Supply Current, Dynamic
VDD = 3.3V, 25MHz, No Load 1.6 mA
VDD = 2.5V, 25MHz, No Load 1.2 mA
VDD = 1.8V, 25MHz, No Load 0.9 mA
VDD Operating Voltage 1.62 3.63 V
VOL Output Low Voltage IOL = +4mA, 3.3V 0.4 V
VOH Output High Voltage IOH = -4mA, 3.3V 2.4 V
IOSD Output Current VOL = 0.4V, VOH = 2.4V 8 mA
Crystal Specificatio ns
VDD = 1.8V ±10%, 2.5V ±10% or 3.3V ±10%; CL = 15pF; TA = -40°C to +85°C, unless otherwise noted
Symbol Parameter Condition Min. Typ. Max. Units
FXIN Fundamental Crystal
Resonator Frequency 10 40 MHz
CL(xtal) Crystal Loading Rating 12 pF
PD Operating Drive Level 0.1 2 mW
C0 Shunt Capacitance 5.5 pF
ESR Effective Series Resistance C0 ≤ 5.5pF 40 Ω
C0 ≤ 2.5pF 60 Ω
Micrel, Inc.
PL135-27
, 2014 4 Revision 2.0
Layout Recommendations
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerati o n s
• Keep traces short.
• Trace = Inductor. With a capacitive load this equals
ringing.
• Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
• Design long traces as “striplines” or “microstrips” with
defined impedance.
• Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
• Place decoupling capacitors as close as possible to the
VDD pin(s) to limit noise from the power supply
• Multiple VDD pins should be decoupled separately for
best performance.
• Addition of a ferrite bead in series with VDD can help
prevent noise from other board sources
• Value of decoupling capacitor is frequency dependent.
Typical value to use is 0.1µF.
Micrel, Inc.
PL135-27
, 2014 5 Revision 2.0
Package Information(4)
6-Lead DFN
Note:
4. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
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