Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Bt497A/498A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDACTM The Bt497A/8A is designed specifically for high-performance, high-resolution color graphics applications. The architecture enables the display of true-color 1920 x 1200 bit-mapped color graphics at 75 Hz refresh rates. The wide input pixel port and internal multiplexing modes enable TTL-compatible interfacing to the frame buffer, while maintaining PLL-generated 240 MHz, or externally provided 240 MHz video data rates required for high-refresh-rate, high-resolution color graphics. The Bt497A/8A supports PLL pixel clock generation, supporting a variety of frequencies using an M/N divisor scheme. This decreases system cost due to the elimination of multiple crystal oscillators that are used to support a variety of monitor and refresh rates. The Bt497A/8A contains three 1K x 8 color lookup tables for color-space flexibility, triple 8-bit video D/A converters, a 64 x 64 x 2 programmable cursor, and a fully programmable video timing generator. The Bt497A/8A RAMDAC allows different display modes of operation for each pixel. Utilizing a window-type scheme, each set of pixel and control bits maps the accompanying pixel data to a user-defined display mode. The window identification index addresses a color model table which determines the description of pixel data. For example, separate windows displaying 24-plane true color, 8-plane pseudo color, and 24-plane double-buffer true color can exist within a single frame. A programmable setup (0 or 7.5 IRE) is included. Distinguishing Features * * * * * * * * * * * * * * * * Functional Block Diagram VAA GND CLOCK CLOCK* Applications XTAL[1] XTAL[2] Pixel Clock PLL Clock MPX GPCLK Pixel Load Control Color Model Selection P[127:0] VREF * * * * * FSADJ General Purpose PLL LD SC* PLL pixel clock generation (M/N) Supports true-color 1920 x 1200 resolutions Up to 128-bit input pixel port width 240 and 160 MHz operation Multiple display modes on a pixel basis High-resolution true-color support 2:1 and 4:1 multiplexed pixel port support Programmable pixel format Three 1K x 8 color palette RAMs 64 x 64 x 2 programmable cursor Programmable setup (0 or 7.5 IRE) VRAM shift clock generation On-chip user-definable video timing generator JTAG support 160-pin (Bt497A), 208-pin (Bt498A) PQFP packages LVTTL (3.3 V) I/O interface Pixel Port Registers High-resolution color 3D graphics CAE/CAD/CAM Image processing Instrumentation Desktop publishing COMP2 COMP 1K x 8 RAM 3 x 8 Cursor LUT IOR 1K x 8 RAM 3 x 8 Cursor LUT IOG 1K x 8 RAM IOB 3 x 8 Cursor LUT Bus Control DRAWING* Data Sheet TMS Pipelines CE* R/W C[1,0] LB* Data Bus Mux D[7:0] TCK TDI TDO 497-8_001 Video Timing Generator CSYNC*, VSYNC* 64 x 64 x 2 Cursor RAM JTAG STSCAN FIELD SCEN* Window Lookup Logic Preliminary Information/Conexant Proprietary and Confidential L498A_B June 17, 1999 Ordering Information Model Number Package Operating Temperature Bt497AKHF160 160-Pin PQFP 0-70 C with 100 LFPM airflow Bt498AKHF240 208-Pin PQFP 0-70 C with 100 LFPM airflow Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. The trademarks "Conexant" and the Conexant symbol are trademarks of Conexant Systems, Inc. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. (c) 1999 Conexant Systems, Inc. Printed in U.S.A. All Rights Reserved Reader Response: To improve the quality of our publications, we welcome your feedback. Please send comments or suggestions via e-mail to Conexant Reader Response@conexant.com. Sorry, we can't answer your technical questions at this address. Please contact your local Conexant sales office or local field applications engineer if you have technical questions. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.4 Reading/Writing Color Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.5 Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.6 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.7 Frame Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.8 Color Model Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.9 Color Model Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.10 Color Lookup Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.11 Overlay/Underlay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 1.12 Window Lookup Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 1.13 On-chip Cursor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 1.14 Cursor Color LUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1.15 Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 1.16 Cursor Interlace Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 1.17 Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 1.18 Monitor Identification and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 1.19 Video Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential iii L498A_B Table of Contents 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 2.0 Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Pixel PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 General Purpose PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Pixel Format Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 User Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Shadow-Overlay Window Lookup Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Active-Overlay Window Lookup Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Window Transfer Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Transparent Mask Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Transparent Color Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Window Address Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Shadow-Primary Window Lookup Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Active-Primary Window Lookup Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Signature Analysis Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 DAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Timing Generator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Vertical Blank Negation Point Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Vertical Blank Assertion Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Vertical Sync. Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Vertical Sync. Assertion Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Horizontal Serration Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Horizontal Blank Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Horizontal Blank Assertion Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Horizontal Sync. Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Horizontal Sync. Assertion Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Horizontal SCEN Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Horizontal SCEN Assertion Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Equalizing Pulse Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Equalization Interval Negation Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Equalization Interval Assertion Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Timing Generator Vertical Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Timing Generator Horizontal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Monitor Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Monitor Port Sense Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Cursor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Cursor Position Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 iv Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B Table of Contents 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 3.0 PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4.0 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 5.0 4.1 Test Features of the Bt497A/8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 Signature Analysis Control Register (SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.3 Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.4 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.5 JTAG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.6 Initializing the Bt497A/8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.7 PLL Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.8 Guide to Frame Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential v L498A_B Table of Contents 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC vi Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B List of Figures 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 1-16. Figure 1-17. Figure 1-18. Figure 1-19. Figure 1-20. Figure 1-21. Figure 1-22. Figure 1-23. Figure 1-24. Figure 1-25. Figure 1-26. Figure 1-27. Figure 1-28. Figure 1-29. Figure 1-30. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. L498A_B Bt497A 160-pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Bt498A 208-pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Detailed Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 MPU Full-Word Access Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 PLL Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 CMOS Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Differential Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 2:1 Single-Buffered Pixel Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 2:1 Double-Buffered Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 4:1 Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 4/2:1 Single-Buffered Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 4/2:1 Double-Buffered Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 8/2:1 Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Color Model Selection Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Color Model Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 Overlay/Underlay Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 Multi-Chip Window Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 Cursor RAM Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 Cursor Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 Noninterlaced Format Timing Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46 Horizontal Timing and Composite Sync Generation-Noninterlaced Format. . . . . . . . . . . . 1-48 Noninterlaced Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 Horizontal Timing Waveforms-Interlaced Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 Interlaced Horizontal Timing for CSYNC* Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 NTSC Interlaced Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Monitor Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 Monitor Port Sense Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 Composite Video Output Waveform (7.5 IRE Setup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 Composite Video Output Waveform (0 IRE Setup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 Representative Power/Ground Analog Area Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Typical Analog Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Signature Analysis Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 JTAG Boundry Scan Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 CLOCK and XTAL Connections for PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Frame Buffer Interface for Bt497A/8A-Generated VRAM Serial Clock and Pixel Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Latching of First Pixels After BLANK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 CRT Signals at Vertical Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Conexant Preliminary Information/Conexant Proprietary and Confidential vii L498A_B List of Figures 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. viii Video Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 MPU Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Input Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 ECL Clock Input (PLL Bypassed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 160-Pin Metric Quad Flatpack (MQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 208-Pin Metric Quad Flatpack (MQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B List of Tables 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC List of Tables Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 1-9. Table 1-10. Table 1-11. Table 1-12. Table 1-13. Table 1-14. Table 1-15. Table 1-16. Table 1-17. Table 3-1. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. L498A_B Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 208-pin PQFP Pin Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 160-pin PQFP Pin Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 MPU Interface Address Map-Control Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Configuration Address Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Cursor Address Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Serial Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Pixel Port Naming Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Window Look-Up Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Pixel Format Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Color Model Control WLUT Linked Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Overlay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 Cursor Color LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 Internal Timing Generator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 CSYNC* Output: HSYNC* and VSYNC* Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 Video Output Truth Table (7.5 IRE Setup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 Video Output Truth Table (0 IRE Setup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 Typical Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 JTAG Bidirectional Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 JTAG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 1280 x 1024 Noninterlaced Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 NTSC Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 PAL Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Pixel Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 GPCLK PLL Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Analog Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 PLL Clock Generation Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 MPU Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Serial Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Pixel and LD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Package Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Conexant Preliminary Information/Conexant Proprietary and Confidential ix L498A_B List of Tables 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC x Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B 1 1.0 Circuit Description 1.1 Introduction The Bt497A and Bt498A are software-compatible RAMDACs designed for high-performance and high-resolution applications. The architecture supports a 1280 x 1024 160 MHz (Bt497A) or up to a 1920 x 1200 240 MHz (Bt498A) bit-mapped color-graphics display. Two on-chip Phase Lock Loops (PLL) eliminate the high-speed signals on the Printed Circuit Board (PCB) and reduce the need for multiple, expensive Emitter-Coupled Logic (ECL) crystal oscillators required to support multiple monitors and refresh rates. The PLLs use an M/(L x N) scheme to program over 500 unique pixel clock or general purpose clock frequencies. The Bt497A/8A allows different display modes of operation for each pixel. Utilizing a window attribute scheme, the control bits of every pixel are used to map the pixel data to a pre-defined display mode (pseudo color from three 1K x 8 color lookup tables or nonlinear true color) or to create an overlay image. Control bits on the Bt497A/8A define the pixel port source to accommodate double-buffered operation for animation. The 128-pin pixel port supports a standard 2:1 and 4:1 format, as well as 4/2:1 and 8/2:1 interleaved format used in high-end 3D graphics Video RAMs (VRAMs). The Bt497A/8A provides an on-chip, user-definable, three-color, 64 x 64 bit-map cursor and a programmable timing generator. With the timing generator, users now achieve full control of sync and blank characteristics, for both interlaced and progressive scanned systems, that previous RAMDACs required externally. Video control can be sent to the monitor on discrete sync outputs or on green (IOG) analog output. The Bt497A/8A contains three 8-bit DACs programmable with a 7.5 IRE pedestal. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-1 L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.2 Pin Descriptions Figure 1-1 illustrates the Bt497A is packaged in a 160-pin Plastic Quad Flatpack (PQFP). Figure 1-2 illustrates the Bt498A is a 208-pin PQFP. Table 1-1 lists the pin descriptions, labels, and I/O assignments for both packages. 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 N/C PA[21] PA[22] PA[23] N/C GND VAA5 PA[24] N/C PA[25] PA[26] PA[27] PA[28] N/C PA[29] N/C PA[30] PA[31] N/C LD GND PA[32] N/C PA[33] PA[34] PA[35] N/C PA[36] PA[37] PA[38] N/C PA[39] VAA5 GND PA[40] PA[41] PA[42] N/C PA[43] N/C Figure 1-1. Bt497A 160-pin PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Bt497A 160-Pin PQFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VAA3 PA[44] PA[45] PA[46] PA[47] N/C VAA5 GND PA[48] PA[49] PA[50] N/C PA[51] PA[52] N/C PA[53] PA[54] N/C PA[55] N/C VAA5 GND PA[56] N/C PA[57] PA[58] N/C PA[59] PA[60] PA[61] PA[62] PA[63] FIELD SCEN* STSCAN SC* SCL GPCLK GND VAA3 1-2 Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_002 GND IOR VAA5 IOG GND IOIB VAA5 GND VREF FSADJ VAA5 COMP COMP2 RANGE VAA5 GND XTAL[2] XTAL[1] VAA5 GND CLOCK CLOCK* CSYNC* RESET* CE* R/W C[0] C[1] LB* GND D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] VSYNC* SDA 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VAA3 PA[20] PA[19] N/C PA[18] PA[17] PA[16] VAA5 GND N/C PA[15] PA[14] PA[13] N/C PA[12] PA[11] N/C PA[10] PA[9] PA[8] VAA5 GND N/C PA[7] N/C PA[6] N/C PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] GND TDO TDI TMS TCK TRST* VAA3 L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.2 Pin Descriptions 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 PB[52] PA[21] PB[53] PA[22] PB[54] PA[23] PB[55] GND VAA5 PA[24] PB[56] PA[25] PB[57] PA[26] PB[58] PA[27] PB[59] PA[28] PB[60] PA[29] PB[61] PA[30] PB[62] PA[31] PB[63] LD GND PA[32] PB[0] PA[33] PB[1] PA[34] PB[2] PA[35] PB[3] PA[36] PB[4] PA[37] PB[5] PA[38] PB[6] PA[39] PB[7] VAA5 GND PA[40] PB[8] PA[41] PB[9] PA[42] PB[10] PA[43] Figure 1-2. Bt498A 208-pin PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Bt498A 208-Pin PQFP 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VAA3 PB[11] PA[44] PB[12] PA[45] PB[13] PA[46] PB[14] PA[47] PB[15] VAA5 GND PA[48] PB[16] PA[49] PB[17] PA[50] PB[18] PA[51] PB[19] PA[52] PB[20] PA[53] PB[21] PA[54] PB[22] PA[55] PB[23] VAA5 GND PA[56] PB[24] PA[57] PB[25] PA[58] PB[26] PA[59] PB[27] PA[60] PB[28] PA[61] PB[29] PA[62] PB[30] PA[63] PB[31] FIELD SCEN* STSCAN SC* SCL GPCLK L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_003 VAA3 VAA5 GND IOR VAA5 IOG GND VAA5 IOB VAA5 GND VAA5 VREF FSADJ GND VAA5 COMP COMP2 RANGE VAA5 GND GND XTAL[2] XTAL[1] VAA5 GND GND CLOCK CLOCK* CSYNC* RESET* DRAWING* CE* R/W C[0] C[1] LB* GND GND D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] VSYNC* SDA GND GND VAA3 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VAA3 PA[20] PB[51] PA[19] PB[50] PA[18] PB[49] PA[17] PB[48] PA[16] VAA5 GND PB[47] PA[15] PB[46] PA[14] PB[45] PA[13] PB[44] PA[12] PB[43] PA[11] PB[42] PA[10] PB[41] PA[9] PB[40] PA[8] VAA5 GND PB[39] PA[7] PB[38] PA[6] PB[37] PA[5] PB[36] PA[4] PB[35] PA[3] PB[34] PA[2] PB[33] PA[1] PB[32] PA[0] GND TDO TDI TMS TCK TRST* 1-3 L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-1. Pin Assignments (1 of 3) Pin Count Description I/O/Z 8 D[7:0] I/O/Z 2 C[1,0] I MPU Control Bus Input (LVTTL Compatible). 1 R/W I MPU Read/Write Control Input (LVTTL Compatible). Defines the transaction direction. 1 LB* I MPU Low Byte Control (LVTTL Compatible). 1 CE* I Chip Enable Control Input (LVTTL Compatible). This input must be a logical 0 to enable data to be written to or read from the device. During write operations, data is internally registered on the rising edge of CE*. Avoid glitches on this edge-triggered input. P[63:0](A,B) I Pixel Port Inputs (LVTTL Compatible). These inputs have internal pullup resistors that cause the logic level to be high if they are left unconnected. Bt497A PA[63:0]. 1 LD I Pixel Port Load Clock (LVTTL Compatible). The rising edge of this signal captures input pixel data. 1 SC* O Serial Clock Output (LVTTL Compatible). The pixel clock divider produces this signal. It is used as the clock for the serial port of the video memory. 1 SCEN* O Serial Clock Enable Output (LVTTL Compatible). The timing generator produces this signal and controls the serial port of the video memory. 1 STSCAN O Horizontal Scan Line Indicator (LVTTL Compatible). The timing generator produces this signal and is used by external circuitry to index the serial port of the video memory. 1 FIELD I/O/Z 1 XTAL1 I Crystal Input. This input is either connected to a crystal or driven by a CMOS oscillator. The internal phase lock loop generates the pixel clock using this input. 1 XTAL2 O Crystal Amplifier Output. This output connects to the second terminal of the crystal when used. 1 GPCLK O General Purpose Clock Output. The GPCLK PLL Control Register determines the frequency. 1 DRAWING* I/O/Z Open-drain signal used for coordinating WLUT updates among multiple Bt498A devices. 2 CLOCK, CLOCK* I Clock Inputs. These differential clock inputs are driven by ECL logic configured for single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. 1 VREF I Voltage Reference Input. An external voltage reference circuit must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended. Any low-frequency power supply noise on VREF is directly coupled onto the analog outputs. A 0.1 F ceramic capacitor must be used to decouple this input to VAA5. The decoupling capacitor must be as close as possible to the device to keep lead lengths to an absolute minimum. 128 1-4 Signal Name MPU Data Bus (LVTTL Compatible). Bidirectional data. The MPU port zero-fills unused bits on data reads. Odd Field Indicator (LVTTL Compatible). The timing generator produces this signal and is used by external circuitry to index the serial port of the video memory. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-1. Pin Assignments (2 of 3) Pin Count Signal Name I/O/Z Description 2 COMP, COMP2 -- Compensation pins. These pins provide compensation for the internal reference amplifier. A 0.1 F ceramic capacitor must be connected between these two pins. 1 RANGE -- Compensation for VCO. A 0.01 F ceramic chip capacitor and a 4.7 F tantalum capacitor must be connected between this pin and adjacent VAA5. 1 FSADJ I Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. The IRE relationships in Figures 1-29 and 1-30 are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG is RSET () = K1 * VREF (V) / IOG (mA) The full-scale output current on IOR and IOB for a given RSET is IOR, IOB (mA) = K2 * VREF (V) / RSET () where K1 and K2 are defined as: Setup IOG IOR, IOB 7.5 IRE K1 = 3052 K2 = 2180 0 IRE K1 = 2888 K2 = 2016 1 IOR O Red analog current output. 1 IOG O Green analog current output. 1 IOB O Blue analog current output. 1 VSYNC* O Vertical Sync Output. Active low on reset, but can be programmed active high via DAC control register. 1 CSYNC* O Composite Sync Output. Active low on reset, but can be programmed active high via DAC control register. 1 SDA I/O/Z Serial Monitor Port Data. Open Drain pin. 1 SCL I/O/Z Serial Monitor Port Clock. Open Drain pin. 1 RESET* I Reset Input (LVTTL Compatible). This is the reset signal. Its assertion causes a number of actions, these are described in Initializing the Bt497A/8A in the Applications Information section. 1 TRST* I Test Reset (LVTTL compatible). JTAG input pin is asserted at power-on to force all the boundary scan cells to their normal, non-JTAG state. The transitions on this signal reset the JTAG state machine. When not performing JTAG operations, this pin should be driven to a logic high. 1 TMS I Test Mode Select (LVTTL compatible). JTAG input pin whose transitions drive the JTAG state machine through its sequences. When not performing JTAG operations, this pin should be driven to a logic high. 1 TCK I Test Clock (LVTTL compatible). Used to synchronize all JTAG test structures. Maximum clock rate for this pin is 50 MHz. When not performing JTAG operations, this pin should be driven to a logic high. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-5 L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-1. Pin Assignments (3 of 3) Pin Count Signal Name I/O/Z Description 1 TDI I Test Data In (LVTTL compatible). JTAG input pin used for loading instructions to the TAP controller or to load test vector data for boundary scan operation. When not performing JTAG operations, this pin should be driven to a logic high. 1 TDO O Test Data Out (LVTTL compatible). JTAG output used for verifying test results of all JTAG sampling operations. This pin is active for certain JTAG sequences, and is three-stated at all other times. When not performing JTAG operations, this pin should be left floating. 4 VAA3 -- +3.3 V Power Supply. All VAA3 pins must be connected together. 14 VAA5 -- +5.0 V Power Supply. All VAA5 pins must be connected together. (Bt497A: 10 pins) 20 GND -- Ground. (Bt497A: 15 pins) NOTE(S): 1. I = Input, O = Output, Z = Three-state. 2. Power-Up Sequence: VAA5, which supplies both a 5 V analog section and a 5 V digital section of the Bt497A/498A, should be powered up at the same time as VAA3. If VAA5 and VAA3 cannot be powered up at the same time, the power-up sequence should be to power VAA5 first with VAA3 being powered up within 2 ms of VAA5. VAA5 -> VAA3 Since most designs have VAA5 and VDD5(VAA5 digital power pins) tied together, this should not be a problem. If the designer wishes to separate the VAA5 analog and digital sections, VAA5 digital must be powered up within 2 s of VAA5 analog (power pins next to the IOR, IOG, and IOB). In other words, the sequence would be as follows: VAA5 analog -> VAA5 digital -> VAA3. 1-6 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC u Table 1-2. 160-pin PQFP Pin Labels Pin Pin Label Pin Pin Label Pin Pin Label Pin Pin Label Pin Pin Label 1 VAA3 33 PA[0] 65 CE* 97 N/C 129 PA[39] 2 PA[20] 34 GND 66 R/W 98 PA[56] 130 N/C 3 PA[19] 35 TDO 67 C[0] 99 GND 131 PA[38] 4 N/C 36 TDI 68 C[1] 100 VAA5 132 PA[37] 5 PA[18] 37 TMS 69 LB* 101 N/C 133 PA[36] 6 PA[17] 38 TCK 70 GND 102 PA[55] 134 N/C 7 PA[16] 39 TRST* 71 D[0] 103 N/C 135 PA[35] 8 VAA5 40 VAA3 72 D[1] 104 PA[54] 136 PA[34] 9 GND 41 GND 73 D[2] 105 PA[53] 137 PA[33] 10 N/C 42 IOR 74 D[3] 106 N/C 138 N/C 11 PA[15] 43 VAA5 75 D[4] 107 PA[52] 139 PA[32] 12 PA[14] 44 IOG 76 D[5] 108 PA[51] 140 GND 13 PA[13] 45 GND 77 D[6] 109 N/C 141 LD 14 N/C 46 IOB 78 D[7] 110 PA[50] 142 N/C 15 PA[12] 47 VAA5 79 VSYNC* 111 PA[49] 143 PA[31] 16 PA[11] 48 GND 80 SDA 112 PA[48] 144 PA[30] 17 N/C 49 VREF 81 VAA3 113 GND 145 N/C 18 PA[10] 50 FSADJ 82 GND 114 VAA5 146 PA[29] 19 PA[9] 51 VAA5 83 GPCLK 115 N/C 147 N/C 20 PA[8] 52 COMP 84 SCL 116 PA[47] 148 PA[28] 21 VAA5 53 COMP2 85 SC* 117 PA[46] 149 PA[27] 22 GND 54 RANGE 86 STSCAN 118 PA[45] 150 PA[26] 23 N/C 55 VAA5 87 SCEN* 119 PA[44] 151 PA[25] 24 PA[7] 56 GND 88 FIELD 120 VAA3 152 N/C 25 N/C 57 XTAL[2] 89 PA[63] 121 N/C 153 PA[24] 26 PA[6] 58 XTAL[1] 90 PA[62] 122 PA[43] 154 VAA5 27 N/C 59 VAA5 91 PA[61] 123 N/C 155 GND 28 PA[5] 60 GND 92 PA[60] 124 PA[42] 156 N/C 29 PA[4] 61 CLOCK 93 PA[59] 125 PA[41] 157 PA[23] 30 PA[3] 62 CLOCK* 94 N/C 126 PA[40] 158 PA[22] 31 PA[2] 63 CSYNC* 95 PA[58] 127 GND 159 PA[21] 32 PA[1] 64 RESET* 96 PA[57] 128 VAA5 160 N/C L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-7 L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-3. 208-pin PQFP Pin Labels (1 of 2) Pin Pin Label Pin Pin Label Pin Pin Label Pin Pin Label Pin Pin Label 1 VAA3 43 PB[33] 85 CE* 127 GND 169 PA[38] 2 PA[20] 44 PA[1] 86 R/W 128 VAA5 170 PB[5] 3 PB[51] 45 PB[32] 87 C[0] 129 PB[23] 171 PA[37] 4 PA[19] 46 PA[0] 88 C[1] 130 PA[55] 172 PB[4] 5 PB[50] 47 GND 89 LB* 131 PB[22] 173 PA[36] 6 PA[18] 48 TDO 90 GND 132 PA[54] 174 PB[3] 7 PB[49] 49 TDI 91 GND 133 PB[21] 175 PA[35] 8 PA[17] 50 TMS 92 D[0] 134 PA[53] 176 PB[2] 9 PB[48] 51 TCK 93 D[1] 135 PB[20] 177 PA[34] 10 PA[16] 52 TRST* 94 D[2] 136 PA[52] 178 PB[1] 11 VAA5 53 VAA3 95 D[3] 137 PB[19] 179 PA[33] 12 GND 54 VAA5 96 D[4] 138 PA[51] 180 PB[0] 13 PB[47] 55 GND 97 D[5] 139 PB[18] 181 PA[32] 14 PA[15] 56 IOR 98 D[6] 140 PA[50] 182 GND 15 PB[46] 57 VAA5 99 D[7] 141 PB[17] 183 LD 16 PA[14] 58 IOG 100 VSYNC* 142 PA[49] 184 PB[63] 17 PB[45] 59 GND 101 SDA 143 PB[16] 185 PA[31] 18 PA[13] 60 VAA5 102 GND 144 PA[48] 186 PB[62] 19 PB[44] 61 IOB 103 GND 145 GND 187 PA[30] 20 PA[12] 62 VAA5 104 VAA3 146 VAA5 188 PB[61] 21 PB[43] 63 GND 105 GPCLK 147 PB[15] 189 PA[29] 22 PA[11] 64 VAA5 106 SCL 148 PA[47] 190 PB[60] 23 PB[42] 65 VREF 107 SC* 149 PB[14] 191 PA[28] 24 PA[10] 66 FSADJ 108 STSCAN 150 PA[46] 192 PB[59] 25 PB[41] 67 GND 109 SCEN* 151 PB[13] 193 PA[27] 26 PA[9] 68 VAA5 110 FIELD 152 PA[45] 194 PB[58] 27 PB[40] 69 COMP 111 PB[31] 153 PB[12] 195 PA[26] 28 PA[8] 70 COMP2 112 PA[63] 154 PA[44] 196 PB[57] 29 VAA5 71 RANGE 113 PB[30] 155 PB[11] 197 PA[25] 30 GND 72 VAA5 114 PA[62] 156 VAA3 198 PB[56] 31 PB[39] 73 GND 115 PB[29] 157 PA[43] 199 PA[24] 32 PA[7] 74 GND 116 PA[61] 158 PB[10] 200 VAA5 33 PB[38] 75 XTAL[2] 117 PB[28] 159 PA[42] 201 GND 34 PA[6] 76 XTAL[1] 118 PA[60] 160 PB[9] 202 PB[55] 35 PB[37] 77 VAA5 119 PB[27] 161 PA[41] 203 PA[23] 1-8 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.2 Pin Descriptions 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-3. 208-pin PQFP Pin Labels (2 of 2) Pin Pin Label Pin Pin Label Pin Pin Label Pin Pin Label Pin Pin Label 36 PA[5] 78 GND 120 PA[59] 162 PB[8] 204 PB[54] 37 PB[36] 79 GND 121 PB[26] 163 PA[40] 205 PA[22] 38 PA[4] 80 CLOCK 122 PA[58] 164 GND 206 PB[53] 39 PB[35] 81 CLOCK* 123 PB[25] 165 VAA5 207 PA[21] 40 PA[3] 82 CSYNC* 124 PA[57] 166 PB[7] 208 PB[52] 41 PB[34] 83 RESET* 125 PB[24] 167 PA[39] -- -- 42 PA[2] 84 DRAWING* 126 PA[56] 168 PB[6] -- -- L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-9 L498A_B 1.0 Circuit Description 1.3 MPU Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.3 MPU Interface As illustrated in Figure 1-3, the Bt497A/8A supports a standard Microprocessor Unit (MPU) bus interface. The MPU can access the internal control registers and color palettes. The on-chip color palette RAM and cursor color registers support color updating with minimum contention to the display refresh process. All MPU words are 32 bits in length and require four CE* cycles. Accesses are performed in two modes, direct and indirect. The modes are differentiated by encoding the control bits C[0] and C[1], as listed in Table 1-4. Indirect access requires an address pointer is written through the MPU port. The direct access pointer is read through the MPU port. All indirect MPU accesses generate an auto-increment function in the word dimension. The first CE* cycle asserts the LB* signal to indicate the least significant byte for every MPU access. D[0] corresponds to the Least Significant Bit (LSB) of each byte. Figure 1-4 illustrates the MPU read timing. Table 1-5 and Table 1-6 illustrate how the C0 and C1 control inputs work in conjunction with the internal address register to specify which configuration or cursor function register is accessed by the MPU. The MPU zero-fills reserved bits on data reads. Toggling the RESET* pin presets the internal registers to the values shown in Table 1-5 and Table 1-6. 1-10 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.3 MPU Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-3. Detailed Functional Block Diagram D[7:0] C[1, 0] R/W CE RESET* LB* MPU Port Interface Logic Address Pointers Data Registers 64 x 7 RAM Primary WID LUT 4 x 9 RAM Overlay WID LUT Transfer Control Logic Overlay/underlay Logic CMC[5] Port A[63:0] X[7:0] Monitor Serial Port Color Model Selection X[7:0] R[7:0] G[7:0] B[7:0] 1K x 8 RAMLUT Port B[63:0] 1K x 8 RAMLUT 1K x 8 RAMLUT SDA, SCL Pseudo Color Direct Color DAC IOR DAC IOG DAC IOB Pixel Port Pixel Input Registers and Serialization Cursor Logic Serialization 64 x 64 x 2 Bit Map CDATA[1,0] Nonlinear True Color Diagnostic Registers and Control Logic 3 x 8 RAM Cursor LUT 3 x 8 RAM Cursor LUT Cursor Color 3 x 8 RAM Cursor LUT CRSR Select Clocks Horizontal, Vertical and Field Values Horizontal, Vertical and Field Values PLL Clock Synthesizer Pixel Clock Divider Timing Generator SYNC and BLANK VSYNC* CSYNC* 497-8_004 LD STSCAN FIELD SCEN* SC* XTAL [1, 2] GPCLK Table 1-4. MPU Interface Address Map-Control Field Definition Control Field Function Access Type Control Bit 1 Control Bit 0 Indirect 1 1 Cursor Address Pointer Direct 1 0 Configuration Functions Indirect 0 1 Direct 0 0 Cursor Functions Configuration Address Pointer L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-11 L498A_B 1.0 Circuit Description 1.3 MPU Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-4. MPU Full-Word Access Timing Diagram LB* C[1,0] CE* 1-12 D[7:0] D[15:8] D[23:16] D[31:24] 497-8_005 D[7:0] Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.3 MPU Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-5. Configuration Address Operation (1 of 2) Pointer Address C[1,0] Reset Value $xxxx 00 N/R Configuration Address Pointer Register $0000 01 $227 Pixel PLL Control Register $0001 01 $A1C General Purpose PLL Control Register $0002-$0FFF 01 N/A Reserved $1000 01 N/R Pixel Format Control Register $1001 01 $0 User Control Register $1002-$1FFF 01 N/A Reserved $2000-$20FF 01 N/R Color Lookup Palette (Red, Green, Blue, xx), Table 0 $2100-$21FF 01 N/R Color Lookup Palette, Table 1 $2200-$22FF 01 N/R Color Lookup Palette, Table 2 $2300-$23FF 01 N/R Color Lookup Palette, Table 3 $2400-$30FF 01 N/A Reserved $3100-$3103 01 N/R Shadow-Overlay Window Lookup Table $3104-$311F 01 N/A Reserved $3120-$3123 01 N/R Active-Overlay Window Lookup Table $3124-$314F 01 N/A Reserved $3150 01 $0 Window Transfer Control Register $3151 01 N/R Transparent Mask Control Register $3152 01 N/R Transparent Color Key Register $3153 01 N/R Window Address Mask Register $3154-$31FF 01 N/A Reserved $3200-$323F 01 N/R Shadow-Primary Window Lookup Table $3240-$327F 01 N/R Active-Primary Window Lookup Table $3280-$4FFF 01 N/A Reserved $5000 01 $00XXXXXX $5001 01 $0 DAC Control Register $5002-$5FFF 01 N/A Reserved $6000 01 $0 Timing Generator Control Register $6001 01 N/R Vertical Blank Negation Point Register $6002 01 N/R Vertical Blank Assertion Point Register $6003 01 N/R Vertical Sync. Negation Point Register $6004 01 N/R Vertical Sync. Assertion Point Register $6005 01 N/R Horizontal Sync. Negation Point Register $6006 01 N/R Horizontal Sync. Negation Point Register L498A_B Function Signature Analysis Control Register Conexant Preliminary Information/Conexant Proprietary and Confidential 1-13 L498A_B 1.0 Circuit Description 1.3 MPU Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-5. Configuration Address Operation (2 of 2) Pointer Address C[1,0] Reset Value Function $6007 01 N/R Horizontal Blank Assertion Point Register $6008 01 N/R Horizontal Sync. Negation Point Register $6009 01 N/R Horizontal Sync. Assertion Point Register $600A 01 N/R Horizontal SCEN Negation Point Register $600B 01 N/R Horizontal SCEN Assertion Point Register $600C 01 N/R Equalizing Pulse Negation Point Register $600D 01 N/R Equalization Interval Negation Point Register $600E 01 N/R Equalization Interval Assertion Point Register $600F 01 $0 Timing Generator Vertical Counter $6010 01 $0 Timing Generator Horizontal Counter $6011 01 N/R Timing Generator Test Register $6012-$7FFF 01 N/A Reserved $8000 01 $A236E1AD Device Identification Register $8001 01 $3 Monitor Port Sense Register $8002 01 N/R Monitor Port Sense Register $8003-$FFFF 01 N/A Reserved NOTE(S): N/R = Register exists, but is not resettable. N/A = Reserved addresses indicate no register exists at the given pointer addresses. User should not attempt to access reserved addresses. Table 1-6. Cursor Address Operation Pointer Address C[1,0] Reset Value Function $xxx 10 N/R Cursor Address Pointer Register $000-$07F 11 N/R Cursor RAM-Plane0 $080-$0FF 11 N/R Cursor RAM-Plane1 $100 11 $0 Cursor Control Register $101-$103 11 N/R Cursor Color Lookup Table (Red, Green, Blue, xx) $104 11 N/R Cursor Position Register $105-$1FF 11 N/A Reserved NOTE(S): N/R = Register exists, but is not resettable. N/A = Reserved addresses indicate no register exists at the given pointer addresses. User should not attempt to access reserved addresses. 1-14 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.4 Reading/Writing Color Data 1.4 Reading/Writing Color Data The MPU loads the appropriate address pointer with the address of the color palette RAM location or cursor color register to be modified to write color data. The MPU performs four successive write cycles: red, green, blue, and a dummy value. During the last write cycle, the 3 bytes of color information are concatenated into a 24-bit word and written to the location specified by the address register. The address register then auto-increments to the next location, which the MPU can modify by simply writing another sequence of red, green, and blue data. To read color data, the MPU loads the address pointer with the address of the color palette RAM location or cursor color register to be read. The MPU performs four successive read cycles: red, green, blue, and 00. Following the last read cycle, the address register increments to the next location, which the MPU can view by simply reading another sequence of color data. NOTE: The MPU reads have priority over display refresh reads to the shared color palette read port. To avoid visual artifacts, it is recommended that MPU reads be restricted to the retrace intervals. 1.5 Additional Information Although the color and cursor color registers are dual ported, if the pixel data is addressing the same palette entry being written to by the MPU during the write cycle, a maximum of 1 pixel may be disturbed. All control registers are written to or read by the MPU at any time. To prevent pixels from being disturbed during writes, to certain control registers, the DAC outputs should be disabled through the User Control Register. Setup times shown in the AC Characteristics section are the minimum required to internally capture the data. NOTE: If an invalid address is loaded into the address pointer, data written to the device will be ignored and invalid data will be read by the MPU. This is not recommended, and could cause problems in Bt497A/8A-compatible products. If an incomplete MPU access occurs, (less than four CE* cycles between LB*s) that access and the following full access are ignored. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-15 L498A_B 1.0 Circuit Description 1.6 Clock Generation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.6 Clock Generation The Bt497A/8A has two on-board PLLs for generating the pixel clock and the GPCLK output pin as illustrated in Figure 1-5. The pixel clock is fully programmable, and able to generate over 500 unique pixel clock frequencies using a single crystal. Figure 1-5. PLL Clock Generation Block Diagram CLOCK CLOCK* SC* MPX XTAL1 Crystal 13 or 14 MHz Pixel Clock PLL M/NxL XTAL2 SC Divider Internal RAMDAC Pixel Clock General Purpose PLL M/NxL GPCLK 497-8_006 MPX The advanced PLLs contain internal loop filters to provide maximum noise immunity and to reduce jitter. Except for the reference crystal or oscillator, no external components or adjustments are necessary. The PLLs use an M/(L x N) scheme to provide precise frequencies. The M, N, and L values are programmed through the command registers with a variety of values, which generally provide frequency granularity that averages less than 1 MHz. M is a binary 7-bit value, N is a binary 4-bit value, and L is selectable to be a value of one, two, four, or eight. An oscillator reference is used by connecting the oscillator's output to the XTAL1 input, using a 10000 pF coupling capacitor, as illustrated in Figure 1-6. For this configuration, the XTAL2 pin is left disconnected. 1-16 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.6 Clock Generation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-6. CMOS Oscillator Interface +5 V Bt497A/8A 1000 pF XTAL1 CMOS Oscillator 10 k GND N/C +5 V XTAL2 CLOCK 497-8_007 CLOCK* As an alternative to using the PLLs for clock generation, the Bt497A/8A accepts differential clock signals (CLOCK and CLOCK* illustrated in Figure 1-7). ECL logic, operating at +5 V, generates these clock inputs. NOTE: L498A_B The CLOCK and CLOCK* inputs require termination resistors (220 W to GND) located as close to the driving source as possible. A 150 W chip resistor near the Bt497A/8A pins is needed to ensure proper termination. Conexant Preliminary Information/Conexant Proprietary and Confidential 1-17 L498A_B 1.0 Circuit Description 1.6 Clock Generation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-7. Differential Clock Interface Bt497A/8A Bt438 CLOCK CLOCK 220 150 CLOCK* CLOCK* 220 1k VREF 497-8_008 VREF A serial clock, SC*, is generated for the external clocking of the VRAM frame buffer and for loading pixel data. The serial clock frequencies are either one-half or one-fourth of the pixel clock frequency, Fp, depending on the pixel format selected, as defined in Table 1-7. The SC* output is buffered and inverted and then used to drive the LD input and clock the frame buffer. For proper operation, the delay through the buffer must not exceed the limits in the AC specifications. Table 1-7. Serial Clock Frequencies Pixel Format SC Frequency 2:1 Fp/2 4:1 Fp/4 4/2:1 Fp/2 8/2:1 Fp/4 With the assertion of RESET*, SC* is forced high. When RESET* is released, the first falling edge of SC* is released by the next edge of the pixel clock. 1-18 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.7 Frame Buffer Interface 1.7 Frame Buffer Interface Internal latches and multiplexers incorporated in the Bt497A/8A enable the transfer of pixel data from the frame buffer at VRAM data rates. On the rising edge of LD color information, 2 or 4 consecutive pixels latch into the device. Two additional pixel formats are supported, 4/2:1 and 8/2:1, in which 4 or 8 consecutive pixels latch in two load cycles. In each case, the SC* and LD rates are at one-half or one-fourth of the pixel clock rates. The pixel formats are controlled through the Pixel Format Control Register and are illustrated in Figures 1-8 through 1-13. Table 1-8 lists the Bt498A pixel port configured into two ports, A and B. These accommodate double-buffered operation for animation. The port selection is made by decoding the X field of each pixel, as explained in the Color Model sections. Each port is divided into 8 bytes. The LSB represents the LSB of each color, window attribute, or overlay, for a total of 128 inputs. The Bt497A is a 64-bit pixel port option, port A only, packaged in a 160-pin Plastic Quad Flatpack (PQFP). Because of the smaller port size, the only pixel formats supported are the 2:1 and 4/2:1. Internal logic maintains an internal LOAD signal synchronous to the pixel clock, and is guaranteed to follow the LD signal by at least one but not more than three clock cycles. This LOAD signal transfers the registered pixel and overlay data into a second set of registers, which are then internally multiplexed at the pixel clock rate. The LD may be phase shifted in any amount relative to the clock source, pseudo ECL or PLL. As a result, the pixel data is registered on the rising edge of LD independent of the internal or external clock phase. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-19 L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-8. Pixel Port Naming Convention Pixel Port Device Bits B (Not available on Bt497A) PB[63:56] PB[55:48] PB[47:40] PB[39:32] PB[31:24] PB[23:16] PB[15:8] PB[7:0] A PA[63:56] PA[55:48] PA[47:40] PA[39:32] PA[31:24] PA[23:16] PA[15:8] PA[7:0] 1-20 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-8. 2:1 Single-Buffered Pixel Format Pixel Clock LD PA[63:56] x1 x3 x5 x7 x9 x11 PA[55:48] blue1 blue3 blue5 blue7 blue9 blue11 PA[47:40] green1 green3 green5 green7 green9 green11 PA[39:32] red1 red3 red5 red7 red9 red11 PA[31:24] x0 x2 x4 x6 x8 x10 PA[23:16] blue0 blue blue4 blue6 blue8 blue10 PA[15:8] green0 green2 green4 green6 green8 green10 PA[7:0] red0 red2 red4 red6 red8 red10 Pixel Numbers 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 0 1 2 3 4 5 6 7 8 9 497-8_009 Serialized 24-Bit Pixels plus X Bits NOTE(S): This mode is valid for pixel clock Fp 160 MHz. LD frequency = Fp/2 MHz. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-21 L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-9. 2:1 Double-Buffered Pixel Format Pixel Clock PB[63:56] x1 x3 x5 blue1 blue3 blue5 green1 green3 green5 red1 red3 red5 x0 x2 x4 blue0 blue2 blue4 green0 green2 green4 red0 red2 red4 PA[63:56] x1 x3 x5 PA[55:48] blue1 blue3 blue5 PA[47:40] green1 green3 green5 PA[39:32] red1 red3 red5 x0 x2 x4 PA[23:16] blue0 blue2 blue4 PA[15:8] green0 green2 green4 red0 red2 red4 0, 1 2, 3 4, 5 PB[55:48] PB[47:40] PB[39:32] PB[31:24] PB[23:16] PB[15:8] PB[7:0] PA[31:24] PA[7:0] Pixel Numbers Serialized 24-Bit Pixels plus X Bits 0 1 2 3 4 5 497-8_010 LD NOTE(S): This mode is valid for pixel clock Fp 160 MHz. LD frequency = Fp/2 MHz. Not valid for the Bt497A. 1-22 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-10. 4:1 Pixel Format Pixel Clock LD PB[63:56] x3 x7 x11 blue3 blue7 blue11 green3 green7 green11 PB[39:32] red3 red7 red11 PB[31:24] x2 x6 x10 PB[23:16] blue2 blue6 blue10 PB[15:8] green2 green6 green10 red2 red6 red10 x1 x5 x9 PA[55:48] blue1 blue5 blue9 PA[47:40] green1 green5 green9 red1 red5 red9 x0 x4 x8 blue0 blue4 blue8 green0 green4 green8 red0 red4 red8 0, 1, 2, 3 4, 5, 6, 7 8, 9, 10, 11 PB[55:48] PB[47:40] PB[7:0] PA[63:56] PA[39:32] PA[31:24] PA[23:16] PA[15:8] PA[7:0] Pixel Numbers 0 1 2 3 4 5 6 7 497-8_011 Serialized 24-Bit Pixels plus X Bits NOTE(S): This mode is valid for pixel clock Fp 240 MHz. LD frequency = Fp/4 MHz. Not valid for the Bt497A. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-23 L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-11. 4/2:1 Single-Buffered Pixel Format Pixel Clock LD PA[63:56] x3 green3 x7 green7 x11 green11 PA[55:48] blue3 red3 blue7 red7 blue11 red11 x2 green2 x6 green6 x10 green10 PA[39:32] blue2 red2 blue6 red6 blue10 red10 PA[31:24] x1 green1 x5 green5 x9 green9 PA[23:16] blue1 red1 blue5 red5 blue9 red9 PA[15:8] x0 green0 x4 green4 x8 green8 PA[7:0] blue0 red0 blue4 red4 blue8 red8 PA[47:40] Pixel Numbers 0, 1, 2, 3 4, 5, 6, 7 0 1 8, 9, 10, 11 2 3 4 5 6 7 497-8_012 Serialized 24-Bit Pixels plus X Bits NOTE(S): This mode is valid for pixel clock Fp 160 MHz. LD frequency = Fp/2 MHz. 1-24 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-12. 4/2:1 Double-Buffered Pixel Format Pixel Clock LD PORT B PB[63:56] x3 green3 x7 green7 x11 green11 PB[55:48] blue3 red3 blue7 red7 blue11 red11 x2 green2 x6 green6 x10 green10 blue2 red2 blue6 red6 blue10 red10 x1 green1 x5 green5 x9 green9 blue1 red1 blue5 red5 blue9 red9 x0 green0 x4 green4 x8 green8 blue0 red0 blue4 red4 blue8 red8 x3 green3 x7 green7 x11 green11 blue3 red3 blue7 red7 blue11 red11 PA[47:40] x2 green2 x6 green6 x10 green10 PA[39:32] blue2 red2 blue6 red6 blue10 red10 PA[31:24] x1 green1 x5 green5 x9 green9 PA[23:16] blue1 red1 blue5 red5 blue9 red9 PA[15:8] x0 green0 x4 green4 x8 green8 PA[7:0] blue0 red0 blue4 red4 blue8 red8 PB[47:40] PB[39:32] PB[31:24] P B[23:16] PB[15:8] PB[7:0] PORT A PA[63:56] PA[55:48] Port A Pixels Serialized 24-Bit Pixels plus X Bits 0, 1, 2, 3 4, 5, 6, 7 0 1 8, 9, 10, 11 2 3 4 5 6 7 497-8_013 Port B Pixels NOTE(S): This mode is valid for pixel clock Fp 160 MHz. LD frequency = Fp/2 MHz. Not valid for the Bt497A. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-25 L498A_B 1.0 Circuit Description 1.7 Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-13. 8/2:1 Pixel Format Pixel Clock LD PORT B PB[63:56] x7 green7 x15 green15 x23 green23 PB[55:48] blue7 red7 blue15 red15 blue23 red23 PB[47:40] x6 green6 x14 green14 x22 green22 PB[39:22] blue6 red6 blue14 red14 blue22 red22 x5 green5 x13 green13 x21 green21 PB[23:16] blue5 red5 blue13 red13 blue21 red21 PB[15:8] x4 green4 x12 green12 x20 green20 blue4 red4 blue12 red12 blue20 red20 PA[63:56] x3 green3 x11 green11 x19 green19 PA[55:48] blue3 red3 blue11 red11 blue19 red19 PA[47:40] x2 green2 x10 green10 x18 green18 PA[39:32] blue2 red2 blue10 red10 blue18 red18 PA[31:24] x1 green1 x9 green9 x17 green17 PA[23:16] blue1 red1 blue9 red9 blue17 red17 PA[15:8] x0 green0 x8 green8 x16 green16 PA[7:0] blue0 red0 blue8 red8 blue16 red16 PB[31:24] PB[7:0] PORT A Serialized 24-Bit Pixels plus X Bits 0, 1, 2, 3, 4, 5, 6, 7 8, 9, 10, 11, 12, 13, 14, 15 0 1 2 3 4 5 16, 17, 18, 19, 20, 21, 22, 23 6 7 8 9 10 11 12 13 14 497-8_014 Pixel Numbers NOTE(S): This mode is valid for pixel clock Fp 240 MHz. LD frequency = Fp/4 MHz. Not valid for the Bt497A. 1-26 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.8 Color Model Selection 1.8 Color Model Selection Figure 1-14 illustrates the Bt497A/8A specialized logic that transforms pixel data into color information. The diagrams describing the various pixel formats include a data field named X. Contents of this field are the dynamic primary input to the Color Model Control (CMC) logic, described later. The CMC outputs, labeled in Figure 1-14 as WLU (for "Window Look-Up"), serve to select the pixel source, e.g., port A or B, and to associate the pixel with a particular color model. The term Color Model refers to the final category of mux-selection and resultant color state that drives the RED, GRN and BLU outputs in Figure 1-14. The WLU[6:0] outputs from the CMC block determine a Color Model. There is a correspondence between the WLU bit values and specific CMC[15:0] bits, described later. Table 1-9 describes the various Color Model effects of different WLU values in Figure 1-14. The X field is a component of every pixel, and its content may differ in contiguous pixels. Therefore, port and color model selection is performed for each individual pixel. The pixel formats are divided into two broad categories: single-buffered format and double-buffered format. The Bt497A can only support the 2:1 and 4/2:1 formats running single-buffered. It has no Port B available. The Bt498A supports all formats, including the double-buffered modes. In the WIDSEP8 mode, described later, the X field from Port A and the X field from Port B are used. In 4:1 and 8/2:1 the X field from each pixel is used. Bit WLU[6] is don't care for 4:1 and 8/2:1 formats. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-27 L498A_B 1.0 Circuit Description 1.8 Color Model Selection 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-14. Color Model Selection Mechanism XA[7:0] Color Model Control XB[7:0] WLU[6] XO[7:0] WLU[4:3] WLU[5] Port A[63:0] X[7:0] Pixel R[7:0] Formatting G[7:0] Logic B[7:0] X[7:0] Pixel Formatting R[7:0] G[7:0] Logic B[7:0] WLU[2] R[7:0] G[7:0] B[7:0] Color Model Selection R[7:0] G[7:0] B[7:0] Port B[63:0] WLU[1:0] 1K x 8 RAMLUT 1K x 8 RAMLUT R[7:0] G[7:0] B[7:0] 1K x 8 RAMLUT Palette Pseudocolor Palette Direct Color Bypassed TrueColor RED GRN Bypassed Gray Scale BLU 3 x 8 RAM Cursor LUT 3 x 8 RAM Cursor LUT CURSOR DATA[1,0] 497-8_015 3 x 8 RAM Cursor LUT CURSOR SELECT 1-28 Cursor Color Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.8 Color Model Selection 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-9. Window Look-Up Attributes WLU bits L498A_B Description Value WLU[6] Double Buffering 0 = Buffer A 1 = Buffer B WLU[5] Color Depth 0 = 8 Bits/pixel 1 = 24 Bits/pixel WLU[4:3] Pseudocolor Source 00 = X[7:0] 01 = R[7:0] 10 = G[7:0] 11 = B[7:0] WLU[2] Color Lookup 0 = Bypass 1 = Palette WLU[1:0] Palette Table Selection 00 = Table 0 01 = Table 1 10 = Table 2 11 = Table 3 Conexant Preliminary Information/Conexant Proprietary and Confidential 1-29 L498A_B 1.0 Circuit Description 1.9 Color Model Control 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.9 Color Model Control The Color Model Control (CMC) block introduced in Figure 1-14 is now fully described. The dynamic input is the X field which is output from the pixel unpacking logic. X is generated from both port A and port B, if the pixel format is 2:1 or 4/2:1. If the format is 4:1 or 8/2:1, then X is associated with the single extended pixel port. For these formats, there is only one buffer with a pixel value and corresponding X field. The X field is dynamic in that it can change with any new pixel position. Static, or seldom changing inputs to CMC come from the User Control Register, the Window Address Control Mask Register, the Transparent Color Mask Register, the Transparent Color Key Register, and the Transfer Control Logic. In addition, the Window Look-Up Tables (WLUTs, described below) require standard MPU access. CMC outputs are WLU[6:0], described in the previous section, and XO[7:0]. XO is the final X output bus which expresses into the Color Model Selection logic as a potential pixel source. There are two main processes in the CMC: WLUT indexing and Overlay enable. The remainder of this section describes WLUT indexing and the composition of XO. A later section describes Overlay/Underlay operation. WLUT indexing refers to the process of generating address inputs to the two active WLUTs in the CMC: * The Primary WLUT (PWLUT), which has 64 entries, with each entry 7 bits wide. * The Overlay WLUT (OWLUT), which has 4 entries, each being 11 bits wide. Both the PWLUT and the OWLUT are high-speed Random Access Memories (RAMs) that are able to switch their entry outputs at pixel rate. These two WLUTS are illustrated in Figure 1-15, along with the other main CMC functions. Each WLUT has a shadow WLUT associated with it that is the same size as its active reference RAM. The shadow WLUTs provide a smooth, synchronous updating mechanism for changing the contents of the active WLUTs. When the UPDATE signal is asserted, the full contents of the shadow PWLUT load directly into the active PWLUT. Simultaneously, the active OWLUT is loaded with the full contents of the shadow OWLUT. The conditions that cause UPDATE assertion are described later. Only the active PWLUT and OWLUT are involved in Color Model Control. All WLUT references in the remainder of this section are understood to indicate the Active PWLUT and OWLUT. Refer to Figure 1-15. The WM control refers to Window Mode, a 2-bit control set by the User Control Register. The three Window Modes are: C = Combined, S4 = Separate_4, and S8 = Separate_8. These terms refer to the sources of Overlay Comparison versus that for PWLUT indexing. The state of WM directly affects the index sources for the PWLUT and the OWLUT, and mapping for the XO output. The XA and XB inputs come directly from the Pixel Unpacking logic. Review Table 1-10 to clarify the dependencies of these primary inputs on pixel formats. It shows that the Separate_8 window mode is NOT supported for 4:1 and 8/2:1 pixel formats, since there is no concept of XB. The Combined and Separate_4 modes ARE supported for all pixel formats. MPU access connections have been omitted in Figure 1-15 for clarity. 1-30 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.9 Color Model Control 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-15. Color Model Control XA[7:0] UPDATE XA[5:0] 5:4 3:0 XB[5:0] S4 6 PMASK 00 XA[7:4] C 6 PCM[15:12, 8, 5:4] PWLUT 64 x 7 S8 7 Overlay Mux OCM[3:0] 4 CMC[15] CMC[14] 0 CMC[13:12] XA[7:6] C XA[7:6] S4 XB[7:6] 2 S8 OMASK 0 2 OWLUT 4 x 11 5 6:5 4:0 1 OCM[13:12, 8, 5:4] CMC[8] CMC[5:4] WLU[6] WLU[5] WLU[4:3] WLU[2] WLU[1:0] 2 OCM[11:10] 8 XA[7:0] XA[3:0] XA[7:0] Overlay / Underlay Logic DO_OVLY C 7:4 3:0 S4 8 XO[7:0] S8 XB[7:0] WM OV_EN 497-8_016 2 In Figure 1-15, the PMASK and OMASK blocks refer to the respective fields from the Window Address Mask Register. These blocks allow restriction of the selected entries within the two WLUTs. Program the fields with all 1s to allow maximum WLUT entry selection. The masking operation is described further in the respective Internal Register section. After masking, the PWLUT and OWLUT are addressed, and the selected entries generate corresponding output states. In Figure 1-15, these outputs are PCM (for Primary Color Model) and OCM (for Overlay Color Model) respectively. At the Overlay Mux, the DO_OVLY signal selects between all of PCM or a subset of OCM to generate the final CMC state. The bit indexes for these busses are shown as greater than the widths of either WLUT. That is because the CMC, PCM, and OCM busses are referenced with the linked bit-assignments given in the WLUT 16 bit MPU programmed values. These assignments are shown in Table 1-11. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-31 L498A_B 1.0 Circuit Description 1.9 Color Model Control 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Mapping between the MPU Color Model WLUT bits and the actual bit positions within the OWLUT and PWLUT RAMS is also given in Table 1-11. The MPU interface to the PWLUT and OWLUT performs the translation between the expanded bit positions of Table 1-11 and the actual compressed bit positions in the two WLUTs. NOTE: The first Table 1-11 function, Double Buffering, is "don't-care" if the Pixel Format is either 4:1 or 8/2:1. Table 1-10. Pixel Format Dependencies Pixel Format XA Source XB Source Separate_8 mode 2:1 and 4/2:1 64-pin port_A 64-pin port_B Supported 4:1 and 8/2:1 128-pin port_A AND port_B N/A Supported Table 1-11. Color Model Control WLUT Linked Bit Definitions (1 of 2) Bit(s) Function/Assignment OCM State OWLUT Mapping PCM State PWLUT Mapping 15 Double Buffering 0 = Buffer A 1 = Buffer B <force 0> N/A PCM[15] PWLUT[6] 14 Color Depth 0 = 8 Bits/pixel (Pseudo-color) 1 = 24 Bits/pixel (True-color) <force 0> N/A PCM[14] PWLUT[5] 13, 12 Pseudocolor Source 00 = X0[7:0] 01 = R[7:0] 10 = G[7:0] 11 = B[7:0] OCM[13:12] OWLUT[10:9] PCM[13,12] PWLUT[4:3] 11, 10 Overlay Type 00 = No Overlay 01 = Transparent Overlay 10 = Opaque Overlay 11 = Reserved OCM[11,10] OWLUT[8:7] N/A N/A 9 Reserved N/A N/A N/A N/A 8 Color Lookup 0 = Bypass the Palette 1 = Index thru Palette OCM[8] OWLUT[6] PCM[8] PWLUT[2] 7, 6 Reserved N/A N/A N/A N/A 1-32 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.9 Color Model Control 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-11. Color Model Control WLUT Linked Bit Definitions (2 of 2) Bit(s) Function/Assignment OCM State OWLUT Mapping PCM State PWLUT Mapping 5, 4 Palette Table 00 = Table 0 01 = Table 1 10 = Table 2 11 = Table 3 OCM[5,4] OWLUT[5:4] PCM[5,4] PWLUT[1:0] 3-0 Palette Section, Separate_4 $0 = Section 0 $1 = Section 1 $2 = Section 2 : $F = Section 15 OCM[3:0] OWLUT[3:0] N/A N/A L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-33 L498A_B 1.0 Circuit Description 1.10 Color Lookup Operations 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.10 Color Lookup Operations Color Lookup refers to the final selection of a 24-bit color value that is the input to the Bt497A/8A DACs. This is illustrated on the right side of Figure 1-14. Color Lookup includes the Palette RAM, the Cursor LUT, and the Bypass Mux. The Palette refers to the 3 1Kx8 RAMs that store color values indexed (addressed) by the pixel value delivered after Color Model selection. The Cursor information always has highest priority. Whenever CURSOR_SELECT is asserted, the Color Lookup will be one of the three Cursor LUT colors, as determined by the CURSOR_DATA value. The rest of this section assumes that the Cursor is NOT active. If the CMC Lookup function = BYPASS, then the Palette's 24-bit input pixel data goes directly to the DACs. Pipeline stages match the delays of the Palette. A Color Channel refers to one of the Palette's 1Kx8 RAMs, or that same RAM's potential Bypassing pixel-value. With its three color channels, the Palette is used to generate true or pseudocolor information. The CMC Color Depth function controls this attribute. In true color each channel is addressed independently, while in pseudocolor the selected pixel input is replicated to the three channels. If both Pseudocolor and Bypass are asserted, the resulting display is Gray Scale, with identical inputs to each of the three DACs. The CMC Palette Table function serves to divide down the Palettes large 1K color space. In general, a given Color Model state corresponds to the specific attributes of different windows exhibited on the system display screen. The usual pixel space for such windows is 256, which corresponds to the 8-bit width of X, R, G, or B pixel components. Associated with such a pixel range is a Color Palette table of 256 locations. For greater color flexibility, the Bt497A/8A provides four distinct Palette tables selected by CMC. The last function in Table 1-11 is labeled Palette Section for the Separate_4 mode. From Figure 1-15, it is seen that these OCM[3:0] bits are input to the XO mux as an upper nibble. Thus, when the Color Model is "Pseudo-color from XO," and the WM is Separate_4, the Palette Section bits divides and selects the chosen Palette Table among sixteen 16-entry sections. 1-34 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.11 Overlay/Underlay Operation 1.11 Overlay/Underlay Operation As indicated previously, data in the incoming X field is interpreted as either a WLUT index or as an overlay select. Thus, pixel overlays are accommodated without incurring the expense of additional planes in the frame buffer memory and additional LUTs in the Bt497A/8A. This is accomplished by using the 1K x 8 x 3 Palette to contain overlay colors and by circuitry to regulate the selection of overlay or underlay data for display. This function appears in the color model control diagram as the Overlay/Underlay Logic block of Figure 1-15. The details are illustrated in Figure 1-16. An active Overlay causes the CMC output to be the OCM state. Otherwise the color model is Underlay, and CMC drives the PCM state. These two states are detailed in Table 1-11. In this framework, there are two Overlay types, which are selected from specific OCM bits. Control of overlay types is summarized in Table 1-12. Assuming the Overlay Enable bit is asserted, SELECT_OVERLAY is asserted whenever the OPAQUE overlay input is active (The SELECT_OVERLAY signal in Figure 1-16 is equivalent to DO_OVLY in Figure 1-15.) The remainder of this section assumes Overlay Enable is asserted and TRANSPARENT overlay is active. (Transparent and Opaque selections cannot be active simultaneously.) The principle of transparent overlay/underlay operation is illustrated in Table 1-12, and works as follows. The contents of two registers, the Transparent Mask Control Register and the Transparent Color Key Register, define a transparent overlay color key value. This color key value is compared to the value contained in XA[7:0]. If the two values are equal, the overlay is said to be transparent and the underlay (Primary WLUT) color model is driven; i.e., the overlay mux passes PCM state to WLU[6:0]. Therefore, the color model and the color source are chosen by the contents of the PWLUT. If the two values are not equal, the overlay color model is active; the overlay mux passes the OCM state to WLU[6:0]. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-35 L498A_B 1.0 Circuit Description 1.11 Overlay/Underlay Operation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-16. Overlay/Underlay Logic OCM[11,10] = 01 OCM[11,10] = 10 Overlay Type = Overlay Type = TRANSPARENT OPAQUE 1 Overlay Enable Bit 8 8 Transparent Color Key Register a a=b 8 Transparent Mask Control Register 8 b SELECT_OVERLAY 497-8_017 XA[7:0] Table 1-12. Overlay Operation (1) 1-36 Overlay Enable OCM[11,10] Overlay Type Transparent Color SELECT_OVERLAY 0 x x x Under 1 10 Opaque x Over 1 00 None x Under 1 01 Transparent Color key AND Mask = XA AND Mask Under(1) 1 01 Transparent Color key AND Mask | XA AND Mask Over For the special case where all of the Transparent Mask Control Register bits [7:0] are set to 0, the underlay is used for color model control. Overlay Enable Control Bit The User Control Register contains the Overlay Enable Bit. When the overlay control is disabled, (set to a logical 0), the underlay data (PCM) is used for color model control (i.e., WLU[6:0]). When the overlay control is enabled, (set to a logical 1), the selection of overlays is controlled by the rest of the logic in Figure 1-16. Transparent Overlay Mask Register This 8-bit register operates on the contents of the Transparent Color Key Register and the XA data to define the extent (in the bit dimension) of the color key value. Transparent Mask Control Register bits set to logical 1 allow the corresponding bits of the Transparent Color Key Register and the XA field to participate in the transparent color comparison. Transparent Mask Control Register bits set to logical 0 preclude the corresponding bits of the Transparent Color Key Register and the XA field from comparison. Register initialization is not required. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Transparent Overlay Color Key Register Overlay Type Selection Bits L498A_B 1.11 Overlay/Underlay Operation This 8-bit register defines the transparent color key value, subject to the contents of the Transparent Mask Control Register. Register initialization is not required. These two dynamic bits are input from the OWLUT location that is currently active. OCM[10], when asserted, indicates Transparent overlay type. OCM[11], when asserted, indicates Opaque overlay type. Conexant Preliminary Information/Conexant Proprietary and Confidential 1-37 L498A_B 1.0 Circuit Description 1.12 Window Lookup Transfer Control 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.12 Window Lookup Transfer Control In the Color Model Control section, the two WLUT Shadow RAMS were introduced. These RAMs are loaded at any arbitrary time by the MPU with new window attribute information intended to become active for the system display. NOTE: The 2 Active WLUTs may be accessed by the MPU and should be initialized during the startup procedure. To avoid visual artifacts on the display screen, the active WLUTs should not be accessed during active video, but should instead get updated through the two respective Shadow WLUTs. This section describes the details of how and when the Active RAM contents get updated with the contents of the respective Shadow RAMs, a process referred to as window transfer. The eventual updating, or transfer of RAM data from Shadow to Active WLUTs is handled by the Window Transfer Control (WTC) Register. The general operation of this register is given here, see the Internal Register section for specific bit assignments and descriptions. The Bt497A/8A has several features to facilitate operation in a multiple RAMDAC configuration with other Bt497A/8As. One of those aspects is the synchronizing of window transfers by use of the DRAWING* pin, as illustrated in Figure 1-17. The intention is to provide a hold off of final window transfer for all Bt497A/8As, even though some local MPUs have requested it, until ALL the Bt497A/8As have signalled they are ready for the transfer. Accordingly, each Bt497A/8A has an open-drain DRAWING* pin which operates in a bidirectional fashion as follows. Assume the user is ready for a major WLUT change, such as switching between Double Buffers. First, the user programs the WTC Drawing Data bit to a 1, meaning that this local Bt497A/8A is pursuing window changes. In Figure 1-17, this activates the pulldown, which pulls the common DRAWING* line low. The user updates the local Shadow PLWUT (and OWLUT) as required. Finally the (local) user sets Drawing Data to 0, and sets the WTC Transfer Command to 1. The local Bt497A/8A is then in a transfer pending state. However, the transfer cannot be fully enabled until all chips on the network also become pending. When that happens, no local node pulldown is active, and the external pullup brings the DRAWING* line high. The actual transfer occurs when Valid Event goes high, which is always at an appropriate VSYNC-active edge. (Valid Event symbolizes the more detailed effects of the Transfer Event bit and FIELD signal edges in WTC.) The Latch block in Figure 1-17 indicates that the DRAWING* pulldown will be prevented from changing its state if VBLANK happens to be active. The target color model function for the above synchronizing mechanism is in fact Double Buffer changes. As Double Buffering is only supported in the Bt498A, the DRAWING* feature is only supported for that product. DRAWING* pin is not found in the Bt497A part. Users of Bt497A should set the Drawing Data bit to a constant 0, to allow normal window transfers. The same applies to users of single-chip Bt498A systems. In both cases, a weak internal pullup at the DRAWING* pad-buffer ensures that the Drawing Status bit is low, and the DRAWING* pin (for Bt498A) can be left unconnected. 1-38 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.12 Window Lookup Transfer Control 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-17. Multi-Chip Window Transfer Control +5V DRAWING* Pin (to other Bt497A/8As) External Pullup UPDATE VBLANK Latch Drawing Status Valid Event Transfer Command Window Transfer Control Register L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_018 Drawing Data 1-39 L498A_B 1.0 Circuit Description 1.13 On-chip Cursor Operation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.13 On-chip Cursor Operation The Bt497A/8A has an on-chip, user-definable, three-color, 64 x 64 pixel cursor. A two-plane 64 x 64 cursor RAM, accessed by the MPU at any time, provides the pattern for the cursor. Each plane provides one bit of cursor information every pixel clock cycle. These two bits are used to select a cursor color from a 3 x 24 LUT, as defined in Table 1-13. Each plane can also be independently enabled or disabled using the Cursor Control Register. Writing a 1 to the appropriate register bits immediately blocks the cursor from appearing, regardless of its position. This action is recommended before doing any updates to either the cursor RAM or the cursor color LUT, to avoid visual artifacts. Then, re-enable the appropriate planes to view the completed changes. The assertion of RESET* enables both planes. The cursor RAM is accessed through the MPU in a planar format. Each byte in the MPU write cycle constitutes 8 RAM bits in which the Most Significant Bit (MSB) becomes the leftmost location of each load group. The most significant byte corresponds to the leftmost position of each address. The Plane0 addresses are $00 to $7F and Plane1 addresses are $80 to $FF within the cursor configuration address space. See Figure 1-18 for an exact mapping between the MPU addresses and the corresponding bit map as it is observed on the screen. Table 1-13. Cursor Color LUT 1-40 Plane1 Plane0 Color Displayed Cursor Address 0 0 Transparent -- 0 1 Cursor Color 1 $0101 1 0 Cursor Color 2 $0102 1 1 Cursor Color 3 $0103 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.14 Cursor Color LUT 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-18. Cursor RAM Address Map Address $80 Address $82 Address $81 Address $00 Address $02 Address $01 Plane 1 Address $FF Address $7F Plane 0 Byte 2 Byte 1 Byte 0 497-8_019 Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 1.14 Cursor Color LUT Cursor color LUT follows the same load sequence, through the MPU, as the color palette LUT (red, green, blue, and a dummy value) and can be accessed at any time. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-41 L498A_B 1.0 Circuit Description 1.15 Cursor Positioning 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.15 Cursor Positioning The Cursor Position Register determines the cursor position. This 32-bit field contains the sign and magnitude of the X and Y start position of the 64 X 64 cursor's top left corner, as illustrated in Figure 1-19. The Bt497A/8A contains an internal X counter that increments by pixel going right, from -64 to +4031, and a Y counter that increments by line, going down on the screen from -64 to +4031. When the values of the X and Y counter match the values in the Cursor Position Register the contents of the cursor RAM are displayed on the screen. In noninterlaced mode, the latest position is loaded in from the register, and the display counters are reset to zero (the top left corner of the screen) at the beginning of each vertical sync. In interlaced mode, the position update does not take effect until the next VSYNC* before an even field. Cursor position (0,0) constitutes the top left corner of the active video display. This enables the users to position the cursor off of the top (Y = -64) and the left side of the screen (X = -64). See Figure 1-20. The assertion of RESET* resets the cursor RAM X and Y display counters, but does not reset the position register. NOTE: All other cursor registers exhibit immediate effects when they are written with new values by the MPU. When the Cursor Position Register is written, its new value can be read back immediately. However, the cursor does not move on the screen until the appropriate VSYNC* occurrence. Figure 1-19. Cursor Position Register Reserved 27 16 15 Y Position Sign for Y 1-42 11 0 X Position Sign for X Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_020 31 Reserved L498A_B L498A_B 1.0 Circuit Description 1.15 Cursor Positioning 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-20. Cursor Positioning VBLANK* HBLANK* X Y Display Area 497-8_021 64 x 64 Cursor L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-43 L498A_B 1.0 Circuit Description 1.16 Cursor Interlace Operation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.16 Cursor Interlace Operation When the Bt497A/8A operates in the interlaced mode, the cursor is displayed in an odd and even field format. If the Y value in the Cursor Position Register is an even number, then the first row (Row 0) and all even rows of cursor RAM are displayed during the even field. The odd rows, starting with Row 1, are displayed in the odd field. If the Y position value is an odd value, the display sequence is reversed; even rows during odd fields and odd rows during even fields. 1.17 Timing Generator The Bt497A/8A has an on-chip timing generator, operating from the serial clock, to provide video display and memory timing reference signals for interlaced and noninterlaced video formats. Values in the Timing Generator Control Register and in the various timing point registers set the timing boundaries. To avoid lockup or timing glitches it is required that the pixel clock be freely running whenever changes are made to any of the Timing Generator Registers. 1-44 System Reset When asserted, the system reset signal (RESET*) has the following effects. A registered function named Video Enable is forced to the video disabled state by the assertion of RESET*. This condition persists after the negation of RESET* and until it is overwritten via the MPU port. Video Enable, when in the disabled state, asserts composite blanking within the RAMDAC so that the video monitor remains black while the timing generator is being programmed. When asserted, RESET* forces the Timing Generator Horizontal and Vertical Counters to a zero value. Timing Generator Enable is forced to the disabled state by the assertion of RESET*. This condition persists after the negation of RESET* and until it is overwritten via the MPU port. The purpose is to hold the timing generator in a known state while it is being programmed. No other Timing Generator functions or waveforms are affected when Video Enable is in the disabled state. When asserted, RESET* causes the timing generator to be in the slave mode. In this case, the FIELD signal is placed in the high-impedance mode. Timing Generator Test Features To enable the user to observe timing generator operation, several internal timing signals can be output onto the MPU bus by accessing the Timing Generator Test Register ($6011). This is accomplished by loading the register value in the address pointer and setting the MPU port into the read mode. When the CE* is enabled (low) the signals listed in Table 1-14 is output onto the MPU port. When the CE* is disabled (high) the MPU port returns to normal operation. Three additional CE* cycles are required to increment to the next address. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-14. Internal Timing Generator Signals MPU Output Internal Signal Description D[7] HSYNC* Internal Horizontal Sync D[6] SERRATION* Internal Serration Pulses D[5] EqualizE Internal Equalizing Pulses D[4] CBLANK Internal Composite Blank D[3] CSYNC* Internal Composite Sync D[2] VSYNC* Internal Vertical Sync D[1] VBLANK* Internal Vertical Blank D[0] HBLANK* Internal Horizontal Blank Timing Generator Display Formats Programming the appropriate values into the Timing Generator Control Register controls the timing generator. Both interlaced and noninterlaced modes of operation are supported. All horizontal register values are units of the serial clock rate. All vertical register values are units of horizontal lines. The origin of the timing coordinates is the serial clock period immediately following the start of vertical sync. This means that line 0 is the first line of vertical sync, and horizontal unit 0 is the first serial clock period immediately following the start of horizontal sync. The values to load into the registers are one less than the desired timing point. Neither the horizontal nor the vertical registers can be programmed to have a value of zero. When operated in pixel formats of 4/2:1 and 8/2:1, the horizontal active interval, represented by the Horizontal Blank Negation Point and Horizontal Blank Assertion Point registers, should be programmed with an even value. The Internal Registers section describes the programming of these registers. Video display timing information goes to the monitor by inserting the blank and sync information onto the DAC outputs, via the Timing Generator Control Register. The sync information is also available on two digital pins: CSYNC* and VSYNC*. In noninterlaced mode the CSYNC* contains horizontal and vertical, optionally serrated sync information. In interlaced mode the horizontal Equalization information is also included. VSYNC* always expresses the Vertical Sync transitions, with Vsync active driven to a low level. For separate sync monitors, CSYNC* can be reduced to HSYNC* by setting appropriate bit(s) in the Timing Generator Control Register. Output Signals Bt497A/498A provides the following timing generator outputs: SC*, SCEN*, STSCAN, FIELD, VSYNC*, and CSYNC*. Assuming the Timing Generator is enabled, all these signals preserve their programmed waveforms even if the screen is set to constant blank by other Bt497A/498A registers. FIELD Output The FIELD signal, when in master mode, transitions with the leading edge of the internal VSYNC*. Additionally, the level outputs the current field when in interlaced mode (logical 0 = even field, logical 1 = odd field). In noninterlaced mode, transitional edges of this signal still occur near the leading edge of every VSYNC*; however, the level of the FIELD signal has no meaning. Externally, the signal can be used to differentiate between left and right views of a stereo display. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-45 L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC STSCAN Output The STSCAN output is an internally generated signal that can be used by the memory controller to determine the proper row transfer address timing for the VRAM frame buffer serial port. The logic sets the STSCAN signal at the rising edge of SCEN* if the next line is visible and reset the STSCAN at the falling edge of SCEN*. SCEN* Output The SCEN* output enables the clocking of serial data from the VRAMs. The assertion of SCEN* is controlled by programming the timing generator registers Vertical Blank Negation Point (VBNP), Vertical Blank Assertion Point (VBAP), Horizontal Serial Clock Enable Assertion Point (HSCENAP), and Horizontal Serial Clock Enable Negation Point (HSCENNP). VSYNC* and CSYNC* Outputs These two outputs are distinguished from the others in that A) they are pipeline delayed to be consistent with the Analog DAC outputs; and B) they are synchronized by the pixel clock. (The above outputs belong to the serial clock domain.) The waveforms of VSYNC* and CSYNC* were described in the previous section. Both VSYNC* and CSYNC* can be disabled (forced to high level) by setting bits in the Timing Generator Control Register. The active state may be programmed via sync polarity bit in DAC control register. Noninterlaced Timing Figure 1-21 illustrates the noninterlaced timing points. Figures 1-22 and 1-23 illustrate timing diagrams. Register values represent the SC* period or line before the event occurrence and should be programmed to a value one less than the desired time point. An example of a 1280 x 1024 display is given in the Applications Information section. Timing points are defined in two groupings: horizontal and vertical. Figure 1-21. Noninterlaced Format Timing Boundaries HSNP HBNP HSERNP HBAP HSAP VSNP VBNP Active Display VBAP 497-8_022 VSAP 1-46 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Horizontal Timing Generation For generating the horizontal and serrated sync signals, the Horizontal Sync Assertion Point (HSAP), Horizontal Sync Negation Point (HSNP), and Horizontal Serration Negation Point (HSERNP) registers are programmed with the desired durations in SC* clock units. All parameters should be programmed as one less than the desired duration. The operation is described as follows: The Timing Generator Horizontal Counter begins at a value of zero, with the HSYNC* and SERRATION* waveforms active (i.e., low). When the counter reaches the HSNP value, HSYNC* is deasserted on the next serial clock. The Timing Generator Horizontal Counter continues counting up until the programmed HSERNP value is reached, at which point the SERRATION* waveform is deasserted on the next serial clock. The Timing Generator Horizontal Counter continues until the HSAP value is reached, after which the Timing Generator Horizontal Counter is restarted at zero on the next serial clock. Timing diagrams for the generation of composite sync are illustrated in Figure 1-22. Figure 1-23 illustrates the relative register values related to active screen area. The generation of the horizontal blanking signal is relatively straightforward; HBLANK* is asserted on the next serial clock after the Timing Generator Horizontal Counter reaches the value programmed in the Horizontal Blank Assertion Point Register (HBAP). HBLANK* is then deasserted on the next serial clock after the Timing Generator Horizontal Counter reaches the value programmed in the Horizontal Blank Negation Point Register (HBNP). The horizontal timing register values should satisfy the following relationships: 0 < HSNP < HSERNP < HSAP 0 < HSNP < HBNP < HBAP < HSAP HSNP HBNP HBAP HSAP Endpoint Hsync and start of Horizontal Back Porch. Endpoint HBLANK* and start of active video. Endpoint active video and start of HBLANK*. Endpoint Horizontal Front Porch and start of Hsync. HSAP +1 represents the total number of serial clock periods in a line. HSCENNPThe last serial clock period that SCEN* will be active. HSCENAPSCEN* is active on the next serial clock period. HSCENAP should be less than HBNP by exactly the number of serial clocks that it takes for pixel data to be clocked in at Bt497A/8A input. HBNP-HSCENAP should always equal HBAP-HSCENNP. HSERNP The last serial clock period of horizontal sync during the vertical sync interval. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-47 L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-22. Horizontal Timing and Composite Sync Generation-Noninterlaced Format HSYNC* SERRATION* VSYNC* 497-8_023 CSYNC* HSERNP HSAP HSNP Figure 1-23. Noninterlaced Horizontal Timing IOG Active Video HBNP HBAP HSNP HSAP 497-8_024 CSYNC* Vertical Timing Generation 1-48 The VSYNC* vertical timing signal is generated using the values contained in the Vertical Sync Negation Point (VSNP) and Vertical Sync Assertion Point (VSAP) registers. The VBLANK* vertical timing signal is generated using the values contained in the Vertical Blank Assertion Point (VBAP) and Vertical Blank Negation Point (VBNP) registers. In noninterlaced mode, all vertical timing register intervals are specified in units of horizontal lines (i.e., the load period x HSAP). The vertical timing counter is incremented at each horizontal sync assertion time; subsequently, the only time that any vertical timing signals can transition is at HSYNC* assertion. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC The vertical timing registers should be programmed to satisfy the following relationship: 0 < VSNP < VBNP < VBAP < VSAP The composite blank signal is derived by logically OR'ing internal HBLANK* with VBLANK*. VSNP VBNP VBAP VSAP Composite Sync Endpoint VSYNC and start of Vertical Back Porch. VSNP +1 represents the number of lines during the vertical sync period. Endpoint of VBLANK* and start of active video. The register values represent the number of blanked lines above the active video display plus the lines of Vertical Sync -1. Video is blanked starting on the next line. Endpoint VBLANK* and start of Vsync. VSAP +1 represents the total number of lines in the frame. The Timing Generator Vertical Counter is reset to zero after Vertical Sync is asserted. The composite sync signal combines the HSYNC with the serration pulses during the vertical sync interval onto a discrete output. The components of the CSYNC* output can be enabled or disabled using the Timing Generator Control Register, as shown in Table 1-15. NOTE: The characteristics of CSYNC* as defined by Table 1-15 are also exhibited in the analog IOG output SYNC component timing. Table 1-15. CSYNC* Output: HSYNC* and VSYNC* Control Timing Control Register CSYNC* Output HSYNC* (Bit 2) VSYNC* (Bit 3) Enabled Enabled Normal operation Enabled Disabled CSYNC* looks like HSYNC* (no serrations) Disabled Enabled CSYNC* looks like VSYNC* (no serrations) Disabled Disabled CSYNC* inactive (high level) NOTE(S): Non interlaced mode only. Interlaced Timing L498A_B Due to the nature of the composite sync and video signals during the equalization and vertical sync intervals, interlace mode timing events are based on half-line intervals. Equalization refers to the process whereby special pulses, different from HSYNC timings, appear on CSYNC* during a significant portion of the vertical blank interval. Equalizing refers to these special pulses, or their duration. During the equalization interval, CSYNC* expresses equalizing pulses every half-line. Outside of equalization however, CSYNC* expresses HSYNC pulses every other half-line. To generate half-lines, the timing generator clocks the horizontal and vertical counters twice per scan line. The first starts the external horizontal sync interval. The second occurs at the half-way point of the scan line and is used mainly to trigger the consecutive serration or equalizing pulses during the vertical sync. Conexant Preliminary Information/Conexant Proprietary and Confidential 1-49 L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC The Timing Registers are described in this section and in the Internal Register section. The register values represent the SC* period or half-line before the event occurrence and should be programmed to a value one less than the desired time point. Since the counters are clocked twice per scan line, values in the registers are half of the value programmed for the noninterlaced mode. Examples of the timing values for NTSC and PAL are included in the Application Information section. The timing points are defined into two groupings, Horizontal and Vertical. Horizontal Timing Generation The relationships between the programmed register values and the waveforms are illustrated in Figures 1-24 and 1-25. One additional horizontal time point is required in interlaced mode. EQNP Equalizing Negation Point (EQNP) is the value programmed in the control register that represents the equalizing pulse width (minus one SC*) and is normally programmed to half of the HSYNC* width. The equalizing pulses can only occur during the pre- and post-Equalization intervals illustrated in Figure 1-26. The start of the horizontal timing is determined by the field to be displayed. If the field is even, it starts on an even half-line; if it is odd, it starts on an odd half-line as illustrated in Figure 1-26. The FIELD pin reflects the state of the field, which changes at the onset of Vertical Sync. During an Even Field, FIELD is low; during an odd field, FIELD is high. The SCEN* and STSCAN signals extend over half-line boundaries and follow the same behavior as the noninterlaced mode. Figure 1-24. Horizontal Timing Waveforms-Interlaced Format EQNP EQUALIZE* HSAP HSNP HSYNC* HSERNP SERRATION* HBLANK* HBNP Vertical Counter = n 1-50 Vertical Counter = n+1 Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_025 HBAP L498A_B L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-25. Interlaced Horizontal Timing for CSYNC* Signal HSYNC* Internal Half Line 0 HBNP Half Line 1 Half Line 2 Half Line 3 HBAP Active Video Active Video IOG CSYNC* Even Field CSYNC* Odd Field EQNP HSAP Full Scan Line 497-8_026 HSNP End of Vertical Sync. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-51 1-52 Preliminary Information/Conexant Proprietary and Confidential Conexant 497-8_027 CSYNC* HSYNC* EQUALIZE* Half Line Number SERRATION* VSYNC* 513 514 515 516 517 EIAP 518 519 520 521 522 523 524 Pre-Equalization Even Field 513 514 515 516 517 518 519 520 521 522 523 524 Odd Field 1 2 0 1 2 Odd Field 0 Even Field 3 3 4 4 5 5 6 6 8 9 10 11 7 8 9 10 11 Post-Equalization 7 12 12 14 13 14 EINP 13 38 38 39 39 40 40 41 41 1.17 Timing Generator EQUILIZATION Interval VBLANK* CSYNC* HSYNC* EQUALIZE* Half-Line Number SERRATION* VSYNC* (Serration Interval) EQUILIZING Interval VBLANK* 1.0 Circuit Description L498A_B 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 1-26. NTSC Interlaced Timing L498A_B L498A_B 1.0 Circuit Description 1.17 Timing Generator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Vertical Timing Generation Interlaced display on the Bt497A/498A adopts the convention of displaying the first line of active video, corresponding to the first line of the frame buffer on an even field; the second line of the frame buffer is displayed as the first line at the odd field. This allows the Bt497A/8A to properly order the cursor scan line. To keep this convention, the VBNP must be programmed with an odd value to ensure that the beginning of the horizontal events happened on an even cycle. VBAP can be programmed as an even or odd value depending on the number of lines in the frame buffer. The value in the VSAP register represents the total number of half-lines -1, while the value in the VSNP reflects the number of half-lines of serration during vertical sync. Interlaced operation requires two additional timing parameters, illustrated in Figure 1-26. EINP EIAP Equalization Interval Negation Point (EINP) indicates the last half-line following vertical sync on which to generate an equalize pulse. The value in this register and the VSNP register determine the number of Equalizing pulses in the post-equalization interval. Equalization Interval Assertion Point (EIAP) corresponds to the first equalizing pulse before vertical sync. The value in this register and the VSAP register determine the number of equalize pulses in the pre-equalization interval. The vertical timing registers should satisfy the following relationship: 0 < VSNP < EINP < VBNP < VBAP EIAP VSAP Composite Sync Generation The composite sync signal combines the HSYNC* with the serration and equalizing pulses on a discrete output. The start of the HSYNC* component depends on the field to be displayed. If it is an even field it starts on the first even half-line after the VSYNC* interval; if it is an odd field it starts on the first odd half-line. For composite monitors running interlace, the two Sync Disable bits in the Timing Control Register should match each other. If they are enabled, CSYNC* operates normally; if they are disabled, CSYNC* outputs a high level. Slave Mode Operation When the Timing Generator Control Register is programmed to slave mode, the timing generator accepts the FIELD signal as an input. In this mode, a transition occurring on this input causes the Timing Generator Vertical Counter to be reset and VSYNC to be asserted, regardless of the VSAP value, at the subsequent horizontal sync occurrence. If the Bt497A/498A is in interlaced mode, the level to which the FIELD input transitions determines which field is current (i.e., a high-to-low transition causes the timing generator to start at the top of an even field on the next HSYNC* leading edge). Since the Timing Generator Horizontal Counters are not reset, clock drift eventually causes the blanked front porch, for the slave, to be one line longer, or shorter. Master field transition must occur after VBAP and EIAP. Vertical front porch may need to be extended to accommodate this. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-53 L498A_B 1.0 Circuit Description 1.18 Monitor Identification and Control Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.18 Monitor Identification and Control Interface The Bt497A/8A incorporates two separate 2-bit registers for use as the hardware portion of a software driven, synchronous, half-duplex, serial interface. This interface provides the means for reading video monitor identification codes and for controlling certain monitor functions from the host system. The host system communicates with the interface registers via the MPU port. It is important to note that no interface control circuitry is required. The serial monitor features are not active during active video. These features could be accessed during blanking. The Monitor Port Data Register, illustrated in Figure 1-27, contains the levels intended for driving out on the individual open-drain monitor pins, SDA and SCL. A 0 in either bit causes the respective pin's buffer to drive an active low. A 1 causes the pin to be 3-stated. In this condition, the read-only Monitor Port Sense Register (Figure 1-28) may be accessed by the MPU to determine the actual level driven by the monitor on either SDA or SCL. X X X X X X SDA Data SCL Data 497-8_028 Figure 1-27. Monitor Port Data Register X 1-54 X X X X X SDA SCL Sense Sense 497-8_029 Figure 1-28. Monitor Port Sense Register Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 1.0 Circuit Description 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1.19 Video Generation 1.19 Video Generation Every clock cycle, the selected color information from the color model or cursor is presented to the D/A converters. Sync and blank information adds appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figure 1-29 and Figure 1-30. The varying output current from each of the D/A converters produces a corresponding voltage level, used to drive the color CRT monitor. Only the green output (IOG) can contain sync information. Table 1-16 and Table 1-17 detail how the sync and blank information from the timing generator modifies the output levels. The D/A converters on the Bt497A/8A7A use a segmented architecture in which bit currents go to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabilizes the D/A converter's full-scale output current against temperature and power supply variations. Figure 1-29. Composite Video Output Waveform (7.5 IRE Setup) RED, BLUE MA V GREEN MA V White Level 19.05 0.714 26.67 1.000 92.5 IRE 1.44 Black Level 0.054 9.05 0.340 7.5 IRE 0.00 0.000 Blank Level 7.62 0.286 Sync Level 0.00 0.000 L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_030 40 IRE 1-55 L498A_B 1.0 Circuit Description 1.19 Video Generation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-16. Video Output Truth Table (7.5 IRE Setup) Analog Level IOR (mA) IOB (mA) IOG (mA) VSYNC* HSYNC* VBLANK* HBLANK* DAC Input Data White 26.67 19.05 Disabled Disabled $FF Data Data + 9.05 Data + 1.44 Disabled Disabled Data Data-Sync Data + 1.44 Data + 1.44 Enabled Disabled Data Black 9.05 1.44 Disabled Disabled $00 Black-Sync 1.44 1.44 Enabled Disabled $00 Blank 7.62 0 Disabled Enabled $xx Sync 0 0 Enabled Enabled $xx Figure 1-30. Composite Video Output Waveform (0 IRE Setup) RED, BLUE MA V GREEN MA V 17.62 0.660 25.24 0.95 White Level 100 IRE 0.00 Black/Blank Level 0.000 7.62 0.286 Sync Level 0.00 0.000 0.00 0.000 1-56 Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_031 43 IRE L498A_B L498A_B 1.0 Circuit Description 1.19 Video Generation 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 1-17. Video Output Truth Table (0 IRE Setup) Analog Level IOR (mA) IOB (mA) IOG (mA) VSYNC* HSYNC* VBLANK* HBLANK* DAC Input Data White 25.24 17.62 Disabled Disabled $FF Data Data + 7.62 Data Disabled Disabled Data Data-Sync Data Data Enabled Disabled Data Black 7.62 0 Disabled Disabled $00 Black-Sync 0 0 Enabled Disabled $00 Blank 7.62 0 Disabled Enabled $xx Sync 0 0 Enabled Enabled $xx L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1-57 L498A_B 1.0 Circuit Description 1.19 Video Generation 1-58 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B 2 2.0 Internal Registers This section details the Bt497A/8A internal registers. The user should not access reserved address locations. Furthermore, the user needs to be aware of reserved bits when accessing internal registers via the MPU interface. Reserved bits do nothing if they are written to, and most give a zero value when their register is read out. However, to ensure compatibility with future Bt497A/8A code-compatible products, it is recommended that the reserved bits be maintained with read-modify-write access, which only updates unreserved bits. Also, in some registers, unreserved bits may not be resettable, but reserved bits have a reset value of zero. NOTE(S): R/O = Read Only, N/R = Not Resettable, R/W = Readable and Writable. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-1 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Pixel PLL Control Register (C[1,0] = 01, Address = $0000) Bit(s) Field Read /Write Reset Value Description 31-15 Reserved R/O -- Reserved. Returns zeros when read. 14 PLL Enable (0) Disable PLL (1) Enable PLL R/W 0 PLL enable control. A logical 1 enables the pixel PLL as the pixel clock source, using the crystal connected to the XTAL1 and XTAL2 inputs as the reference. A logical 0 disables the PLL. CLOCK and CLOCK* would then be directly used for the internal pixel clock. 13 Reserved R/O -- Reserved. Returns zeros when read. 12,11 L (00) (01) (10) (11) R/W 00 Post VCO frequency divider. R/W $4 PLL VCO divisor. R/W $27 PLL VCO multiplicand. 10-7 6-0 2-2 N ($0) : ($3) ($4) ($5) : ($A) ($B) ($C) ($D) : ($F) M ($00) : ($1F) ($20) ($21) : ($4F) ($50) ($51) : ($7F) Divide by 1 Divide by 2 Divide by 4 Divide by 8 Reserved Reserved Divide by 4 Divide by 5 Divide by 10 Divide by 11 Divide by 12 Reserved Reserved Reserved Reserved Multiply by 32 Multiply by 33 Multiply by 79 Multiply by 80 Reserved Reserved Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC General Purpose PLL Control Register (C[1,0] = 01, Address = $0001) Bit(s) Field Read / Write Reset Value Description 31-15 Reserved R/O -- Reserved. Returns zeros when read. 14 PLL Enable R/W 0 PLL enable control. A logic 1 enables the GP PLL as the General Purpose Clock source, using the XTAL1 and XTAL2 pins as reference. A logical 0 disables the PLL. CLOCK and CLOCK* would then be directly used as the GPCLK reference. 13 Reserved R/O -- Reserved. Returns zeros when read. 12,11 L (00) (01) (10) (11) R/W 1 Post VCO frequency divider. R/W 4 PLL VCO divisor. R/O -- Reserved. Returns zeros when read. R/W $1C PLL VCO multiplicand. 10-7 N ($0) : ($3) ($4) ($5) : ($E) ($F) 6 Reserved 5-0 M ($0) : ($14) ($15) ($16) : ($3E) ($3F) L498A_B Divide by 1 Divide by 2 Divide by 4 Divide by 8 Reserved Reserved Divide by 4 Divide by 5 Divide by 14 Divide by 15 Reserved Reserved Multiply by 21 Multiply by 22 Multiply by 62 Multiply by 63 Conexant Preliminary Information/Conexant Proprietary and Confidential 2-3 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Pixel Format Control Register (C[1,0] = 01, Address = $1000) Bit(s) Field Read / Write Reset Value Description 31-2 Reserved R/O -- Reserved. Returns zeros when read. 1,0 Pixel Format Control R/W N/R Selects the pixel interleaving format. The LD frequency in each multiplex rate would be as follows: FLD = Fp/2 MHz FLD = Fp/4 MHz FLD = Fp/2 MHz FLD = Fp/4 MHz Read/ Write Reset Value (00) (01) (10) (11) 2:1 4:1 4/2:1 8/2:1 User Control Register (C[1,0] = 01, Address = $1001) Bit(s) Field Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-8 Reserved R/O N/A This four bit field contains the current manufacturing revision for this device. 7,6 Reserved R/O 0 Returns zeros when read. 5,4 Window Mode (00) Combined (01) Separate_4 (10) Separate_8 (11) Reserved R/W 0 The Window Mode selection determines the specific source components to the 2 Window Lookup Tables, and the XO bus in the Color Model Control section. 3 Overlay Enable (0) Disabled (1) Enabled R/W 0 When this bit is 0, the color model control always expresses underlays. When this bit is 1, the color model control is determined by the Overlay/Underlay logic. 2 Double-Buffer Enable (0) Single Buffered (1) Double Buffered R/W 0 This field is valid only when in the 4/2:1 or 2:1 pixel format. Other formats require that this bit be set to zero. 1 Asynchronous Blank (0) Normal Operation (1) BLANK is constant R/W 0 Allows user to force a blank to the screen. 0 Input Pullup Disable (0) Enabled (1) Disabled R/W 0 Disables input pullup resistors on pins where present. Should be enabled during normal operation. 2-4 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Shadow-Overlay Window Lookup Table (C[1,0] = 01, Address: $3100-$3103) and Active-Overlay Window Lookup Table (C[1,0] = 01, Address: $3120-$3123) Bit(s) Field Read/ Write Reset Value Description 31-14 Reserved R/O -- Reserved. Returns zeros when read. 13, 12 Pseudo-Color Source (00) XO[7:0] (01) R[7:0] (10) G[7:0] (11) B[7:0] R/W N/R If overlays are active, these bits determine which pixel component gets replicated. 11,10 Overlay Type (00) No Overlay (01) Transparent Overlay (10) Opaque Overlay (11) Reserved R/W N/R If overlays are enabled, these bits determine if and when the overlay state becomes active. 9 Reserved R/O -- Reserved. Returns zeros when read. 8 Color Lookup (0) Bypass the Palette (1) Index through Palette R/W N/R If overlays are active, this bit controls whether the overlay pixel state addresses the Palette or bypasses it. 7,6 Reserved R/O -- Reserved. Returns zeros when read. 5,4 Palette Table (00) Table 0 (01) Table 1 (10) Table 2 (11) Table 3 R/W N/R If overlays are active, these bits select which of the 4 Palette tables are active for color lookup. 3-0 Palette Section, Separate_4 ($0) Section 0 ($1) Section 1 ($2) Section 2 : ($F) Section 15 R/W N/R These bits form the upper nibble of the XO field, if the Window Mode is Separate_4. If XO addresses the Palette, then this Section value corresponds to a contiguous 16-location section within the Palette. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-5 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Window Transfer Control Register (C[1,0] = 01, Address = $3150) Bit(s) Field Read/ Write Reset Value Description 31-5 Reserved R/O -- Reserved. Returns zeros when read. 4 Drawing Status (1) Network Drawing Active (0) Network Drawing Idle R/O N/R This bit gives the overall status of a networked system of multiple Bt497A/8A nodes. WLUT transfers may not occur until this bit is 0. 3 Drawing Data (1) Local Drawing Active (Pulldown) (0) Local Drawing Idle (3-state) R/W 0 This bit controls the level and drive of the Bt497A/8A's DRAWING* pin. Changes to this bit are latched and delayed such that the DRAWING* pin will not change its state anytime VBLANK is active. Systems using Bt497A, and single-Bt498A systems should leave this bit at 0. 2 Transfer Event (1) Next Frame (0) Next Field R/W 0 This bit controls the actual occurrence of the transfer, if the Transfer Command bit is set. If this bit is set to 0, then the transfer will occur on any transition of the field signal (0 1 or 1 0). If this bit is set to 1, the transfer occurs on the falling edge of field signal (1 0). 1 Transfer Command (1) Transfer (0) No Action R/W 0 Directs RAMDAC hardware to execute the transfer operation immediately upon, but not before, the arrival of the transfer event interval. This bit is set by software and is cleared by either of two events: by RAMDAC hardware when the transfer operation has been completed; or by software, indicating the command has been withdrawn. 0 Device Status (1) Busy, Table Unavailable (0) Idle, Table Available R/O 0 The Bt497A/8A controls this bit and indicates when a transfer is underway. Read/ Write Reset Value Transparent Mask Control Register (C[1,0] = 01, Address = $3151) Bit(s) Field Description 31-8 Reserved R/O -- Reserved. Returns zeros when read. 7-0 Overlay Mask (0) Deselect (1) Select R/W N/R When a bit in this field is set to a logical 1, it selects the bit in the Overlay Color Key Register to be compared with the bits in the X field. 2-6 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Transparent Color Key Register (C[1,0] = 01, Address = $3152) Bit(s) Field Read / Write Reset Value Description 31-8 Reserved R/O -- Reserved. Returns zeros when read. 7-0 Overlay Color Key R/W N/R When Overlays are enabled, the bits in this field that are selected by the Overlay Mask Control Register are compared to the bits in the X field. If they are equal, the underlay pixel is displayed. If they are not equal the Overlay State governs the Color Model selection. Read / Write Reset Value Window Address Mask Register (C[1,0] = 01, Address = $3153) Bit(s) Field Description 31-10 Reserved R/O -- Reserved. Returns zeros when read. 9,8 OMASK (00) Single OWLUT entry (Address 0) (01) Two OWLUT entries (Addresses 0 and 1) (10) Two OWLUT entries (Addresses 0 and 2) (11) All four OWLUT entries R/W N/R The OMASK bits determine the range and entries within the OWLUT that may control the Overlay State. 7,6 Reserved R/O -- Reserved. Returns zeros when read. 5-0 PMASK (0) (1) R/W N/R The PMASK bits determine the range and selection of the 64 entries within the PWLUT that may control the Underlay State. L498A_B Deselect Select Conexant Preliminary Information/Conexant Proprietary and Confidential 2-7 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Shadow-Primary Window Lookup Table (C[1,0] = 01, Address: $3200-$323F) and Active-Primary Window Lookup Table (C[1,0] = 01, Address: $3240-$327F) Bit(s) Field Read / Write Reset Value Description 31-16 Reserved R/O -- Reserved. Returns zeros when read. 15 Double Buffering (0) Buffer A (1) Buffer B R/W N/R If Underlays are active, this bit selects pixel data between Port A and Port B, for 2:1 and 4/2:1 Pixel Formats. 14 Color Depth (0) Pseudo-Color (1) True-Color R/W N/R If Underlays are active, this bit selects whether one 8-bit component is replicated to all 3 Color Channels. 13,12 Pseudo-Color Source (00) XO[7:0] (01) R[7:0] (10) G[7:0] (11) B[7:0] R/W N/R If Underlays are active and the Color Depth = Pseudo-Color, these bits determine which pixel component gets replicated. 11-9 Reserved R/O -- Reserved. Returns zeros when read. 8 Color Lookup (0) Bypass the Palette (1) Index through Palette R/W N/R If Underlays are active, this bit controls whether the Underlay pixel state addresses the palette or bypasses it. 7,6 Reserved R/O -- Reserved. Returns zeros when read. 5,4 Palette Table (00) Table 0 (01) Table 1 (10) Table 2 (11) Table 3 R/W N/R If Underlays are active, these bits select which of the 4 Palette tables are active for Color lookup. 3-0 Reserved R/O -- Reserved. Returns zeros when read. 2-8 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Signature Analysis Control Register (C[1,0] = 01, Address = $5000) Bit(s) Field Read/ Write Reset Value Description 31-28 Reserved R/O -- Reserved. Returns zeros when read. 27 Data Strobe Mode (0) Signature Analysis Mode (1) Data Strobe Mode R/W 0 This bit determines the method of high-speed test used. Signature analysis registers are used to hold the test results for both test methods. 26 Signature Analysis Busy (0) Idle (1) Busy R/O 0 Status of signature analysis logic. A logical 0 indicates the signature analysis has completed the previous signature acquisition. A logical 1 indicates a requested signature acquisition has been requested, but not completed. 25 Signature Capture Request (0) Cancel Signature Request (1) Request Signature Capture R/W 0 Writing a one causes the signature analysis logic to become busy and requests that the signature analysis logic capture a signature. The data written into bits 23 through 0 is used as the seed for signature acquisition for the frame. Writing a zero cancels any previously requested signature acquisition. 24 Signature Analysis Seed/ Result Dummy Bit R/W N/R Seed value or test result for dummy bit. 23-16 Signature Analysis Seed/ Result Blue DAC R/W N/R Seed value or test result for the blue DAC. 15-8 Signature Analysis Seed/ Result Green DAC R/W N/R Seed value or test result for the green DAC. 7-0 Signature Analysis Seed/ Result Red DAC R/W N/R Seed value or test result for the red DAC. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-9 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC DAC Control Register (C[1,0] = 01, Address = $5001) Bit(s) Field Read/ Write Reset Value Description 31-9 Reserved R/O -- Reserved. Returns zeros when read. 8 Sync Polarity Bit (0) VSYNC* and CSYNC* active low (1) VSYNC* and CSYNC* active high R/W 0 Reset or writing a zero causes VSYNC* and CSYNC* pins to be active low. Writing a one causes VSYNC* and CSYNC* to be active high. 7 VSYNC* Pin Disable (0) Pin expresses VSYNC* (1) Pin drives high if bit 8 is 0, low if bit 8 is 1 R/W 0 Reset or writing a zero enables the VSYNC* pin. The active state is determined by bit 8 of this register. 6 Pedestal Enable (0) No pedestal (1) 7.5 IRE pedestal R/W 0 This bit specifies whether a 0 or 7.5 IRE blanking pedestal is generated on the video outputs. 0 IRE specifies that the black and blank levels are the same. 5 SYNC on Green Enable (0) Disabled (1) Enabled R/W 0 This bit specifies whether sync information is output onto IOG. It has no effect on the CSYNC* pin. 4 Comparator Result (0) Operand 1 < Operand 2 (1) Operand 1 > Operand 2 R/O N/R This bit yields the result of the comparison of the DAC and/or reference output. Comparing operands whose values lie within a few LSBs will yield unpredictable results. Data written to this bit is ignored, as it is read only. The result is valid only after the required comparison setting time is reached (i.e., 5 s after the operand becomes constant). 3,2 Operand 1 Select (00) Normal Operation (01) Select Green DAC Output (10) Select Red DAC Output (11) Reserved R/W 00 This field selects Operand 1 of the comparator. For normal operation, the operand 1 and 2 fields should both contain 00. 1,0 Operand 2 Select (00) Normal Operation (01) Select 145 mv Reference (10) Select Blue DAC Output (11) Reserved R/W 00 This field selects Operand 2 of the comparator. For normal operation, the operand 1 and 2 fields should both contain 00. 2-10 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Timing Generator Control Register (C[1,0] = 01, Address = $6000) Bit(s) Field Read/ Write Reset Value Description 31-7 Reserved R/O -- Reserved. Returns zeros when read. 6 Interlaced Mode (0) Noninterlaced Mode (1) Interlaced Mode R/W 0 This bit selects the timing generators mode of operation. Reset or writing a zero causes the timing generator to operate in noninterlaced mode. A logical 1 causes the timing generator to operate in interlaced mode. 5 Master Mode (0) Slave (1) Master R/W 0 This bit controls the FIELD I/O signal direction. Reset or writing a zero to this bit causes the timing generator to be in slave mode, forcing the bidirectional FIELD signal to be an input (provided by the master timing generator). Writing a one causes the timing generator to be in the master mode, forcing the FIELD signal to be an output. 4 Equalization Disable (0) Equalization Enabled (1) Equalization Disabled R/W 0 If the chip is in interlaced mode, reset or writing a zero to this bit enables the equalizing pulses on CSYNC*. Otherwise, CSYNC* should look like the noninterlaced case. Horizontal syncs occur on CSYNC* except during vertical sync; during vertical sync CSYNC* has serration pulses. 3 Vertical Sync Disable(1) (0) VSYNC* Enabled (1) VSYNC* Disabled R/W 0 Reset or writing a zero to this bit causes the vertical sync to be enabled on the CSYNC* signal. Disabling VSYNC* during interlaced operation also disables HSYNC*. 2 Horizontal Sync Disable(1) (0) HSYNC* Enabled (1) HSYNC* Disabled R/W 0 Reset or writing a zero to this bit causes the horizontal sync to be enabled on the CSYNC* signal. Disabling HSYNC* during interlaced operation also disables VSYNC*. 1 Timing Generator Enable (0) Disabled (1) Enabled R/W 0 Upon reset or writing a zero to this bit, both the Timing Generator Horizontal and Vertical Counters are disabled and reset to zero. Writing a one enables both Timing Generator Horizontal and Vertical Counters. 0 Video Enable (0) Disabled (1) Enabled R/W 0 Reset or writing a zero to this bit causes the DAC outputs to be blanked. Writing a one, enables them. Any signature acquired during the video disable state will have data equal to zero. (1) Bits 3, 2, 0 disabling these output signals does not disable the internal timing generator L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-11 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Vertical Blank Negation Point Register (C[1,0] = 01, Address = $6001) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 VBNP R/W N/R This field represents the value of the Timing Generator Vertical Counter that corresponds to the end of the vertical blank interval. The next vertical count [VBNP+1] triggers the first line of active video. Programmed value should be greater than zero. Vertical Blank Assertion Point Register (C[1,0] = 01, Address = $6002) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 VBAP R/W N/R This field represents the value of the Timing Generator Vertical Counter that corresponds to the last line of active video. The next vertical count [VBAP+1] triggers the beginning of the vertical blank interval. Programmed value should be greater than zero. Vertical Sync. Negation Point Register (C[1,0] = 01, Address = $6003) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 VSNP R/W N/R This field represents the value of the Timing Generator Vertical Counter that corresponds to the last line of the vertical sync interval. Programmed value should be greater than zero. 2-12 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Vertical Sync. Assertion Point Register (C[1,0] = 01, Address = $6004) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 VSAP R/W N/R This field represents the value of the Timing Generator Vertical Counter that corresponds to the line before the beginning of vertical sync. The Timing Generator Vertical Counter is zero on the next line. VSAP+1 is the total number of lines. Programmed value should be greater than zero. Horizontal Serration Negation Point Register (C[1,0] = 01, Address = $6005) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HSERNP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that represents the duration -1 in serial clock periods of the serration pulses on CSYNC* during the vertical sync interval. Horizontal Blank Negation Point Register (C[1,0] = 01, Address = $6006) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HBNP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the last serial clock period of blanking before active video on a line. Programmed value should be greater than zero. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-13 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Horizontal Blank Assertion Point Register (C[1,0] = 01, Address = $6007) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HBAP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the last serial clock period of active video. Horizontal blanking starts with the next serial clock period. Programmed value should be greater than zero. Horizontal Sync. Negation Point Register (C[1,0] = 01, Address = $6008) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HSNP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the last serial clock period of horizontal sync. Programmed value should be greater than zero. Horizontal Sync. Assertion Point Register (C[1,0] = 01, Address = $6009) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HSAP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the last serial clock period of a line. HSAP+1 is the total number of serial clock periods in a line. The Timing Generator Horizontal Counter is zero on the next serial clock period. Programmed value should be greater than zero. 2-14 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Horizontal SCEN Negation Point Register (C[1,0] = 01, Address = $600A) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HSCENNP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the last serial clock period that SCEN* is active. Programmed value should be greater than zero. Horizontal SCEN Assertion Point Register (C[1,0] = 01, Address = $600B) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 HSCENAP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the start SCEN*. SCEN* is active on the next serial clock period. HSCENAP should be less than HBNP by exactly the number of serial clocks that it takes for pixel data to be clocked in at the Bt497A/8A inputs. HBNP and HSCENAP should always equal (HBAP and HSCENNP). Programmed value should be greater than zero. Equalizing Pulse Negation Point Register (C[1,0] = 01, Address = $600C) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 EQNP R/W N/R This field represents the value of the Timing Generator Horizontal Counter that corresponds to the last serial clock period of an equalizing pulse. Equalizing pulses always begin at horizontal coordinate 0. Equalizing pulses are generally one-half the duration of horizontal sync. Programmed value should be greater than zero. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-15 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Equalization Interval Negation Point Register (C[1,0] = 01, Address = $600D) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 EINP R/W N/R This field represents the value of the Timing Generator Vertical Counter that corresponds to the last half-line following vertical sync on which to generate an equalizing pulse. Programmed value should be greater than zero. Equalization Interval Assertion Point Register (C[1,0] = 01, Address = $600E) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 EIAP R/W N/R This field represents the value of the Timing Generator Vertical Counter that corresponds to the half-line before the beginning of the pre-equalization interval. The first equalizing pulse before vertical sync occurs on the next half-line. Programmed value should be greater than zero. Read/ Write Reset Value Timing Generator Vertical Counter (C[1,0] = 01, Address = $600F) Bit(s) Field Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 Vertical Line Counter R/O 0 This read-only field gives the real-time value of the Timing Generator Vertical Counter at the time it is read by the MPU. 2-16 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Timing Generator Horizontal Counter (C[1,0] = 01, Address = $6010) Bit(s) Field Read/ Write Reset Value Description 31-12 Reserved R/O -- Reserved. Returns zeros when read. 11-0 Horizontal Serial Clock Counter R/O 1 This read-only field gives the real-time value of the Timing Generator Horizontal Counter at the time it is read by the MPU. Read/ Write Reset Value Device Identification Register (C[1,0] = 01, Address = $8000) Bit(s) Field Description 31-28 Device Revision R/O $A Manufacturer Marketing Revision. The value stored in this field can be read through the JTAG Tap Access Port or the MPU Port. 27-12 Device Part Number R/O $236E Manufacturer Part Number. The value stored in this field can be read through the JTAG Tap Access Port or the MPU Port. 11-1 Device Manufacturer ID $0D6 R/O $0D6 Manufacturer Identification Number. The value stored in this field can be read through the JTAG Tap Access Port or the MPU Port. 0 Bit 0 = 1 R/O 1 Read/ Write Reset Value Final value for the register is $A236E1AD. Monitor Port Data Register (C[1,0] = 01, Address = $8001) Bit(s) Field Description 31-2 Reserved R/O -- Reserved. Returns zeros when read. 1 SDA Data R/W 1 The SDA Data bit determines the drive state of the open-drain SDA pin. A 0 causes the pin to drive an active low level. A 1 causes the pin to be 3-stated. Its level will be determined by the external Monitor connection. 0 SCL Data R/W 1 The SCL Data bit determines the drive state of the open-drain SCL pin. A 0 causes the pin to drive an active low level. A 1 causes the pin to be 3-stated. Its level will be determined by the external Monitor connection. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 2-17 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Monitor Port Sense Register (C[1,0] = 01, Address = $8002) Bit(s) Field Read/ Write Reset Value Description 31-2 Reserved R/O -- Reserved. Returns zeros when read. 1 SDA Sense R/O N/R The SDA Sense bit allows detection of the external SDA pin level whenever the corresponding SDA Data bit is 1. If SDA Data is 0, then SDA Sense will always contain 0. The Sense level is captured on the first falling edge of CE* during MPU read cycle. 0 SCL Sense R/O N/R The SCL Sense bit allows the external SCL pin level to be detected, whenever the corresponding SCL Data bit is 1. If SCL Data is 0, then SCL Sense will always contain 0. The Sense level is captured on the first falling edge of CE* during MPU read cycle. Read/ Write Reset Value Cursor Control Register (C[1,0] = 11, Address = $100) Bit(s) Field Description 31-2 Reserved R/O N/R Reserved. Returns zeros when read. 1 64 x 64 Cursor Plane1 Display Enable (0) Enabled (1) Disabled R/W $0 This bit specifies whether Plane1 of the 64 x 64 cursor is to be displayed. 0 64 x 64 Cursor Plane0 Display Enable (0) Enabled (1) Disabled R/W $0 This bit specifies whether Plane0 of the 64 x 64 cursor is to be displayed. 2-18 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Cursor Position Register (C[1,0] = 11, Address = $104) Bit(s) Field Reset Value R/W N/R Sign for the Y position of the cursor. Description 31 (0) (1) 30-28 Reserved R/O N/R Returns zeros when read. 27-16 Y Position R/W N/R Y cursor position, in number of lines, of the cursor. Values from $0000 to $0FFF can be written. 15 (0) (1) R/W N/R Sign for the X position of the cursor. 14-12 Reserved R/O N/R Reserved. Returns zeros when read. 11-0 X Position R/W N/R X cursor position, in number of pixels, of the cursor. Values from $0000 to $0FFF can be written. L498A_B Positive Negative Read/ Write Positive Negative Conexant Preliminary Information/Conexant Proprietary and Confidential 2-19 L498A_B 2.0 Internal Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 2-20 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B 3 3.0 PC Board Layout Considerations Optimize the Bt497A/8A layout for lowest noise on the power and ground lines by shielding the digital inputs and providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to minimize inductive ringing. This layout enables the Bt497A/8A to be located as close to the power supply connector and the video output connector as possible. A well-designed power distribution network is critical to eliminating digital switching noise. The ground planes must provide a low-impedance return path for the digital circuits. A PC board with a minimum of six layers is recommended. Use the ground layer as a shield to isolate noise from the analog traces with layer 1 (top), the analog traces; layer 2, the ground plane (preferable analog ground plane); and layer 3, the analog power plane. Use the remaining layers for digital traces and digital power supplies. Power and Ground Planes L498A_B The power and ground planes need isolation gaps at least 1/8-inch wide to minimize digital switching noise effects on the analog signals and components. Gaps are placed so that digital currents cannot flow through a peninsula that contains the analog components, signals, and video connector (a sample layout is illustrated in Figure 3-1). It is necessary to have separate planes for VAA3 and VAA5. The VAA3 plane covers all the digital signal line terminations at the Bt497A/8A with occasional openings for VAA5 access. Conexant Preliminary Information/Conexant Proprietary and Confidential 3-1 L498A_B 3.0 PC Board Layout Considerations 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 3-1. Representative Power/Ground Analog Area Layout Digital Area Bt497A/8A Analog Area Board Edge Device Decoupling Power Supply Decoupling For optimum performance, all capacitors should be located as close to the device as possible, using the shortest leads possible (consistent with reliable operation) to reduce the lead inductance. Chip capacitors are recommended for lead inductance. Radial lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self-resonance above the pixel clock. Best power supply decoupling performance is from a 0.1 F ceramic capacitor connected in parallel with a 0.01 F chip capacitor to decouple each group of VAA3 and VAA5 pins to GND. The capacitors should be placed as close as possible to the device VAA and GND pins. The 33 F capacitor illustrated in Figure 3-2 and Table 3-1 is for low-frequency power supply ripple; the 0.1 F and 0.01 F capacitors are for high-frequency power supply noise rejection. The decoupling capacitors should be connected at the VAA3, VAA5, and GND pins, using short, wide traces. When using a linear regulator, the power-up sequence must be verified to prevent latchup. A linear regulator is recommended to filter the analog power supply, if the power supply noise is greater than 200 mV. This is especially important with a switching power supply and when the switching frequency is close to the raster scan frequency. NOTE: 3-2 497-8_032 Video Connector About 10 percent of power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 3.0 PC Board Layout Considerations 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 3-2. Typical Analog Connection Diagram + 3.3 + C17, C18 C15, C16 C14 C13 Bt497A/8A VAA3 Locate as close as possible to Bt497A/8A C12 + C11 VAA5 VAA5 (@ pin 72) Bt498 (@ pin 55) Bt497A RANGE +5 (VCC) C9 R4 + C2-C4 VREF C5-C7 C10 C1 Z1 XTAL[1] GND X1 GROUND R1 RSET R2 R3 XTAL[2] FSADJ IOR P IOG P IOB P COMP C8 COMP2 To Monitor VAA5 P IN4148/9 DAC OUTPUT TO MONITOR 497-8_033 IN4148/9 Diode Protection Circuit Table 3-1. Typical Parts List Location Description C1-C4, C8, C9, C13, C17, C18 C5-C7, C11, C15, C16 C10, C14 C12 R1, R2, R3 R4 RSET X1 Z1 0.1 F Ceramic capacitor 0.01 F Ceramic chip capacitor 33 F Tantalum capacitor 4.7 F Tantalum capacitor 75 1% Metal film resistor 1000 5% Metal film resistor 1% Metal film resistor 10-24 MHz Crystal 1.2 V Voltage reference Vendor Part Number Erie RPE112Z5U104M50V AVX 12102T103QA1018 Mallory CSR13F336KM Mallory CSR13F477KM Dale CMF-55C Dale CMF-55C National Semiconductor LM385Z-1.2 NOTE(S): The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt497A/8A. Also, the VAA5 pins shown refer to the analog VAA5s which are located in the vicinity of the other analog pins. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 3-3 L498A_B 3.0 PC Board Layout Considerations 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 3-4 COMP Decoupling The COMP pin must be decoupled to COMP2, typically using a 0.1 F ceramic capacitor. Low-frequency supply noise requires a larger value capacitor. The COMP capacitor must be as close to the COMP and COMP2 pins as possible. A surface-mount ceramic chip capacitor is preferred for minimal lead inductance, which degrades the noise rejection of the circuit. Short, wide traces also reduce lead inductance. If the display has a ghosting problem, additional capacitance connected in parallel with the COMP capacitor may help fix the problem. VREF Decoupling A 0.1 F ceramic capacitor should be used to decouple this input to VAA5. If VAA5 is excessively noisy, better performance may be obtained by decoupling VREF to GND. Providing alternate PCB pads (one to VAA5 and one to GND) are recommended for the VREF decoupling capacitor. Digital Signal Interconnect The digital inputs to the Bt497A/8A should be isolated as much as possible from the analog outputs and other analog circuitry. These input signals should not overlay the analog power and output signals. Most noise on the analog outputs is caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs. Digital edge rates should be no faster than necessary, as feedthrough noise is proportional to the digital edge rates. Lower speed applications benefit from using lower speed logic (3-5 ns edge rates) to reduce data-related noise on the analog outputs. Transmission lines mismatch if they do not match the source and destination impedance. Signal fidelity degrades if the line length reflection time is greater than one-fourth the signal edge time. Line termination or line length reduction is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Damping the line with a series resistor (30-300 ) reduces ringing. Radiation of digital signals can be picked up by the analog circuitry. Reducing the digital edge rates (rise/fall time), minimizing ringing by using damping resistors, and minimizing coupling through PC board capacitance by routing 90 degrees to any analog signals prevents this. The clock driver and all other digital devices on the circuit board must have adequate decoupling to prevent noise generated by the digital devices from coupling into the analog circuitry. Analog Signal Interconnect The Bt497A/8A should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. To maximize high-frequency power supply rejection, the video output signals should overlay the analog ground plane. For maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. Analog output video edges exceeding the CRT monitor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high-frequency energy, reducing EMI and noise. The filter impedance must match line impedance. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 3.0 PC Board Layout Considerations 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Analog Output Protection L498A_B The Bt497A/8A analog outputs should be protected against high-energy discharges, such as those from monitor arc-over or from hot-switching AC-coupled monitors. The diode protection circuit illustrated in Figure 3-2 can prevent latchup under severe discharge conditions without adversely degrading analog transition times. The 1N4148/9 are low-capacitance, fast-switching diodes, which are available in multiple device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001). Conexant Preliminary Information/Conexant Proprietary and Confidential 3-5 L498A_B 3.0 PC Board Layout Considerations 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 3-6 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B 4 4.0 Application Information 4.1 Test Features of the Bt497A/8A The Bt497A/498A contains a Signature Analysis Control Register (SAR), a DAC output comparator, and JTAG test structures to assist the user in evaluating the performance and functionality of the part. This section explains the operating usage of these test features. 4.2 Signature Analysis Control Register (SAR) When enabled, the output SAR operates with the 24 bits of data presented to the DAC inputs. These 24-bit vectors represent a single pixel color, and are presented simultaneously as inputs to the red, green, and blue SARs, and the three on-chip DACs. The SAR acts as a wide linear feedback shift register on each succeeding DAC input. To simplify the feedback circuitry a 25th bit has been added, but has no corresponding test input. It is written and read through the MPU port as bit 24, which represents the LSB in the fourth CE* load cycle. The Bt497A/8A only generates signatures during the active video of two fields, starting on the first even field following a Signature Capture Request in the SAR. After the signature has been acquired, the SAR is available for reading and writing via the MPU port. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 4-1 L498A_B 4.0 Application Information 4.2 Signature Analysis Control Register (SAR) 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Typically, the user writes a specific 25-bit seed value into the SAR, then sets the Signature Capture Request bit. A full field of known pixel information is then input to the chip, after which the resultant 25-bit signature can be read by the MPU. The 25-bit signature results from the same color data fed to the DACs. Thus, overlay, cursor, and palette bypass data validity is tested using the SARs. Figure 4-1 illustrates the linear feedback configuration. Figure 4-1. Signature Analysis Feedback Circuit D[7:0] R[7:0] D[15:8] RED IN 0 1 2 3 4 5 6 7 IN G[7:0] D[23:16] GREEN 01234567 B[7:0] BLUE IN 0 1 2 3 4 5 6 7 Q 4-2 D Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_034 D[24] L498A_B L498A_B 4.0 Application Information 4.3 Analog Comparator 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 4.3 Analog Comparator The other dedicated test structure in the Bt497A/8A is the analog comparator. It allows the user to measure the DACs against each other, as well as against a specific reference voltage. Four combinations of tests are selected through the DAC Control Register. With a given setting, the respective signals (DAC outputs or the 145 mV reference) are continuously input to the comparator. The result of the comparator latches into the Timing Generator Test Register. The capture occurs at the bottom-right point of the 64 x 64 cursor bit map. Due to the simple design of the comparator, it is recommended that the DAC outputs be stable for 5 s before capture. At a display rate of 100 MHz, 5 s corresponds to 500 pixels. Furthermore, either the color palette RAM or the pixel inputs (or both) should be configured to guarantee a single continuous output from the DACs under test, until capture. 4.4 Device Identification Register The Bt497A/8A incorporates a Device Identification Register (Table 4-1) which can be accessed via the MPU port. The register is read only and uniquely identifies the device in accordance with requirements and principles set forth by the JEDEC organization. The Device Identification value can be read out via the JTAG interface. The final value read by the MPU port is $A236E1AD. Table 4-1. Device Identification Register Version 1 0 1 Part Number 0 0 0 1 0 0 0 1 1 0 1 Manufacturer ID 1 0 1 1 1 0 0 0 0 1 1 0 $A 9070, $236E $0D6 4 bits 16 bits 11 bits L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 1 0 1 1 0 1 4-3 L498A_B 4.0 Application Information 4.5 JTAG Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 4.5 JTAG Registers The Bt497A/8A incorporates special circuitry that allows it to be accessed in full compliance with standards set by the Joint Test Action Group (JTAG). Conforming to IEEE P1149.1, Standard Test Access Port and Boundary Scan Architecture, the Bt497A/8A has dedicated pins used for test purposes only. JTAG uses boundary-scan cells placed at each digital pin, Figure 4-2 illustrates both inputs and outputs. All scan cells interconnect into a Boundary-Scan Register (BSR). The register applies or captures test data used for functional verification of the Bt497A/8A. Even though the Bt497A has 64 pixel pins connected to its package, JTAG users of the Bt497A still need to account for all the unconnected Port B boundary-scan cells when they utilize the Bt497A Boundary-Scan Register. JTAG is particularly useful for board testers using functional testing methods. JTAG has five dedicated pins that comprise the Test Access Port (TAP): Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI), Test Data Out (TDO) and Test Reset (TRST*). Connection verification of the Bt497A/8A can be achieved through these five TAP pins. With boundary-scan cells at each digital pin, the Bt497A/8A applies and captures the logic level. Since all of the digital pins are interconnected as a long shift register, the TAP logic has access and control of all the pins necessary to verify functionality. The TAP controller can shift in any number of test vectors through the TDI input and apply them to the internal circuitry. The output result is scanned out on the TDO pin and externally checked. While isolating the Bt497A/8A from the other components on the board, the user has easy access to all Bt497A/8A digital pins through the TAP and can perform complete interconnect testing without using expensive bed-of-nails testers. The bidirectional MPU port and other digital I/Os require extra attention with respect to JTAG. Because JTAG requires full control over each digital pin, additional Output Enable (OE) cells are included in the BSR for the I/O and open-drain pins. Table 4-2 describes the scope and effects of the <OEFM> and <OEMPU> control cells. Tables 4-3 and 4-4 give further details concerning the JTAG accessible registers and test instructions supported. A BSDL has been created with the AT&T BSD Editor. Should JTAG testing be implemented, a disk with an ASCII version of the complete BSDL file can be obtained by calling 1-800-2BtApps. 4-4 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.5 JTAG Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 4-2. JTAG Boundry Scan Registers TDI PA[0] PA[13] PA[26] PB[6] PB[19] FIELD PB[32] PB[45] PB[58] PA[39] PA[52] SCEN* PA[1] PA[14] PA[27] PB[7] PB[20] STSCAN* PB[33] PB[46] PB[59] PA[40] PA[53] SC* PA[2] PA[15] PA[28] PB[8] PB[21] SCL_o PB[34] PB[47] PB[60] PA[41] PA[54] SCL_i PA[3] PA[16] PA[29] PB[9] PB[22] GPCLK PB[35] PB[48] PB[61] PA[42] PA[55] SDA_o PA[4] PA[17] PA[30] PB[10] PB[23] SDA_i PB[36] PB[49] PB[62] PA[43] PA[56] VSYNC* PA[5] PA[18] PA[31] PB[11] PB[24] <OEMPU> PB[37] PB[50] PB[63] PA[44] PA[57] D[7] PA[6] PA[19] LD* PB[12] PB[25] D[6] PB[38] PB[51] PA[32] PA[45] PA[58] D[5] PA[7] PA[20] PB[0] PB[13] PB[26] D[4] PB[39] PB[52] PA[33] PA[46] PA[59] D[3] PA[8] PA[21] PB[1] PB[14] PB[27] D[2] PB[40] PB[53] PA[34] PA[47] PA[60] D[1] PA[9] PA[22] PB[2] PB[15] PB[28] D[0] PB[41] PB[54] PA[35] PA[48] PA[61] LB* PA[10] PA[23] PB[3] PB[16] PB[29] C[1] PB[42] PB[55] PA[36] PA[49] PA[62] C[0] PA[11] PA[24] PB[4] PB[17] PB[30] RW PB[43] PB[56] PA[37] PA[50] PA[63] CE* PA[12] PA[25] PB[5] PB[18] PB[31] DRAWING*_o PB[44] PB[57] PA[38] PA[51] <OEFM> DRAWING*_i RESET* CLOCK TDO L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_035 CSYNC* 4-5 L498A_B 4.0 Application Information 4.5 JTAG Registers 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-2. JTAG Bidirectional Control Control Cell <OEFM> <OEMPU> Bidirect Pins FIELD D[7:0] Control = 1 Bidirect is Output mode. Level driven is determined by value scanned into corresponding Data cell. Control = 0 Bidirect is Input mode. Pin level may be latched into the corresponding Data cell. Table 4-3. JTAG Registers Name Width Instruction Register (IR) 4 Boundary Scan Register (BSR) 159 Description Holds and decodes active instruction. Corresponds to all chip digital pins. Bypass Register (BYR) 1 Holding D-FF, for bypassing chip. Device ID Register (DID) 32 Contains official part and manufacturing numbers. Table 4-4. JTAG Instructions 4-6 Code Name Register Description 0 EXTEST BSR Scan in test-vector, apply at outputs. 1 INTEST BSR Scan in test-vector, apply at inputs. 2 SAMPLE BSR Capture pin levels in BSR, scan out. 3-5, 7 <Reserved> -- 6 IDCODE BYR Pass data from TDI direct to TDO. 8-$F BYPASS DID Scan out the [read-only] DID information. -- Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 4.6 Initializing the Bt497A/8A 4.6 Initializing the Bt497A/8A Power up the VAA5 and VAA3 supplies in any order. Assert and release TRST*. Assert and release RESET* twice. The write instructions given in the MPU initialization sequence configure the Bt497A/8A to the following settings: 2:1 pixel format Block Cursor, enabled for both planes Cursor position X = 48, Y = 64 Sync-on-green enabled, 7.5 IRE blank pedestal, no analog compare PLL enabled to 135 MHz (assumes 13.5 MHz crystal, plus M = 40, N = 4, and L = 1) All (active) WID locations programmed to * True color, with input from port_A, color model = palette Timing generator programmed to * 1280 x 1024, 76 Hz noninterlaced mode, VSYNC* enabled, HSYNC* enabled, EQUALIZING disabled. The following register states endure from their Reset defaults: * SAR is not enabled * Serial monitor is all inputs * No transparent overlay, No double buffer, display enabled, pullups enabled * No pending transfer for WID RAM L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 4-7 L498A_B 4.0 Application Information 4.6 Initializing the Bt497A/8A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC MPU Initialization Sequence For best results, follow the Order of Writes given below. It is important to have the intended Pixel Format Register selection done before enabling the PLL via the PLL Control Register. Every MPU access consists of four CE* cycles, where each CE* cycle transfers 1 byte. C1,C0 Pixel and Clock Control Write $1000 to Configuration Pointer Write 0 to Pixel Format Register Write 0 to Configuration Pointer Write $4228 to pixel PLL Control Register 00 01 00 01 Load Cursor: Bitmap, Colors, Position Write 0 to Cursor Pointer Write $FFFFFFFF to Cursor RAM (location 0) Write $FFFFFFFF to Cursor RAM (location 1) : : Write $FFFFFFFF to Cursor RAM (location $FF) Write red, green, blue data to Color 1 Write red, green, blue data to Color 2 Write red, green, blue data to Color 3 Write $400030 to Cursor Position Register 10 11 11 11 11 11 11 11 C1,C0 Load Palette RAM Write $2000 to Configuration Pointer Write red, green, blue data to Palette 0 Write red, green, blue data to Palette 1 : : Write red, green, blue data to Palette $FF 00 01 01 01 Load WID Registers, DAC Control Write $3120 to Configuration Pointer Write $10 to Active WID (location 0) Write $10 to Active WID (location 1) : Write $10 to Active WID (location $1f) Write $5001 to Configuration Pointer Write $60 to DAC Control Register 00 01 01 : Load Timing Generator Registers Write $6001 to Configuration Pointer Write $027 to VBNP Register Write $427 to VBAP Register Write $007 to VSNP Register Write $429 to VSAP Register Write $31F to HSERNP Register Write $0AF to HBNP Register Write $32F to HBAP Register Write $01F to HSNP Register Write $33F to HSAP Register Write $32E to HSCENNP Register Write $0AE to HSCENAP Register 4-8 Conexant Preliminary Information/Conexant Proprietary and Confidential 01 00 01 C1,C0 00 01 01 01 01 01 01 01 01 01 01 01 L498A_B L498A_B 4.0 Application Information 4.6 Initializing the Bt497A/8A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Release Timing Generator, Begin Display (Assumes frame buffer or pixel generator are ready:) Write $6000 to Configuration Pointer Write $023 to Timing Generator Control Register Enable WID transfer control post Timing Generator Enable (Optional) 00 01 Table 4-5. 1280 x 1024 Noninterlaced Register Values L498A_B Register Value (dec) Hex VBNP 39 $027 VBAP 1063 $427 VSNP 7 $007 VSAP 1065 $429 HSERNP 799 $31F HBNP 175 $0AF HBAP 815 $32F HSNP 31 $01F HSAP 831 $33F HSCENNP 814 $32E HSCENAP 174 $0AE Conexant Preliminary Information/Conexant Proprietary and Confidential 4-9 L498A_B 4.0 Application Information 4.6 Initializing the Bt497A/8A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 1280 x 1024 x 76 Hz Noninterlaced Display See Table 4-5 for noninterlaced register values. Horizontal Pixels: 1280 Vertical Lines: 1024 Horizontal Frequency: 81.13 kHz Horizontal Sync: 0.474 s Horizontal Unblanked: 9.48 s Horizontal Blanking: 2.84 s Total Vertical Lines: 1066 Vertical Frequency: 76.11 Hz Vertical Sync: 8 Lines Pixel Clock: 135 MHz Crystal: 13.5 MHz Frame Buffer Pipeline: 1 serial clock cycle NTSC Interlaced Display See Table 4-6 for NTSC register values. Horizontal Pixels: 640 Vertical Lines: 480 Horizontal Frequency: 15.73 kHz Horizontal Sync: 4.73 s Horizontal Unblanked: 52.15 s Horizontal Blanking: 11.41 s Total Vertical Lines: 525 Vertical Frequency: 59.94 Hz Vertical Sync: 3 Lines Equal. Pulses: 6 Pre and Post 12 full lines after equal before 1st line of active video for field 0. Pixel Clock: 12.273 MHz Crystal: 13.5 MHz PLL Control Register PLL: Enable M = 80 N = 11 L=8 Pixel Format Control Register Pixel Format: 4/2:1 or 2:1 Timing Generation Control Register EQUAL*: Enabled Interlaced mode: Enabled VSYNC*: Enabled HSYNC*: Enabled Frame Buffer Pipeline: 1 serial clock cycle 4-10 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.6 Initializing the Bt497A/8A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-6. NTSC Register Values L498A_B Register Value (dec) Hex VBNP 37 $25 VBAP 517 $205 VSNP 5 $5 VSAP 524 $20C HSERNP 165 $A5 HBNP 59 $3B HBAP 184 $B8 HSNP 28 $1C HSAP 194 $C2 HSCENNP 183 $B7 HSCENAP 58 $3A EQNP 13 $D EINP 11 $B EIAP 518 $206 Conexant Preliminary Information/Conexant Proprietary and Confidential 4-11 L498A_B 4.0 Application Information 4.6 Initializing the Bt497A/8A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC PAL Interlaced Display See Table 4-7 for PAL register values. Horizontal Pixels: 768 Vertical Lines: 625 Horizontal Frequency: 15.62 kHz Horizontal Sync: 4.79 s Horizontal Unblanked: 52.51 s Horizontal Blanking: 11.49 s Total Vertical Lines: 570 Vertical Frequency: 50 Hz Vertical Sync: 2.5 Lines Equalizing Pulses:5 Pre and Post 17 full lines after equal before 1st line of active video for field 0 Pixel Clock: 14.625 MHz Crystal = 13.5 MHz PLL Control Register PLL: Enable M = 52 N=6 L=8 Pixel Format Control Register Pixel Format: 4/2:1 or 2:1 Timing Generation Control Register EQUAL*: Enabled Interlaced Mode: Enabled VSYNC*: Enabled HSYNC*: Enabled Frame Buffer Pipeline: 1 serial clock cycle 4-12 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.6 Initializing the Bt497A/8A 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-7. PAL Register Values L498A_B Register Value (dec) Hex VBNP 43 $2B VBAP 618 $26A VSNP 4 $4 VSAP 624 $270 HSERNP 200 $C8 HBNP 76 $4C HBAP 226 $E2 HSNP 34 $22 HSAP 233 $E9 HSCENNP 225 $E1 HSCENAP 75 $4B EQNP 16 $10 EINP 9 $9 EIAP 619 $26B Conexant Preliminary Information/Conexant Proprietary and Confidential 4-13 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 4.7 PLL Initialization The Bt497A/8A-Generated VRAM Shift Clock and Pixel PLL-Generated Pixel Clock In this configuration, the on-chip Pixel PLL generates the pixel clock. SC* runs continuously and shifts out pixel data from the VRAMs. Here, a relatively low-frequency crystal connects to the XTAL1 and XTAL2 inputs, instead of using an ECL oscillator operated on a pseudo-ECL supply (i.e., +5 and GND) connected to the CLOCK and CLOCK* inputs of the Bt497A/8A, as shown in Figures 1-5, 1-6, and 1-7 in the Chapter 1.0, Circuit Description of this document. Crystal Frequency Selection The crystal frequency should be selected based on the required pixel rate(s) and the display pixel rate tolerance. The desired ratio for the PLL is then computed by dividing the required pixel rate by the crystal frequency, looking up the M and N values in the ratio table (Table 4-8) for the closest ratio, and ensuring that the display still operates satisfactorily within the best-fit pixel rate and associated CRT timings. It is assumed that the choice of crystal is dictated by desired pixel frequencies, and that GPCLK frequency choices are lower priority. Ratio Selection Programming the M and N values through the MPU port sets the PLL clock ratios. Table 4-8 and Table 4-9 show the complete range of pixel clock and GPCLK frequencies corresponding to various settings for M, N, and L. Table 4-8 shows VCO frequency only. Pixel rate is further selectable to be 1/1, 1/2, 1/4, or 1/8 of VCO frequency by programming the L value. Pixel PLL Deselection Users planning to utilize the two PLLs exclusively should still provide definite connections to the CLOCK and CLOCK* pins, as shown in Figure 4-3. With this hookup, the user may shut off the pixel display operation of the chip at any time to save AC power. This clock shut off is accomplished by writing a 0 into bit 14 of the Pixel PLL Control Register. Among other effects, this also forces the SC* output to a DC state. The two PLLs are deselected by chip reset. 4-14 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 4-3. CLOCK and XTAL Connections for PLL Operation +5 100 CLOCK CLOCK* 100 XTAL1 Crystal 13 or 14 MHz SC* SC Divider MPX Internal RAMDAC Pixel Clock Pixel Clock PLL M/NxL XTAL2 General Purpose PLL M/NxL GPCLK 497-8_036 MPX Table 4-8. Pixel Rate Selection (1 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = L498A_B M/N M N 13.50 MHz 14.31818 MHz N/A 96.136 6.714 47 7 N/A 96.322 6.727 74 11 N/A 96.648 6.750 54 8 N/A 97.045 6.778 61 9 N/A 97.364 6.800 34 5 N/A 97.624 6.818 75 11 N/A 97.841 6.833 41 6 N/A 98.182 6.857 48 7 N/A 98.437 6.875 55 8 N/A 98.636 6.889 62 9 N/A 98.795 6.900 69 10 N/A 98.926 6.909 76 11 N/A 100.227 7.000 35 5 N/A 101.529 7.091 78 11 N/A 101.659 7.100 71 10 96.000 101.818 7.111 64 9 Conexant Preliminary Information/Conexant Proprietary and Confidential 4-15 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-8. Pixel Rate Selection (2 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = 4-16 M/N M N 13.50 MHz 14.31818 MHz 96.188 102.017 7.125 57 8 96.429 102.273 7.143 50 7 96.750 102.614 7.167 43 6 96.955 102.831 7.182 79 11 97.200 103.091 7.200 36 5 97.500 103.409 7.222 65 9 97.875 103.807 7.250 58 8 98.182 104.132 7.273 80 11 98.357 104.318 7.286 51 7 98.550 104.523 7.300 73 10 99.000 105.000 7.333 44 6 99.563 105.597 7.375 59 8 99.900 105.955 7.400 37 5 100.286 106.364 7.429 52 7 100.500 106.591 7.444 67 9 101.250 107.386 7.500 45 6 102.000 108.182 7.556 68 9 102.214 108.409 7.571 53 7 102.600 108.818 7.600 38 5 102.938 109.176 7.625 61 8 103.500 109.773 7.667 46 6 103.950 110.250 7.700 77 10 104.143 110.455 7.714 54 7 104.625 110.966 7.750 62 8 105.000 111.364 7.778 70 9 105.300 111.682 7.800 39 5 105.750 112.159 7.833 47 6 106.071 112.500 7.857 55 7 106.313 112.756 7.875 63 8 106.500 112.955 7.889 71 9 106.650 113.114 7.900 79 10 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-8. Pixel Rate Selection (3 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = L498A_B M/N M N 13.50 MHz 14.31818 MHz 108.000 114.545 8.000 32 4 109.500 116.136 8.111 73 9 109.688 116.335 8.125 65 8 109.929 116.591 8.143 57 7 110.250 116.932 8.167 49 6 110.700 117.409 8.200 41 5 111.000 117.727 8.222 74 9 111.375 118.125 8.250 33 4 111.857 118.636 8.286 58 7 112.500 119.318 8.333 50 6 113.063 119.915 8.375 67 8 113.400 120.273 8.400 42 5 113.786 120.682 8.429 59 7 114.000 120.909 8.444 76 9 114.750 121.705 8.500 34 4 115.500 122.500 8.556 77 9 115.714 122.727 8.571 60 7 116.100 123.136 8.600 43 5 116.438 123.494 8.625 69 8 117.000 124.091 8.667 52 6 117.643 124.773 8.714 61 7 118.125 125.284 8.750 35 4 118.500 125.682 8.778 79 9 118.800 126.000 8.800 44 5 119.250 126.477 8.833 53 6 119.571 126.818 8.857 62 7 119.813 127.074 8.875 71 8 120.000 127.273 8.889 80 9 121.500 128.864 9.000 36 4 123.188 130.653 9.125 73 8 123.429 130.909 9.143 64 7 Conexant Preliminary Information/Conexant Proprietary and Confidential 4-17 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-8. Pixel Rate Selection (4 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = 4-18 M/N M N 13.50 MHz 14.31818 MHz 123.750 131.250 9.167 55 6 124.200 131.727 9.200 46 5 124.875 132.443 9.250 37 4 125.357 132.955 9.286 65 7 126.000 133.636 9.333 56 6 126.563 134.233 9.375 75 8 126.900 134.591 9.400 47 5 127.286 135.000 9.429 66 7 128.250 136.023 9.500 38 4 129.214 137.045 9.571 67 7 129.600 137.455 9.600 48 5 129.938 137.812 9.625 77 8 130.500 138.409 9.667 58 6 131.143 139.091 9.714 68 7 131.625 139.602 9.750 39 4 132.300 140.318 9.800 49 5 132.750 140.795 9.833 59 6 133.071 141.136 9.857 69 7 133.313 141.392 9.875 79 8 135.000 143.182 10.000 40 4 136.929 145.227 10.143 71 7 137.250 145.568 10.167 61 6 137.700 146.045 10.200 51 5 138.375 146.761 10.250 41 4 138.857 147.273 10.286 72 7 139.500 147.955 10.333 62 6 140.400 148.909 10.400 52 5 140.786 149.318 10.429 73 7 141.750 150.341 10.500 42 4 142.714 151.364 10.571 74 7 143.100 151.773 10.600 53 5 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-8. Pixel Rate Selection (5 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = L498A_B M/N M N 13.50 MHz 14.31818 MHz 144.000 152.727 10.667 64 6 144.643 153.409 10.714 75 7 145.125 153.920 10.750 43 4 145.800 154.636 10.800 54 5 146.250 155.114 10.833 65 6 146.571 155.455 10.857 76 7 148.500 157.500 11.000 44 4 150.429 159.545 11.143 78 7 150.750 159.886 11.167 67 6 151.200 160.364 11.200 56 5 151.875 161.080 11.250 45 4 152.357 161.591 11.286 79 7 153.000 162.273 11.333 68 6 153.900 163.227 11.400 57 5 154.286 163.636 11.429 80 7 155.250 164.659 11.500 46 4 156.600 166.091 11.600 58 5 157.500 167.045 11.667 70 6 158.625 168.239 11.750 47 4 159.300 168.955 11.800 59 5 159.750 169.432 11.833 71 6 162.000 171.818 12.000 48 4 164.250 174.205 12.167 73 6 164.700 174.682 12.200 61 5 165.375 175.398 12.250 49 4 166.500 176.591 12.333 74 6 167.400 177.545 12.400 62 5 168.750 178.977 12.500 50 4 170.100 180.409 12.600 63 5 171.000 181.364 12.667 76 6 172.125 182.557 12.750 51 4 Conexant Preliminary Information/Conexant Proprietary and Confidential 4-19 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-8. Pixel Rate Selection (6 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = 4-20 M/N M N 13.50 MHz 14.31818 MHz 172.800 183.273 12.800 64 5 173.250 183.750 12.833 77 6 175.500 186.136 13.000 52 4 177.750 188.523 13.167 79 6 178.200 189.000 13.200 66 5 178.875 189.716 13.250 53 4 180.000 190.909 13.333 80 6 180.900 191.864 13.400 67 5 182.250 193.295 13.500 54 4 183.600 194.727 13.600 68 5 185.625 196.875 13.750 55 4 186.300 197.591 13.800 69 5 189.000 200.455 14.000 56 4 191.700 203.318 14.200 71 5 192.375 204.034 14.250 57 4 194.400 206.182 14.400 72 5 195.750 207.614 14.500 58 4 197.100 209.045 14.600 73 5 199.125 211.193 14.750 59 4 199.800 211.909 14.800 74 5 202.500 214.773 15.000 60 4 205.200 217.636 15.200 76 5 205.875 218.352 15.250 61 4 207.900 220.500 15.400 77 5 209.250 221.932 15.500 62 4 210.600 223.364 15.600 78 5 212.625 225.511 15.750 63 4 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-8. Pixel Rate Selection (7 of 7) Pixel Clock Rate (MHz), L = 0 w/Reference Crystal = M/N M N 13.50 MHz 14.31818 MHz 213.300 226.227 15.800 79 5 216.000 229.091 16.000 64 4 219.375 232.670 16.250 65 4 222.750 236.250 16.500 66 4 226.125 239.830 16.750 67 4 239.625 N/A 17.750 71 4 Table 4-9. GPCLK PLL Programming Table (1 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L N/A 10.7386 30 5 3 12.0234 12.7521 57 8 3 N/A 10.9176 61 10 3 12.0536 12.7841 50 7 3 N/A 10.9375 55 9 3 12.0938 12.8267 43 6 3 N/A 10.9624 49 8 3 12.15 12.8864 36 5 3 N/A 10.9943 43 7 3 12.2344 12.9759 29 4 3 N/A 11.0369 37 6 3 12.2946 13.0398 51 7 3 N/A 11.0966 31 5 3 12.375 13.125 44 6 3 N/A 11.1364 56 9 3 12.4453 13.1996 59 8 3 N/A 11.1861 25 4 3 12.4875 13.2443 37 5 3 N/A 11.25 44 7 3 12.5357 13.2955 52 7 3 10.6313 11.2756 63 10 3 12.6563 13.4233 30 4 3 10.6875 11.3352 38 6 3 12.7768 13.5511 53 7 3 10.7578 11.4098 51 8 3 12.825 13.6023 38 5 3 10.8 11.4545 32 5 3 12.8672 13.647 61 8 3 10.8482 11.5057 45 7 3 12.9375 13.7216 46 6 3 10.875 11.5341 58 9 3 13.0179 13.8068 54 7 3 10.9688 11.6335 26 4 3 13.0781 13.8707 31 4 3 11.0625 11.733 59 9 3 13.1625 13.9602 39 5 3 11.0893 11.7614 46 7 3 13.2188 14.0199 47 6 3 11.1375 11.8125 33 5 3 13.2589 14.0625 55 7 3 L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 4-21 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-9. GPCLK PLL Programming Table (2 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L 11.1797 11.8572 53 8 3 13.2891 14.0945 63 8 3 11.25 11.9318 40 6 3 13.5 14.3182 32 4 3 11.3304 12.017 47 7 3 13.7411 14.5739 57 7 3 11.3906 12.081 27 4 3 13.7813 14.6165 49 6 3 11.4375 12.1307 61 9 3 13.8375 14.6761 41 5 3 11.475 12.1705 34 5 3 13.9219 14.7656 33 4 3 11.5313 12.2301 41 6 3 13.9821 14.8295 58 7 3 11.5714 12.2727 48 7 3 14.0625 14.9148 50 6 3 11.6016 12.3047 55 8 3 14.175 15.0341 42 5 3 11.625 12.3295 62 9 3 14.2232 15.0852 59 7 3 11.8125 12.5284 28 4 3 14.3438 15.2131 34 4 3 14.4643 15.3409 60 7 3 18.9 20.0455 56 5 3 14.5125 15.392 43 5 3 18.9844 20.1349 45 4 3 14.625 15.5114 52 6 3 19.2375 20.4034 57 5 3 14.7054 15.5966 61 7 3 19.4063 20.5824 46 4 3 14.7656 15.6605 35 4 3 19.575 20.7614 58 5 3 14.85 15.75 44 5 3 19.8281 21.0298 47 4 3 14.9063 15.8097 53 6 3 19.9125 21.1193 59 5 3 14.9464 15.8523 62 7 3 20.25 N/A 48 4 3 15.1875 16.108 36 4 3 20.5875 N/A 61 5 3 15.4688 16.4062 55 6 3 20.6719 N/A 49 4 3 15.525 16.4659 46 5 3 20.925 N/A 62 5 3 15.6094 16.5554 37 4 3 21.0938 N/A 50 4 3 15.75 16.7045 56 6 3 N/A 21.4773 30 5 2 15.8625 16.8239 47 5 3 N/A 21.8352 61 10 2 16.0313 17.0028 38 4 3 N/A 21.875 55 9 2 16.2 17.1818 48 5 3 N/A 21.9247 49 8 2 16.3125 17.3011 58 6 3 N/A 21.9886 43 7 2 16.4531 17.4503 39 4 3 N/A 22.0739 37 6 2 16.5375 17.5398 49 5 3 N/A 22.1932 31 5 2 16.5938 17.5994 59 6 3 N/A 22.2727 56 9 2 16.875 17.8977 40 4 3 N/A 22.3722 25 4 2 4-22 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-9. GPCLK PLL Programming Table (3 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L 17.1563 18.196 61 6 3 N/A 22.5 44 7 2 17.2125 18.2557 51 5 3 21.2625 22.5511 63 10 2 17.2969 18.3452 41 4 3 21.375 22.6705 38 6 2 17.4375 18.4943 62 6 3 21.5156 22.8196 51 8 2 17.55 18.6136 52 5 3 21.6 22.9091 32 5 2 17.7188 18.7926 42 4 3 21.6964 23.0114 45 7 2 17.8875 18.9716 53 5 3 21.75 23.0682 58 9 2 18.1406 19.2401 43 4 3 21.9375 23.267 26 4 2 18.225 19.3295 54 5 3 22.125 23.4659 59 9 2 18.5625 19.6875 44 4 3 22.1786 23.5227 46 7 2 22.275 23.625 33 5 2 26.5179 28.125 55 7 2 22.3594 23.7145 53 8 2 26.5781 28.1889 63 8 2 22.5 23.8636 40 6 2 27 28.6364 32 4 2 22.6607 24.0341 47 7 2 27.4821 29.1477 57 7 2 22.7813 24.1619 27 4 2 27.5625 29.233 49 6 2 22.875 24.2614 61 9 2 27.675 29.3523 41 5 2 22.95 24.3409 34 5 2 27.8438 29.5312 33 4 2 23.0625 24.4602 41 6 2 27.9643 29.6591 58 7 2 23.1429 24.5455 48 7 2 28.125 29.8295 50 6 2 23.2031 24.6094 55 8 2 28.35 30.0682 42 5 2 23.25 24.6591 62 9 2 28.4464 30.1705 59 7 2 23.625 25.0568 28 4 2 28.6875 30.4261 34 4 2 24.0469 25.5043 57 8 2 28.9286 30.6818 60 7 2 24.1071 25.5682 50 7 2 29.025 30.7841 43 5 2 24.1875 25.6534 43 6 2 29.25 31.0227 52 6 2 24.3 25.7727 36 5 2 29.4107 31.1932 61 7 2 24.4688 25.9517 29 4 2 29.5313 31.321 35 4 2 24.5893 26.0795 51 7 2 29.7 31.5 44 5 2 24.75 26.25 44 6 2 29.8125 31.6193 53 6 2 24.8906 26.3991 59 8 2 29.8929 31.7045 62 7 2 24.975 26.4886 37 5 2 30.375 32.2159 36 4 2 25.0714 26.5909 52 7 2 30.9375 32.8125 55 6 2 L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 4-23 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-9. GPCLK PLL Programming Table (4 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L 25.3125 26.8466 30 4 2 31.05 32.9318 46 5 2 25.5536 27.1023 53 7 2 31.2188 33.1108 37 4 2 25.65 27.2045 38 5 2 31.5 33.4091 56 6 2 25.7344 27.294 61 8 2 31.725 33.6477 47 5 2 25.875 27.4432 46 6 2 32.0625 34.0057 38 4 2 26.0357 27.6136 54 7 2 32.4 34.3636 48 5 2 26.1563 27.7415 31 4 2 32.625 34.6023 58 6 2 26.325 27.9205 39 5 2 32.9063 34.9006 39 4 2 26.4375 28.0398 47 6 2 33.075 35.0795 49 5 2 33.1875 35.1989 59 6 2 N/A 44.5454 56 9 1 33.75 35.7955 40 4 2 N/A 44.7443 25 4 1 34.3125 36.392 61 6 2 N/A 45 44 7 1 34.425 36.5114 51 5 2 42.525 45.1023 63 10 1 34.5938 36.6903 41 4 2 42.75 45.3409 38 6 1 34.875 36.9886 62 6 2 43.0313 45.6392 51 8 1 35.1 37.2273 52 5 2 43.2 45.8182 32 5 1 35.4375 37.5852 42 4 2 43.3929 46.0227 45 7 1 35.775 37.9432 53 5 2 43.5 46.1364 58 9 1 36.2813 38.4801 43 4 2 43.875 46.5341 26 4 1 36.45 38.6591 54 5 2 44.25 46.9318 59 9 1 37.125 39.375 44 4 2 44.3571 47.0454 46 7 1 37.8 40.0909 56 5 2 44.55 47.25 33 5 1 37.9688 40.2699 45 4 2 44.7188 47.429 53 8 1 38.475 40.8068 57 5 2 45 47.7273 40 6 1 38.8125 41.1648 46 4 2 45.3214 48.0682 47 7 1 39.15 41.5227 58 5 2 45.5625 48.3239 27 4 1 39.6563 42.0597 47 4 2 45.75 48.5227 61 9 1 39.825 42.2386 59 5 2 45.9 48.6818 34 5 1 40.5 N/A 48 4 2 46.125 48.9204 41 6 1 41.175 N/A 61 5 2 46.2857 49.0909 48 7 1 41.3438 N/A 49 4 2 46.4063 49.2187 55 8 1 41.85 N/A 62 5 2 46.5 49.3182 62 9 1 4-24 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-9. GPCLK PLL Programming Table (5 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L 42.1875 N/A 50 4 2 47.25 50.1136 28 4 1 N/A 42.9545 30 5 1 48.0938 51.0085 57 8 1 N/A 43.6704 61 10 1 48.2143 51.1364 50 7 1 N/A 43.75 55 9 1 48.375 51.3068 43 6 1 N/A 43.8494 49 8 1 48.6 51.5454 36 5 1 N/A 43.9773 43 7 1 48.9375 51.9034 29 4 1 N/A 44.1477 37 6 1 49.1786 52.1591 51 7 1 N/A 44.3864 31 5 1 49.5 52.5 44 6 1 49.7813 52.7983 59 8 1 59.7857 63.4091 62 7 1 49.95 52.9773 37 5 1 60.75 64.4318 36 4 1 50.1429 53.1818 52 7 1 61.875 65.625 55 6 1 50.625 53.6932 30 4 1 62.1 65.8636 46 5 1 51.1071 54.2045 53 7 1 62.4375 66.2216 37 4 1 51.3 54.4091 38 5 1 63 66.8182 56 6 1 51.4688 54.5881 61 8 1 63.45 67.2954 47 5 1 51.75 54.8864 46 6 1 64.125 68.0114 38 4 1 52.0714 55.2273 54 7 1 64.8 68.7273 48 5 1 52.3125 55.4829 31 4 1 65.25 69.2045 58 6 1 52.65 55.8409 39 5 1 65.8125 69.8011 39 4 1 52.875 56.0795 47 6 1 66.15 70.1591 49 5 1 53.0357 56.25 55 7 1 66.375 70.3977 59 6 1 53.1563 56.3778 63 8 1 67.5 71.5909 40 4 1 54 57.2727 32 4 1 68.625 72.7841 61 6 1 54.9643 58.2954 57 7 1 68.85 73.0227 51 5 1 55.125 58.4659 49 6 1 69.1875 73.3807 41 4 1 55.35 58.7045 41 5 1 69.75 73.9773 62 6 1 55.6875 59.0625 33 4 1 70.2 74.4545 52 5 1 55.9286 59.3182 58 7 1 70.875 75.1704 42 4 1 56.25 59.6591 50 6 1 71.55 75.8864 53 5 1 56.7 60.1364 42 5 1 72.5625 76.9602 43 4 1 56.8929 60.3409 59 7 1 72.9 77.3182 54 5 1 57.375 60.8523 34 4 1 74.25 78.75 44 4 1 L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 4-25 L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-9. GPCLK PLL Programming Table (6 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L 57.8571 61.3636 60 7 1 75.6 80.1818 56 5 1 58.05 61.5682 43 5 1 75.9375 80.5398 45 4 1 58.5 62.0454 52 6 1 76.95 81.6136 57 5 1 58.8214 62.3864 61 7 1 77.625 82.3295 46 4 1 59.0625 62.642 35 4 1 78.3 83.0454 58 5 1 59.4 63 44 5 1 79.3125 84.1193 47 4 1 59.625 63.2386 53 6 1 79.65 84.4773 59 5 1 81 N/A 48 4 1 92.25 97.8409 41 6 0 82.35 N/A 61 5 1 92.5714 98.1818 48 7 0 82.6875 N/A 49 4 1 92.8125 98.4375 55 8 0 83.7 N/A 62 5 1 93 98.6364 62 9 0 84.375 N/A 50 4 1 94.5 100.2273 28 4 0 N/A 85.9091 30 5 0 96.1875 102.017 57 8 0 N/A 87.3409 61 10 0 96.4286 102.2727 50 7 0 N/A 87.5 55 9 0 96.75 102.6136 43 6 0 N/A 87.6989 49 8 0 97.2 103.0909 36 5 0 N/A 87.9545 43 7 0 97.875 103.8068 29 4 0 N/A 88.2954 37 6 0 98.3571 104.3182 51 7 0 N/A 88.7727 31 5 0 99 105 44 6 0 N/A 89.0909 56 9 0 99.5625 105.5966 59 8 0 N/A 89.4886 25 4 0 99.9 105.9545 37 5 0 N/A 90 44 7 0 100.2857 106.3636 52 7 0 85.05 90.2045 63 10 0 101.25 107.3864 30 4 0 85.5 90.6818 38 6 0 102.2143 108.4091 53 7 0 86.0625 91.2784 51 8 0 102.6 108.8182 38 5 0 86.4 91.6364 32 5 0 102.9375 109.1761 61 8 0 86.7857 92.0454 45 7 0 103.5 109.7727 46 6 0 87 92.2727 58 9 0 104.1429 110.4545 54 7 0 87.75 93.0682 26 4 0 104.625 110.9659 31 4 0 88.5 93.8636 59 9 0 105.3 111.6818 39 5 0 88.7143 94.0909 46 7 0 105.75 112.1591 47 6 0 89.1 94.5 33 5 0 106.0714 112.5 55 7 0 4-26 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.7 PLL Initialization 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 4-9. GPCLK PLL Programming Table (7 of 7) GPCLK Rate w/ Crystal = 13.50 MHz 14.31818 MHz GPCLK Rate w/ Crystal = M N L 13.50 MHz 14.31818 MHz M N L 89.4375 94.8579 53 8 0 106.3125 112.7557 63 8 0 90 95.4545 40 6 0 108 114.5454 32 4 0 90.6429 96.1364 47 7 0 109.9286 116.5909 57 7 0 91.125 96.6477 27 4 0 110.25 116.9318 49 6 0 91.5 97.0454 61 9 0 110.7 117.4091 41 5 0 91.8 97.3636 34 5 0 111.375 118.125 33 4 0 111.8571 118.6363 58 7 0 118.125 125.2841 35 4 0 112.5 119.3182 50 6 0 118.8 N/A 44 5 0 113.4 120.2727 42 5 0 119.25 N/A 53 6 0 113.7857 120.6818 59 7 0 119.5714 N/A 62 7 0 114.75 121.7045 34 4 0 121.5 N/A 36 4 0 115.7143 122.7273 60 7 0 123.7500 N/A 55 6 0 116.1 123.1363 43 5 0 124.2000 N/A 46 5 0 117 124.0909 52 6 0 124.8750 N/A 37 4 0 117.6429 124.7727 61 7 0 -- -- -- -- L498A_B -- Conexant Preliminary Information/Conexant Proprietary and Confidential 4-27 L498A_B 4.0 Application Information 4.8 Guide to Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 4.8 Guide to Frame Buffer Interface This section clarifies the expected interaction of the Bt497A/8A with its associated frame buffer. Figure 4-4 illustrates the basic hookup. The frame buffer is simplified into its primary components with respect to the Bt497A/8A. RAM chips are expected to be standard or specialized Video RAM (VRAM) components. The control logic handles the major addressing control of the RAM chips. The control logic interacts with all four Bt497A/8A external CRT timing signals. In contrast to previous RAMDAC products from Conexant, the Bt497A/8A has an on-chip CRT timing generator. Thus, the Bt497A/8A generates its own internal syncing and blanking controls for modulation of the analog RGB outputs, as illustrated in Figure 4-4. However, the frame buffer control logic needs some indication of expected timing events in relation to the displayed screen. The Bt497A/8A provides a digital CSYNC* pin, but it is not expected to contribute to the task of latching the first pixels after BLANK de-assertion. Figure 4-4. Frame Buffer Interface for Bt497A/8A-Generated VRAM Serial Clock and Pixel Clock RAM Chips 64 or 128 Pixel Data LD SC* SCEN* Control Logic Bt497A/8A (H) (H) STSCAN FIELD DACs IOR IOG IOB CBLANK* CSYNC* 497-8_037 Frame Buffer Control Signals 4-28 The following signals have been previously described in this data sheet. The definitions are repeated here with an emphasis on their frame buffer control aspect. LD-The control input to the Bt497A/8A whose rising edge latches pixel data and internal CRT sync and blank states into the chip data path. SC*-The Bt497A/8A serial clock output. This is the primary timing reference for all frame buffer control. SCEN*-Serial Clock Enable (active low). This chip output, when active, tells the RAM chips to continuously output active video pixel data for potential display. STSCAN-Start-Scan Enable (active high). This chip output alerts the frame buffer control logic, one horizontal retrace in advance, to prepare the next visible scan-line for display. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 4.8 Guide to Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC FIELD-Indicates which field is active for interlaced scanning. This pin is bidirectional in order to synchronize display systems with multiple Bt497A/8A chips. For single RAMDAC systems (and for this discussion) FIELD is an output. Pixel Data-Represents the frame buffer data sent to the Bt497A/8A for display. A single stable occurrence of the pixel data is referred to as a load group. CBLANK*-Composite BLANK, active low. This signal, after pipeline delays, forces the chip DACs to their inactive level, allowing the display monitor to perform retraces. CSYNC*-Composite SYNC, active low. This signal, after pipeline delay, appears on the IOG signal as a special low-current level. It signals the monitor to execute a retrace. The (H) beside the SC* and SCEN* in Figure 4-4 indicates that they are High Drive outputs, which are expected to be connected to multiple inverter buffers. These buffers are indicated as single gates in Figure 4-4, and are required to drive the multiple RAM chips in a high-resolution frame buffer. STSCAN and FIELD are normal drive outputs, whose load in the control logic is expected to be modest. LD is expected to be inverted from SC* and returned to the Bt497A/8A. In Figure 4-5, the inverter delay, shown as [X], is given by AC Timing #14. Further, the delay from SC* falling edge to the stable point of SCEN* is shown as [Y]. That value is Timing #13. (The same value applies as well to the delay for STSCAN and FIELD, from SC*.) Finally, the pixel data must be stable around the rising edge of LD at the Bt497A/8A. For corresponding timings see Input Pixel Timing in the AC Electrical and parameters section. Figure 4-5. Latching of First Pixels After BLANK 1st Displayed Load Group Pixel Data n+1 n n+2 n+3 LD [X] SC* [Y] SCEN* 497-8_038 CBLANK* Typical Usage L498A_B Figure 4-6 illustrates the above-mentioned signals as they might appear in a simple noninterlaced display system. The waveforms show the last four scan lines of a reference frame followed by a vertical retrace, then followed by the first scan line of the next frame. For illustration purposes, the vertical retrace is greatly shortened from that of a true typical monitor. The SCEN* signal is controlled by programming the Horizontal SCEN Assertion Point (HSCENAP) and the Horizontal SCEN Negation Point (HSCENNP) registers. Program these registers so that the SCEN* edges precede the CBLANK* transitions, as illustrated in Figure 4-6. Conexant Preliminary Information/Conexant Proprietary and Confidential 4-29 L498A_B 4.0 Application Information 4.8 Guide to Frame Buffer Interface 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC The STSCAN signal is not controlled by any dedicated registers, as SCEN* is. Instead, STSCAN assertions are a function of two other timings: SCEN* and the separate horizontal and vertical components of CBLANK*, referred to as HBLANK* and VBLANK*, respectively. When STSCAN edges do occur, they are coincident with the values specified for SCEN*. The enable condition for STSCAN pulses is provided indirectly by VBLANK*. Essentially, the first STSCAN pulse of a frame coincides with the HBLANK* event that precedes the first displayed line. The last STSCAN of a frame coincides with the last HBLANK* just before the last displayed line. The FIELD signal transitions at the point labeled VSAP. That point corresponds to the beginning of the vertical sync interval, and is triggered by the VSAP register value. For noninterlaced displays, the FIELD edges may alert the control logic that the Bt497A/8A is between frames, so the logic should anticipate the top of the screen for its next display sequence. For interlaced displays, the level of FIELD indicates that, for FIELD = low, the next (or present) field of scan lines are even, while FIELD = high indicates that the odd field is pending (or present). Depending on the design of the control logic, the STSCAN and FIELD signals may be all that are required as inputs to implement the CRT timing aspect of the logic. The SC* and SCEN* signals (post-buffered) will certainly connect to the RAM chips, but they may be optional as inputs to the control logic. Figure 4-6. CRT Signals at Vertical Scale CSYNC* CBLANK* SCEN* FIELD VSAP Latching The First Pixels 4-30 497-8_039 STSCAN A key question for any frame buffer design with the Bt497A/8A is when to deliver the first pixels to be displayed immediately after the Horizontal Blank transitions to the active-display state. The previous descriptions dealt with indications for the beginning of a screen from the slower vertical context of the first scan lines of a frame. Figure 4-5 illustrates how the Bt497A/8A handles the first displayable data that forms the beginning (left-most, on the screen) pixels of every scan line in a frame. The corresponding pixel data occurrence is referred to as the "first-displayed load group." Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 4.0 Application Information 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 4.8 Guide to Frame Buffer Interface The falling edge of SCEN* is the direct trigger that tells the frame buffer to prepare to output the first load group. Associated with the SCEN* falling edge is the SC* falling edge that released it (SCEN*), and also the load group that is presently stable at that occurrence. That load group is labeled n in Figure 4-5. Typically a frame buffer will take a small number of SC* cycles to produce the first displayed load group after it received the SCEN* assertion. The n+3 load group is intended for first-display. Thus, the SCEN* and CBLANK* (HBLANK* component) signals are programmed to exhibit a frame buffer latency delta of three serial clock periods. When the SC* edge releases the CBLANK* rising edge, the next immediate LD rising edge is assumed to latch both the Blank-is-Off state and the corresponding first-displayed load group. Programming Details L498A_B The values in the HSCENAP and the HSCENNP registers control the SCEN* signal. Furthermore, the Horizontal Blank Negation Point (HBNP) and Horizontal Blank Assertion Point (HBAP) registers determine the Horizontal Blank component of CBLANK*. Normally, users establish the blank and sync timing points first, based on their monitor, or desired screen characteristics. SCEN* is set based on the frame buffer latency value. In Figure 4-5, this latency is three serial clock periods. Assuming the HBLANK* transitions are fixed, the HSCENAP is programmed to make SCEN* transition three serial clocks earlier than the CBLANK* rising edge. Here it is necessary to mention that the three external control signals, SCEN*, STSCAN, and FIELD, have an extra SC*-based pipeline delay with respect to the internal controls: CBLANK* and CSYNC*. This extra pipeline ensures that the external signals are closely synchronized to the SC* clock output. However, it necessitates an adjustment in programming the SCEN* registers. To achieve the 3-cycle frame buffer latency of the example, the HSCENAP register should be programmed to be four less than the HBNP value. In general, if the actual frame buffer latency is `X' number of serial clock periods, then the programmed delta for the SCEN* registers is X+1 periods less than the corresponding HBLANK* value. The effect for HSCENAP has been described: the same X+1 delta is seen between the HSCENNP and HBAP values. The STSCAN and FIELD signals are not timing-critical in the same sense as SCEN*. Therefore, there is no need or concern for programming adjustments to these two signals. Conexant Preliminary Information/Conexant Proprietary and Confidential 4-31 L498A_B 4.0 Application Information 4.8 Guide to Frame Buffer Interface 4-32 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B 5 5.0 Parametric Information 5.1 DC Electrical Parameters Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5-1. Recommended Operating Conditions Parameter Symbol Min Typ Max Units Power Supply, 3.3 V, 5% VAA3 3.14 3.3 3.47 V Power Supply, 5.0 V, 5% VAA5 4.75 5.0 5.25 V Ambient Operating Temperature Ta 0 25 70 C Output Load RL -- 37.5 -- Reference Voltage VREF 1.2 1.235 1.26 V FSADJ Resistor RSET -- 140 -- Junction Temperature @ 100 LFPM Airflow Tjmax -- -- 125 C SDA, SCL Pullup Resistor (1) Rps -- 1000 -- Drawings Pullup Resistor (1) Rpd -- 1000 -- (1) Pullup resistors must be terminated at +5 V supply. L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 5-1 L498A_B 5.0 Parametric Information 5.1 DC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 5-2. Absolute Maximum Ratings Parameter Symbol Min Typ Max Units VAA3 (measured to GND) -- -- -- 5 V VAA5 (measured to GND) -- -- -- 7 V Voltage on any Signal Pin (1) -- GND -0.5 -- VAA+0.5 V Analog Output Short Circuit Duration to any Power Supply or Common ISC 0 Indefinite -- -- Storage Temperature TS -65 -- +125 C Junction Temperature TJ -- -- +150 C TSOL -- -- 260 C TVSOL -- -- 220 C SDL, SDA Pullup Resistor(2) Rps 600 -- -- W Drawing b Pullup Resistor(2) Rpd 120 -- -- W Soldering Temperature (5 seconds, 1/4" from pin) Vapor Phase Soldering (1 minute) (1) This device employs a high-impedance CMOS device on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. (2) Pullup resistors must be terminated at +5 V supply. Table 5-3. DC Characteristics (1 of 3) Parameter Analog Outputs Resolution (each DAC) Accuracy (each DAC) Integral Linearity Error Differential Linearity Error Gray-Scale Error Monotonicity Coding Symbol Min Typ Max Units 8 8 8 Bits 1 1 5 LSB LSB % Gray Scale IL DL Guaranteed Binary Digital Inputs (except CLOCK and CLOCK*) -- -- -- -- -- Input High Voltage (non Field) VIH 2 -- VAA3 + 0.5 V Input High Voltage (Field pin) VIH 2 -- VAA5 + 0.5 V Input Low Voltage VIL GND -- 0.8 V Vhys -- 0.3 -- V Input High Current (Vin = 2.4 V) IIH -- -- 1 A Input Low Current (Vin = 0.4 V) IIL -- -- -1 A Input Capacitance (f = 1 MHz, Vin = 2.4 V) CIN -- 7 -- pF -- -- -- -- -- Input High Voltage VIH 2 -- VAA3 + 0.5 V Input Low Voltage VIL GND -- 0.8 V Hysteresis (Field pin) Digital Inputs with Internal Pullups (Pixel Inputs and JTAG Pins) 5-2 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 5.0 Parametric Information 5.1 DC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 5-3. DC Characteristics (2 of 3) Parameter Symbol Min Typ Max Units Input High Current (Vin = 2.4 V) IIH -- -- 60 A Input Low Current (Vin = 0.4 V) IIL -- -- -60 A Input Capacitance (f = 1 MHz, Vin = 2.4 V) CIN -- 7 -- pF -- -- -- -- -- Differential Input Voltage VIN 0.6 -- -- V Input High Voltage VKIH 4 -- VAA5 + 0.5 V Input Low Voltage VKIL GND -0.5 -- 3.4 V Input High Current (Vin = 4.0 V) IKIH -- -- 5 A Input Low Current (Vin = 0.4 V) IKIL -- -- -5 A Input Capacitance (f = 1 MHz, Vin = 4.0 V) CKIN -- 7 -- pF -- -- -- -- -- Input High Voltage VIH 3.0 -- VAA5 + 0.5 V Input Low Voltage VIL -0.5 -- 1.5 V Vhys -- 0.3 -- V Ii -30 -- 30 A Output Low Voltage (Iol = 40 mA Drawing* pin) Vol -- -- 0.4 V Output Low Voltage (Iol = 8 mA SDL, SDA pin) Vol -- -- 0.4 V Capacitance Ci -- 7 10 pF Digital Outputs (D[7:0], FIELD, STSCAN, TDO, CSYNC*, VSYNC*) -- -- -- -- -- Output High Voltage (Ioh = -6.4 mA, non Field) Voh 2.4 -- VAA3 V Output Low Voltage (Iol = 6.4 mA, non Field) Vol GND -- 0.4 V Output High Voltage (Ioh = -20 mA, Field pin) Voh 2.4 -- VAA3 V Output Low Voltage (Iol = 20 mA, Field pin) Vol GND -- 0.4 V Three-state Current Ioz -- -- 10 A Load Capacitance(1) Co -- -- 20 pF Digital Outputs (SC*, SCEN*, GPCLK) -- -- -- -- -- Output High Current (Voh = 2.4 V) Ioh -- -- -16 mA Output Low Current (Vol = 0.4 V) Iol -- 12 mA Load Capacitance (SC*, SCEN*)(1) Co -- -- 30 pF Load Capacitance (GPCLK)(1) Co -- -- 10 pF Analog Outputs -- -- -- -- -- Output Current -- -- -- -- -- Pixel Clock Inputs (CLOCK and CLOCK*) Open Drain Pins (SDA, SCL, DRAWING*) Hysteresis Input Current L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 5-3 L498A_B 5.0 Parametric Information 5.1 DC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 5-3. DC Characteristics (3 of 3) Parameter Symbol Min Typ Max Units White Level Relative to Blank -- 17.69 19.05 20.40 mA White Level Relative to Black -- 16.74 17.62 18.50 mA Black Level Relative to Blank -- 0.95 1.44 1.90 mA Blank Level on IOR, IOB -- 0 5 50 A Blank Level on IOG -- 6.29 7.62 8.96 mA Sync Level on IOG -- 0 5 50 A LSB Size -- -- 69.1 -- A DAC-to-DAC Matching -- -- 2 5 % Output Compliance VOC -0.40 -- +1.2 V Output Impedance RAOUT -- 50 -- k Output Capacitance (f = 1 MHz, IOUT = 0 mA) CAOUT -- 13 20 pF Voltage Reference Input Current IREF -- 100 -- A Power Supply Rejection Ratio (COMP = 0.1 F, f = 1 kHz) PSRR -- 0.5 -- %/% VAA (1) 5-4 Includes board wiring and capacitance at buffer input. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 5.0 Parametric Information 5.2 AC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 5.2 AC Electrical Parameters Table 5-4. Analog Output Timing Parameter Symbol 160 MHz Devices (Bt497A) Min Typ -- 20 1.5 3.5 -28 50 0 Analog Output Delay (1) Analog Output Rise/Fall Analog Output Settling (2) Clock/Data Feedthrough (3) Glitch Impulse (4) Analog Output Skew (5) -- Pipeline Delay -- -- VAA Supply Current IAA3 (6) IAA5 (6) IAA3 (7) IAA5 (7) IAA3 (8) IAA5 (8) -- -- 240 MHz Devices (Bt498A) Max Min Typ -- 20 1.5 3.5 -28 50 0 1 ns ns ns dB pV-sec ns -- 17 Clocks 21 735 21 602 mA mA mA mA mA mA 1 17 Units -- Max -- 39 706 37 630 37 610 20 601 (1) Referenced to ECL clock inputs. Output settling time measured from 50% point of full-scale transition to output settling within 1 LSB. (3) Clock and data feedthrough are functions of the amount of edge rates, overshoot, and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 k resistor to GND and are driven by 74 HC logic. Settling time does not include clock and data feedthrough. (4) Glitch impulse includes clock and data feedthrough, -3 dB test bandwidth = 2x clock rate. (5) Output delay time measured from 50% point of the rising clock edge to 50% point of full-scale transition. (6) VAA3 = 3.47 V, VAA5 = 5.25 V, 0 C, at maximum frequency specified. Pixel pattern alternates one full white pixel (logical ones) and one full black pixel (logical zeros). (7) VAA3 = 3.47 V, VAA5 = 5.25 V, 70 C, at maximum frequency specified. Pixel pattern alternates four full white pixels (logical ones) and four full black pixels (logical zeros). (8) VAA3 = 3.30 V, VAA5 = 5.00 V, 25 C, at maximum frequency specified. Pixel pattern alternates four full white pixels (logical ones) and four full black pixels (logical zeros). 9. Worst case pixel patterns may require additional air flow to maintain the junction temperature within its recommended operating limits. 10. Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 140 , VREF = 1.235 V. TTL input values are 0-3 V, with input rise/fall times 3 ns, measured between the 10% and 90% points. ECL input values are VAA5 - 0.8 to VAA5 - 1.8 V, with input rise/fall times 2 ns, measured between the 20% and 80% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF, D[7:0] output load 75 pF. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. (2) L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 5-5 L498A_B 5.0 Parametric Information 5.2 AC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 5-1. Video Output Timing 18 20 IOR, IOG, IOB 19 12 13 497-8_040 CLOCK 14 NOTE(S): 1. Output delay time is measured from the 50% point of the rising clock edge to the 50% point of full-scale transition. 2. Output settling time is measured from the 50% point of full-scale transition to output settling within 1 LSB for the Bt497A/8A. 3. Output rise/fall time is measured between the 10% and 90% points of full-scale transition. Table 5-5. PLL Clock Generation Timing Parameters Parameter Symbol Min Typ Max Units Crystal/Oscillator Frequency -- 10 14.318 24 MHz Pixel PLL VCO Multiplicand MP 24 -- 80 -- Pixel PLL VCO Divisor NP 4 -- 12 -- Pixel PLL M/N Generated Pixel Clock Rate -- 60 -- 240 MHz GPCLK PLL VCO Multiplicand MG 21 -- 63 -- GPCLK PLL VCO Divisor NG 4 -- 15 -- GPCLK M/N Generated Clock Rate -- 11 -- 120 MHz Both PLL M/N Generated Clock Accuracy -- -- 99 -- % Both PLL M/N Generated Clock Jitter -- -- 200 -- ps RESET* Active Pulse Width -- 10 -- -- ns CE* Rise to New SC*/Pixel Clock Rate or GPCLK Rate -- -- 3.75 -- ms NOTE(S): Parameters apply to predivided (i.e., before applying 1/L) pixel clock generation. For frequencies below 100 MHz, it is recommended that L 2. 5-6 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 5.0 Parametric Information 5.2 AC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 5-6. MPU Port Timing Parameter 160 MHz Devices (Bt497A) Symbol 240 MHz Devices (Bt498A) Min Typ Max Min Typ Max -- 0 15 -- -- 55 25 7 -- R/W, C0, C1, LB* Setup R/W, C0, C1, LB* Hold 1 2 0 15 -- CE* Low Time CE* High Time CE* to Data Driven CE* to Data Valid CE* to Data Three-stated 4 5 6 7 8 55 25 7 -- Write Data Setup Time Write Data Hold Time 9 10 10 5 55 19 -- Units ns ns ns ns ns ns ns 55 19 -- 10 5 -- -- ns ns Figure 5-2. MPU Read/Write Timing R/W, C[1,0], LB* VALID 1 VALID 2 4 5 CE* 8 7 6 D[7:0] (READ) Data In (R/W = 0) 9 L498A_B 10 Conexant Preliminary Information/Conexant Proprietary and Confidential 497-8_041 D[7:0] (WRITE) Data Out (R/W = 1) 5-7 L498A_B 5.0 Parametric Information 5.2 AC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Table 5-7. Serial Clock Timing Parameter 160 MHz Devices (Bt497A) Symbol SC* Cycle Time 2:1 and 4/2:1 formats 4:1 and 8/2:1 formats SC* Pulse High Duty Cycle SC* to SCEN*/STSCAN/FIELD 240 MHz Devices (Bt498A) Min Typ Max Min 12.5 N/A 45 0 N/A 50 N/A 55 5 12.5 16.7 45 0 Typ Units Max 11 12 13 50 55 5 ns ns % ns NOTE(S): SC* duty cycle measured at Vth = 1.65 V, at Co 30 pF. Table 5-8. Pixel and LD Timing Parameter Symbol SC* to LD Delay Pixel and Control Setup Pixel and Control Hold 14 15 16 LD Cycle Time 2:1 and 4/2:1 formats 4:1 and 8/2:1 formats LD Pulse Width (high or low) 2:1 and 4/2:1 formats 4:1 and 8/2:1 formats 17 5-8 18 160 MHz Devices (Bt497A) 240 MHz Devices (Bt498A) Min Typ Max Min Typ Max 1 3 2 -- 8 1 3 2 -- 8 -- -- -- -- Units ns ns ns 12.5 12.5 16.7 ns ns 5.7 5.7 7.6 ns ns Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 5.0 Parametric Information 5.2 AC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 5-3. Input Pixel Timing 11 12 SC* 13 SCEN*, STSCAN, FIELD (Valid) 17 14 18 18 LD 15 16 497-8_042 Pixel Data Table 5-9. JTAG Timing Parameter 160 MHz Devices (Bt497A) Symbol Min Typ Max Min Typ Max -- 8 6 -- -- 20 20 1 -- TMS, TDI Setup Time TMS, TDI Hold Time 19 20 8 6 -- TCK Low Time TCK High Time TCK Asserted to TDO Driven TCK Asserted to TDO Valid TCK Negated to TDO three-stated 21 22 23 24 25 20 20 1 -- L498A_B 240 MHz Devices (Bt498A) 20 20 Conexant Preliminary Information/Conexant Proprietary and Confidential 20 20 Units ns ns ns ns ns ns ns 5-9 L498A_B 5.0 Parametric Information 5.2 AC Electrical Parameters 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 5-4. JTAG Timing 19 TDI, TMS TCK 20 Valid 21 22 24 25 23 TDO 497-8_043 Valid and Driving Table 5-10. Input Clock Parameter Symbol 160 MHz Devices (Bt497A) Min Clock Rate Clock Cycle Time Clock Pulse Width High Clock Pulse Width Low Fmax 26 27 28 Typ Max -- 160 6.25 2.8 2.8 240 MHz Devices (Bt498A) Units Min Typ Max -- 240 4.167 ns 2 2 MHz ns ns ns Figure 5-5. ECL Clock Input (PLL Bypassed) 26 27 28 497-8_044 CLOCK 5-10 Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 5.0 Parametric Information 5.3 Package Information 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC 5.3 Package Information Table 5-11. Package Thermal Resistance Airflow (Linear Feet Per Minute) Package Units 0 50 100 200 400 160-Pin Quad Flat Pack 21 19 17 16 14 C/W 208-Pin Quad Flat Pack 22 20 18 16 14 C/W Figure 5-6. 160-Pin Metric Quad Flatpack (MQFP) TOP VIEW PIN 1 BOTTOM VIEW D1 D b E E1 e A A2 A1 L498A_B L 1.95 REF. (.077) A A1 A2 D D1 E E1 L e b ALL DIMENSIONS IN MILLIMETERS MIN. NOM. ---0.25 3.17 31.65 27.90 31.65 27.90 0.65 ------3.42 31.90 28.00 31.90 28.00 ---0.65 BSC. 0.22 ---- Conexant Preliminary Information/Conexant Proprietary and Confidential MAX. 4.07 ---3.67 32.15 28.10 32.15 28.10 0.95 0.38 497-8_045 S Y M B O L 5-11 L498A_B 5.0 Parametric Information 5.4 Revision History 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Figure 5-7. 208-Pin Metric Quad Flatpack (MQFP) TOP VIEW BOTTOM VIEW D D3 PIN #1 D1 b E E3 E1 e A A2 L A1 1.30 REF. (.051) A A1 A2 D D1 D3 E E1 E3 L e b ALL DIMENSIONS IN MILLIMETERS MIN. NOM. ---0.25 3.20 ------3.40 30.60 BSC. 28.00 BSC. 25.50 REF. 30.60 BSC. 28.00 BSC. 25.50 REF. 0.50 0.60 0.50 BSC. 0.17 ---- MAX. 4.10 ---3.60 0.75 0.27 497-8_046 S Y M B O L 5.4 Revision History Revision 5-12 Comments A Initial Release. B 1. Table 5-4, Analog Output Timing updated. 2. Minor editorial corrections. Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B L498A_B 5.0 Parametric Information 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC L498A_B Conexant Preliminary Information/Conexant Proprietary and Confidential 5.4 Revision History 5-13 L498A_B 5.0 Parametric Information 5.4 Revision History 5-14 240 MHz Monolithic CMOS Triple 1K x 8 RAMDAC Conexant Preliminary Information/Conexant Proprietary and Confidential L498A_B 0.0 Sales Offices Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com World Headquarters Conexant Systems, Inc. 4311 Jamboree Road P. O. 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