0.035
[0.9]
0.035
[0.9]
0.039
[1.0]
0.083
[2.1]
0.035
[0.9]
0.035
[0.9]
0.014
[0.35]
0.039
[1.0]
0.020
[0.50]
0.033 ±0.002
0.85 ±0.05
0.126 ±0.002
3.20 ±0.05
0.098 ±0.002
2.50 ±0.05
456
1 2 3
0.9[.035] REF
0.028 ±0.002
0.7 ±0.05
0.004
0.1
REF
0.035 ±0.002
0.90 ±0.050
0.020 ±0.002
0.50 ±0.05
0.041
1.05
45
6
13
2
Recommended Land Pattern for LVPECL, LVDS, HCSL
Note: Recommend using an approximately
0.01uF bypass capacitor between PIN 6 and 3.
Via to Power Layer
Via to GND
Layer
Recommended Land Pattern FOR CMOS
*
1
65
23
4
Pin
Function
1
Tri-state
2
NC
3
GND
4
Output
5
NC (CMOS)
Output (LVPECL, LVDS,
HCSL)
6
Vdd
-
ASEMP
XXXXXX
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TITLE:
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MATERIAL:
DATE
SIGNATURE
NAME
DEBUR AND
BREAK SHARP
EDGES
FINISH:
UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE IN INCH(MM)
SURFACE FINISH:
TOLERANCES:
LINEAR:
ANGULAR:
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