935291857551 - NXP SEMICONDUCTORS

1. General description

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications

requiring a high level of integration and low power dissipation.

The ARM Cortex-M3 is a next generation core that offers better performance than the

ARM7 at the same clock rate and other system enhancements such as mode rnized

debug features and a higher level of support block integration. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and has a Harvard architecture with separate local

instruction and data buses, as well as a third bus with slightly lower performance for

peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that

supports speculative branches.

The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal

performance when executing cod e from flash. The LPC178x/7x operates at up to

120 MHz CPU frequency.

The peripheral complement of the LPC178x/7x includes up to 512 kB of flash prog r am

memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,

External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB

Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,

three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers,

two general purpose PWMs with six outputs each and one motor control PWM, an

ultra-low power RTC with separate battery supply and event recorder, a windowed

watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more.

The analog peripherals include one eight-channel 12-bit ADC and a 10-bit DAC.

The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx

and LPC23xx.

For additional documentation, see Section 18 “References”.

2. Features and benefits

Functional replacement for the LPC23xx an d LPC24xx family devices.

System:

ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory

Protection Unit (MPU) supporting eight regions is included.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and

96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC

Rev. 5.5 — 26 April 2016 Product data sheet

Product data sheet Rev. 5.5 — 26 April 2016 2 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, USB, Ethernet, and the General Purpose DMA

controller. This interconnect provides communication with no arbitration delays

unless two masters attempt to access the same slave at the same time.

Split APB bus allows for higher throughput with fewer stalls between the CPU and

DMA. A single level of write buffering allows the CPU to continue without waiting for

completion of APB writes if the APB was not already busy.

Cortex-M3 system tick timer, including an external clock input option.

Standard JTAG test/debug interface as well as Serial Wire Debug and Serial

WireTrace Port options.

Embedded Trace Macrocell (ETM) module supports real-time trace.

Boundary scan for simplified board testing.

Non-maskable Interrupt (NM I) inpu t.

Memory:

Up to 512 kB on-chip flash program memory with In-System Programming (ISP)

and In-Application Programming (IAP) capabilities. The combination of an

enhanced flash memory accelerator and location of the flash memory on the CPU

local code/dat a bus provides high code performance from flash.

Up to 96 kB on-chip SRAM includes:

64 kB of main SRAM on the CPU with local code/data bus for high-performance

CPU access.

Two 16 kB peripheral SRAM blocks with separate access paths for higher

throughput. These SRAM blocks may be used for DMA memory as well as for

general purpose instruction and data storage.

Up to 4032 byte on-chip EEPROM.

LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film

Tr ansistors (TFT) displays.

Dedicated DMA control ler.

Selectable display resolution (up to 1024 768 pixels).

Supports up to 24-bit true-color mode.

External Memory Controller (EMC) provides support for asynchronous static memory

devices such as RAM, ROM and flash, as well as dynamic memories such as single

data rate SDRAM with an SDRAM clock of up to 80 MHz.

Eight channel General Purpose DMA controller (GPDMA) on the AHB multila yer

matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, GPIO, and for

memory-to-memory transfers.

Serial interfaces:

Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and

associated DMA controller.

Five UARTs with fractional baud rate generation, internal FIFO, DMA sup port, and

RS-485/EIA-485 suppo rt. One UART ( UART1) has full modem contro l I/O, and one

UART (USART4) supports IrDA, synchronous mode, an d a sm ar t car d mod e

conforming to ISO7816-3.

Three SSP controllers with FIFO and multi-protocol capabilities. The SSP

controllers can be used with the GPDMA.

Product data sheet Rev. 5.5 — 26 April 2016 3 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Three enhanced I2C-bus interfaces, one with a true open-drain output supporting

the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two

with standard port pins. Enhancements include multiple address recognition and

monitor mode.

I2S-bus (Inter-IC Sound) interface for digital audio input or output. It can be used

with the GPDMA.

CAN controller with two channels.

Digital peripherals:

SD/MMC memory card interface.

Up to 165 General Purpose I/O (GPIO) pins depending on the packaging with

configurable pull-up/down resistors, open-drain mode, and repeater mode. All

GPIOs are located on an AHB bus for fast access and support Cortex-M3

bit-banding. GPIOs can be accessed by the General Purpos e DMA Controller. Any

pin of ports 0 and 2 can be used to generate an interrupt.

Two external interrupt input s configura ble as edge/level se nsitive. All pins on p ort 0

and port 2 can be used as edge sensitive interrupt sources.

Four general purpose timers/counters with a total of eight captur e inputs and ten

compare outputs. Each time r block has an external count input. Specific timer

events can be selected to generate DMA requ ests.

Quadrature encoder interface that can monitor one external quad rature encoder.

Two standard PWM/timer blocks with external count input option.

One motor control PWM with support for three-phase motor control.

Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a

dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered

backup registers, allowing system status to be stored when the rest of the chip is

powered of f. Battery power can be supplied from a sta ndard 3 V lithium bu tton cell.

The RTC will continue working when the battery voltage drops to as low as 2.1 V.

An RTC interrupt can wake up the CPU from any reduced power mode.

Event Recorder that can capture the clock value when an event occurs on any of

three inputs. The event identification and the time it occurred are stored in

registers. The Event Recorder is located in the RTC power domain and can

therefore operate as long as there is RTC power.

Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal

oscillator, watchdog warning interrupt, and safety features.

CRC Engine block can calculate a CRC on supplied data using one of three

standard polynomials. The CRC engine can be used in conjunction with the DMA

controller to generate a CRC without CPU involvement in the data transfer.

Analog peripherals:

12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,

conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can

be used with the GPDMA controller.

10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and

GPDMA support.

Power control:

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

Product data sheet Rev. 5.5 — 26 April 2016 4 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up

from any priority interrupt that can occur while the clocks are stopped in

Deep-sleep, Power-down , an d De ep pow er -d ow n mo d es .

Processor wake-up from Power-down mode via any interrupt able to operate

during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2

pin interrupt, and NMI).

Brownout detect with separate threshold for interrupt and forced reset.

On-chip Power -On Reset (POR).

Clock generation :

Clock output function that can reflect the main oscillator clock, IRC clock, RTC

clock, CPU clock, USB clock, or the watchdog timer clock.

On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be

used as a system clock.

An on-chip PLL allows CPU operation up to the maximum CPU rate without the

need for a high-frequency crystal. May be run from the main oscillator or the

internal RC oscillator.

A second, dedicated PLL may be used for USB interface in order to allow added

flexibility for the Main PLL settings.

Versatile pin function selection feature allows many possibilities for using on-chip

periphera l functions.

Unique device serial number for identification purposes.

Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C.

Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package.

3. Applications

Communications:

Point-of-sale te rminals, web servers, multi-protocol bridges

Industrial/Medical:

Automation controllers, applicati on contro l, ro botics control, HVAC, PLC, inverters,

circuit breakers, medical scanning, security monitoring, motor drive, video intercom

Consumer/Appliance:

Audio, MP3 decoders, alarm systems, displays, printers, scanners, small

appliances, fitness equipment

Automotive:

After-market, car alarms, GPS/fleet monitors

Product data sheet Rev. 5.5 — 26 April 2016 5 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC1788

LPC1788FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body

15 ´ 15 ´ 0.7 mm SOT950-1

LPC1788FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC1788FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC1787

LPC1787FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1786

LPC1786FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1785

LPC1785FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1778

LPC1778FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1778FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body

15 ´ 15 ´ 0.7 mm SOT950-1

LPC1778FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC1778FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

LPC1777

LPC1777FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1776

LPC1776FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1776FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC1774

LPC1774FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC1774FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1

Product data sheet Rev. 5.5 — 26 April 2016 6 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Maximum data bus width of the External Memory Controller (EMC) depends on package size. Smaller widths may be used.

[2] USART4 not available.

Table 2. LPC178x/7x ordering options

All parts include two CAN channels, three SSP interfaces, three I2C interfaces, one I2S interface, DAC, and an 8-channel

12-bit ADC.

Type number

Device order

pa rt number

Flash

(kB)

Main SRAM

(kB)

Peripheral

SRAM (kB)

Total SRAM

(kB)

EEPROM

(byte)

Ethernet

USB

UART

EMC bus

wid th (bit) [1]

GPIO

LCD

QEI

SD/

MMC

LPC178x

LPC1788FBD208 LPC1788FBD208/CP3E 512 64 16  2 96 4032 Y H/O/D 5 32 165 Y Y Y

LPC1788FET208 LPC1788FET208,551 512 64 16  2 96 4032 Y H/O/D 5 32 165 Y Y Y

LPC1788FET180 LPC1788FET180,551 512 64 16  2 96 4032 Y H/O/D 5 16 141 Y Y Y

LPC1788FBD144 LPC1788FBD144,551 512 64 16  2 96 4032 Y H/O/D 5 8 109 Y Y Y

LPC1787FBD208 LPC1787FBD208,551 512 64 16  2 96 4032 N H/O/D 5 32 165 Y Y Y

LPC1786FBD208 LPC1786FBD208,551 256 64 16 80 4032 Y H/O/D 5 32 165 Y Y Y

LPC1785FBD208 LPC1785FBD208K 256 64 16 80 4032 N H/O/D 5 32 165 Y N Y

LPC177x

LPC1778FBD208 LPC1778FBD208,551 512 64 16  2 96 4032 Y H/O/D 5 32 165 N Y Y

LPC1778FET208 LPC1778FET208,551 512 64 16  2 96 4032 Y H/O/D 5 32 165 N Y Y

LPC1778FET180 LPC1778FET180,551 512 64 16  2 96 4032 Y H/O/D 5 16 141 N Y Y

LPC1778FBD144 LPC1778FBD144,551 512 64 16  2 96 4032 Y H/O/D 5 8 109 N Y Y

LPC1777FBD208 LPC1777FBD208,551 512 64 16  2 96 4032 N H/O/D 5 32 165 N Y Y

LPC1776FBD208 LPC1776FBD208,551 256 64 16 80 4032 Y H/O/D 5 32 165 N Y Y

LPC1776FET180 LPC1776FET180,551 256 64 16 80 4032 Y H/O/D 5 16 141 N Y Y

LPC1774FBD208 LPC1774FBD208,551 128 32 8 40 2048 N D 5 32 165 N N N

LPC1774FBD144 LPC1774FBD144,551 128 32 8 40 2048 N D 4[2] 8 109 N N N

Product data sheet Rev. 5.5 — 26 April 2016 7 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

5. Block diagram

(1) Not available on all parts. See Table 2.

Fig 1. Block diagram

SRAM

96/80/40 kB

ARM

CORTEX-M3

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

FLASH

ACCELERATOR

FLASH

512/256/128/64 kB

GPDMA

CONTROLLER

I-code

bus

D-code

bus

system

bus

AHB TO

APB

BRIDGE 0

HIGH-SPEED

GPIO AHB TO

APB

BRIDGE 1

4032 B/

2048 B

EEPROM

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

clocks and

controls

JTAG

interface

debug

port

SSP0/2

USART4(1)

UART2/3

SYSTEM CONTROL

SSP1

UART0/1

I2C0/1

CAN 0/1

TIMER 0/1

WINDOWED WDT

12-bit ADC

PWM0/1

PIN CONNECT

GPIO INTERRUPT CONTROL

RTC

BACKUP REGISTERS

EVENT RECORDER

32 kHz

OSCILLATOR

APB slave group 1

APB slave group 0

RTC POWER DOMAIN

LPC178x/7x

master

ETHERNET(1)

master

USB

DEVICE/

HOST(1)/OTG(1)

master

002aaf528

slave

CRC

slave slave slave

slave

ROM

EMC

slaveslave

LCD(1)

slave

MULTILAYER AHB MATRIX

I2C2

TIMER2/3

DAC

I2S

QUADRATURE ENCODER(1)

MOTOR CONTROL PWM

MPU

SD/MMC(1)

= connected to GPDMA

Product data sheet Rev. 5.5 — 26 April 2016 8 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

6. Pinning information

6.1 Pinning

Fig 2. Pin configuration (LQ FP2 0 8)

Fig 3. Pin configuration (TF BGA2 08 )

LPC178x/7xFBD208

156

104

208

157

105

002aaf518

002aaf529

LPC178x/7x

Transparent top view

ball A1

index area

24681012

131415 17

1357911

Product data sheet Rev. 5.5 — 26 April 2016 9 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

6.2 Pin description

I/O pins on the LPC178x/7x are 5 V tolerant and have input hyste re sis un le ss othe rwis e

indicated in the table below. Crystal pins, power pins, and refere n ce vo ltage pins ar e no t

5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longe r 5 V

tolerant and the input volt a ge must be limited to the volt a ge at the ADC positive re ference

pin (VREFP).

All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 in the

order defined by the FUNC bits of the corresponding IOCON register up to the highest

used function number. Each port pin can support up to eight multiplexed functions.

IOCON register FUNC values which are reserved are note d as ‘ R’ in the p in configur ation

table.

Fig 4. Pin configuration (TF BGA1 80 )

Fig 5. Pin configuration (LQ FP1 4 4)

002aaf519

LPC178x/7x

2 4 6 8 10 12 13 141357911

ball A1

index area

Transparent top view

LPC178x/7x

108

144

109

002aaf520

Product data sheet Rev. 5.5 — 26 April 2016 10 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 3. Pin description

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

P0[0] to

P0[31] I/O Port 0: Port 0 is a 32-bit I/O po rt with individual direction

controls for each bit. The operation of port 0 pins depends upon

the pin function selected via the pin connect block.

P0[0] 94 U15 M10 66 [3] I;

PU I/O P0[0] — General purpose digital input/outp ut pin.

ICAN_RD1 — CAN1 receiver input.

OU3_TXD — Transmitter output for UART3.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

OU0_TXD — Transmitter output for UART0.

P0[1] 96 T14 N11 67 [3] I;

PU I/O P0[1] — General purpose digital input/outp ut pin.

OCAN_TD1 — CAN1 transmitter output.

IU3_RXD — Receiver input for UART3.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

IU0_RXD — Receiver input for UART0.

P0[2] 202 C4 D5 141 [3] I;

PU I/O P0[2] — General purpose digital input/outp ut pin.

OU0_TXD — Transmitter output for UART0.

OU3_TXD — Transmitter output for UART3.

P0[3] 204 D6 A3 142 [3] I;

PU I/O P0[3] — General purpose digital input/outp ut pin.

IU0_RXD — Receiver input for UART0.

IU3_RXD — Receiver input for UART3.

P0[4] 168 B12 A11 116 [3] I;

PU I/O P0[4] — General purpose digital input/outp ut pin.

I/O I2S_RX_SCK — I2S Receive clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in the

I2S-bus specification.

ICAN_RD2 — CAN2 receiver input.

IT2_CAP0 — Capture input for Timer 2, channel 0.

-R — Function reserved.

OLCD_VD[0] — LCD data.

Product data sheet Rev. 5.5 — 26 April 2016 11 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P0[5] 166 C12 B11 115 [3] I;

PU I/O P0[5] — General purpose digital input/outp ut pin.

I/O I2S_RX_WS — I2S Receive word select. It is driven by the

master and received by the slave. Corresponds to the signal WS

in the I2S-bus specification.

OCAN_TD2 — CAN2 transmitter output.

IT2_CAP1 — Capture input for Timer 2, channel 1.

-R — Function reserved.

OLCD_VD[1] — LCD data.

P0[6] 164 D13 D11 113 [3] I;

PU I/O P0[6] — General purpose digital input/outp ut pin.

I/O I2S_RX_SDA — I2S Receive data. It is driven by the transmitter

and read by the receiver. Correspo nds to the signal SD in the

I2S-bus specification.

I/O SSP1_SSEL — Slave Select for SSP1.

OT2_MAT0 — Match output for Timer 2, channel 0.

OU1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

-R — Function reserved.

OLCD_VD[8] — LCD data.

P0[7] 162 C13 B12 112 [4] I; IA I/O P0[7] — General purpose digital input/output pin.

I/O I2S_TX_SCK — I2S transmit clock. It is driven by the master

and received by the slave. Corresponds to the signal SCK in the

I2S-bus specification.

I/O SSP1_SCK — Serial Clock for SSP1.

OT2_MAT1 — Match output for Timer 2, channel 1.

IRTC_EV0 — Event input 0 to Event Monitor/Recorder.

-R — Function reserved.

OLCD_VD[9] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 12 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P0[8] 160 A15 C12 111 [4] I; IA I/O P0[8] — General purpose digital input/output pin.

I/O I2S_TX_WS — I2S Transmit word sel ect. It is driven by the

master and received by the slave. Corresponds to the signal WS

in the I2S-bus specification.

I/O SSP1_MISO — Master In Slave Out for SSP1.

OT2_MAT2 — Match output for Timer 2, channel 2.

IRTC_EV1 — Event input 1 to Event Monitor/Recorder.

-R — Function reserved.

OLCD_VD[16] — LCD data.

P0[9] 158 C14 A13 109 [4] I; IA I/O P0[9] — General purpose digital input/outp ut pin.

I/O I2S_TX_SDA — I2S transmit data. It is driven by the t ransm itter

and read by the receiver. Correspo nds to the signal SD in the

I2S-bus specification.

I/O SSP1_MOSI — Master Out Slave In for SSP1.

OT2_MAT3 — Match output for Timer 2, channel 3.

IRTC_EV2 — Event input 2 to Event Monitor/Recorder.

-R — Function reserved.

OLCD_VD[17] — LCD data.

P0[10] 98 T15 L10 69 [3] I;

PU I/O P0[10] — General purpose digital input/output pin.

OU2_TXD — Transmitter output for UART2.

I/O I2C2_SDA — I2C2 data input/output (this pin does not use a

specialized I2C pad).

OT3_MAT0 — Match output for Timer 3, channel 0.

P0[11] 100 R14 P12 70 [3] I;

PU I/O P0[11] — General pu rpose digital input/output pin.

IU2_RXD — Receiver input for UART2.

I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a

specialized I2C pad).

OT3_MAT1 — Match output for Timer 3, channel 1.

P0[12] 41 R1 J4 29 [5] I;

PU I/O P0[12] — General purpose digital input/output pin.

OUSB_PPWR2 — Port Power enable signal for USB port 2.

I/O SSP1_MISO — Master In Slave Out for SSP1.

IADC0_IN[6] — A/D converter 0, input 6. When configured as an

ADC input, the digital function of the pin must be disabled.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 13 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P0[13] 45 R2 J5 32 [5] I;

PU I/O P0[13] — General purpose digital input/output pin.

OUSB_UP_LED2 — USB port 2 GoodLink LED indicator. It is

LOW when the device is configured (non-control endpoints

enabled), or when the host is enabled and has detected a

device on the bus. It is HIGH when the device is not configured,

or when host is enabled and has not detected a device on the

bus, or during global suspend. It transi tions between LOW and

HIGH (flashes) when the host is enabled and detects activity on

the bus.

I/O SSP1_MOSI — Master Out Slave In for SSP1.

IADC0_IN[7] — A/D converter 0, input 7. When configured as an

ADC input, the digital function of the pin must be disabled.

P0[14] 69 T7 M5 48 [3] I;

PU I/O P0[14] — General purpose digital input/output pin.

OUSB_HSTEN2 — Host Enabled status for USB port 2.

I/O SSP1_SSEL — Slave Select for SSP1.

OUSB_CONNECT2 — SoftConnect control for USB port 2.

Signal used to switch an external 1.5 k resistor under software

control. Used with the SoftConnect USB feature.

P0[15] 128 J16 H13 89 [3] I;

PU I/O P0[15] — General purpose digital input/output pin.

OU1_TXD — Transmitter output for UART1.

I/O SSP0_SCK — Serial clock for SSP0.

P0[16] 130 J14 H14 90 [3] I;

PU I/O P0[16] — General purpose digital input/output pin.

IU1_RXD — Receiver input for UART1.

I/O SSP0_SSEL — Slave Select for SSP0.

P0[17] 126 K17 J12 87 [3] I;

PU I/O P0[17] — General purpose digital input/output pin.

IU1_CTS — Clear to Send input for UART1.

I/O SSP0_MISO — Master In Slave Out for SSP0.

P0[18] 124 K15 J13 86 [3] I;

PU I/O P0[18] — General purpose digital input/output pin.

IU1_DCD — Data Carrier Detect input for UART1.

I/O SSP0_MOSI — Master Out Slave In for SSP0.

P0[19] 122 L17 J10 85 [3] I;

PU I/O P0[19] — General purpose digital input/output pin.

IU1_DSR — Data Set Ready input for UART1.

OSD_CLK — Clock output line for SD card interface.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 14 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P0[20] 120 M17 K14 83 [3] I;

PU I/O P0[20] — General purpose digital input/output pin.

OU1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal for

UART1.

I/O SD_CMD — Command line for SD card interface.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

P0[21] 118 M16 K11 82 [3] I;

PU I/O P0[21] — General purpose digital input/output pin.

IU1_RI — Ring Indicator inpu t for UART1.

OSD_PWR — Power Supply Enable for external SD card power

supply.

OU4_OE — RS-485/EIA-485 output enable signal for UART4.

ICAN_RD1 — CAN1 receiver input.

I/O U4_SCLK — USART 4 clock input or output in synchronous

mode.

P0[22] 116 N17 L14 80 [6] I;

PU I/O P0[22] — General purpose digital input/output pin.

OU1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

I/O SD_DAT[0] — Data line 0 for SD card interface.

OU4_TXD — Transmitter output for USART4 (input/output in

smart card mode).

OCAN_TD1 — CAN1 transmitter output.

P0[23] 18 H1 F5 13 [5] I;

PU I/O P0[23] — General purpose digital input/output pin.

IADC0_IN[0] — A/D converter 0, input 0. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2S_RX_SCK — Receive Clock. It is driven by th e master and

received by the slave. Corresponds to the signal SCK in the

I2S-bus specification.

IT3_CAP0 — Capture input for Timer 3, channel 0.

P0[24] 16 G2 E1 11 [5] I;

PU I/O P0[24] — General purpose digital input/output pin.

IADC0_IN[1] — A/D converter 0, input 1. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2S_RX_WS — Receive Word Select. It is driven by the master

and received by the slave. Corresp onds to the signal WS in the

I2S-bus specification.

IT3_CAP1 — Capture input for Timer 3, channel 1.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 15 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P0[25] 14 F1 E4 10 [5] I;

PU I/O P0[25] — General purpose digital input/output pin.

IADC0_IN[2] — A/D converter 0, input 2. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2S_RX_SDA — Receive data. It is driven by the transmitter

and read by the receiver. Correspo nds to the signal SD in the

I2S-bus specification.

OU3_TXD — Transmitter output for UART3.

P0[26] 12 E1 D1 8 [7] I;

PU I/O P0[26] — General purpose digital input/output pin.

IADC0_IN[3] — A/D converter 0, input 3. When configured as an

ADC input, the digital function of the pin must be disabled.

ODAC_OUT — D/A converter output. When configured as the

DAC output, the digital function of the pin must be disabled.

IU3_RXD — Receiver input for UART3.

P0[27] 50 T1 L3 35 [8] I I/O P0[27] — General purpose digital input/output pin.

I/O I2C0_SDA — I2C0 data input/output (this pin uses a specialized

I2C pad).

I/O USB_SDA1 — I2C serial data for communication with an

external USB transceiver.

P0[28] 48 R3 M1 34 [8] I I/O P0[28] — General purpose digital input/output pin.

I/O I2C0_SCL — I2C0 clock input/output (this pin uses a

specialized I2C pad).

I/O USB_SCL1 — I2C serial clock for communication with an

external USB transceiver.

P0[29] 61 U4 K5 42 [9] I I/O P0[29] — General purpose digital input/output pin.

I/O USB_D+1 — USB port 1 bidirectional D+ line.

IEINT0 — External interrupt 0 input.

P0[30] 62 R6 N4 43 [9] I I/O P0[30] — General purpose digital input/output pin.

I/O USB_D1 — USB port 1 bidirectional D lin e.

IEINT1 — External interrup t 1 in put.

P0[31] 51 T2 N1 36 [9] I I/O P0[31] — General purpose digital input/output pin.

I/O USB_D+2 — USB port 2 bidirectional D+ line.

P1[0] to

P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon

the pin function selected via the pin connect block

P1[0] 196 A3 B5 136 [3] I;

PU I/O P1[0] — General purpose digital input/outp ut pin.

OENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

-R — Function reserved.

IT3_CAP1 — Capture input for Timer 3, channel 1.

I/O SSP2_SCK — Serial clock for SSP2.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 16 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P1[1] 194 B5 A5 135 [3] I;

PU I/O P1[1] — General purpose digital input/outp ut pin.

OENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

-R — Function reserved.

OT3_MAT3 — Match output for Timer 3, channel 3.

I/O SSP2_MOSI — Master Out Slave In for SSP2.

P1[2] 185 D9 B7 - [3] I;

PU I/O P1[2] — General purpose digital input/outp ut pin.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

OSD_CLK — Clock output line for SD card interface.

OPWM0[1] — Pulse Width Modulator 0, output 1.

P1[3] 177 A10 A9 - [3] I;

PU I/O P1[3] — General purpose digital input/outp ut pin.

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O SD_CMD — Command line for SD card interface.

OPWM0[2] — Pulse Width Modulator 0, output 2.

P1[4] 192 A5 C6 133 [3] I;

PU I/O P1[4] — General purpose digital input/outp ut pin.

OENET_TX_EN — Ethernet transmit data enable (RMII/MII

interface).

-R — Function reserved.

OT3_MAT2 — Match output for Timer 3, channel 2.

I/O SSP2_MISO — Master In Slave Out for SSP2.

P1[5] 156 A17 B13 - [3] I;

PU I/O P1[5] — General purpose digital input/outp ut pin.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

OSD_PWR — Power Supply Enable for external SD card power

supply.

OPWM0[3] — Pulse Width Modulator 0, output 3.

P1[6] 171 B11 B10 - [3] I;

PU I/O P1[6] — General purpose digital input/outp ut pin.

IENET_TX_CLK — Ethernet Transmit Clock (MII interface).

I/O SD_DAT[0] — Data line 0 for SD card interface.

OPWM0[4] — Pulse Width Modulator 0, output 4.

P1[7] 153 D14 C13 - [3] I;

PU I/O P1[7] — General purpose digital input/outp ut pin.

IENET_COL — Ethernet Collision detect (MII interface).

I/O SD_DAT[1] — Data line 1 for SD card interface.

OPWM0[5] — Pulse Width Modulator 0, output 5.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 17 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P1[8] 190 C7 B6 132 [3] I;

PU I/O P1[8] — General purpose digital input/outp ut pin.

IENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII

interface) or Ethernet Carrier Sense/Data Valid (RMII interface).

-R — Function reserved.

OT3_MAT1 — Match output for Timer 3, channel 1.

I/O SSP2_SSEL — Slave Select for SSP2.

P1[9] 188 A6 D7 131 [3] I;

PU I/O P1[9] — General purpose digital input/outp ut pin.

IENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

-R — Function reserved.

OT3_MAT0 — Match output for Timer 3, channel 0.

P1[10] 186 C8 A7 129 [3] I;

PU I/O P1[10] — General purpose digital input/output pin.

IENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

-R — Function reserved.

IT3_CAP0 — Capture input for Timer 3, channel 0.

P1[11] 163 A14 A12 - [3] I;

PU I/O P1[11] — General pu rpose digital input/output pin.

IENET_RXD2 — Ethernet Receive Data 2 (MII interface).

I/O SD_DAT[2] — Data line 2 for SD card interface.

OPWM0[6] — Pulse Width Modulator 0, output 6.

P1[12] 157 A16 A14 - [3] I;

PU I/O P1[12] — General purpose digital input/output pin.

IENET_RXD3 — Ethernet Receive Data (MII interface).

I/O SD_DAT[3] — Data line 3 for SD card interface.

IPWM0_CAP0 — Capture input for PWM0, channel 0.

P1[13] 147 D16 D14 - [3] I;

PU I/O P1[13] — General purpose digital input/output pin.

IENET_RX_DV — Ethernet Receive Data Valid (MII interface).

P1[14] 184 A7 D8 128 [3] I;

PU I/O P1[14] — General purpose digital input/output pin.

IENET_RX_ER — Ethernet receive error (RMII/MII interface).

-R — Function reserved.

IT2_CAP0 — Capture input for Timer 2, channel 0.

P1[15] 182 A8 A8 126 [3] I;

PU I/O P1[15] — General purpose digital input/output pin.

IENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock

(MII interface) or Ethernet Reference Clock (RMII interface).

-R — Function reserved.

I/O I2C2_SDA — I2C2 data input/output (this pin does not use a

specialized I2C pad).

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 18 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P1[16] 180 D10 B8 125 [3] I;

PU I/O P1[16] — General purpose digital input/output pin.

OENET_MDC — Ethernet MIIM clock.

OI2S_TX_MCLK — I2S transmit master clock.

P1[17] 178 A9 C9 123 [3] I;

PU I/O P1[17] — General purpose digital input/output pin.

I/O ENET_MDIO — Ethernet MIIM data input and output.

OI2S_RX_MCLK — I2S receive master clock.

P1[18] 66 P7 L5 46 [3] I;

PU I/O P1[18] — General purpose digital input/output pin.

OUSB_UP_LED1 — It is LOW when the device is configured

(non-control endpoints enabled), or when the host is enabled

and has detected a device on the bus. It is HIGH when the

device is not configured, or when host is enabled and has not

detected a device on the bus, or during global suspend. It

transitions between LOW and HIGH (flashes) when the host is

enabled and detects activity on the bus.

OPWM1[1] — Pulse Width Modulator 1, channel 1 outpu t.

IT1_CAP0 — Capture input for Timer 1, channel 0.

-R — Function reserved.

I/O SSP1_MISO — Master In Slave Out for SSP1.

P1[19] 68 U6 P5 47 [3] I;

PU I/O P1[19] — General purpose digital input/output pin.

OUSB_TX_E1 — Transmit Enable signal for USB port 1 (OTG

transceiver).

OUSB_PPWR1 — Port Power enable signal for USB port 1.

IT1_CAP1 — Capture input for Timer 1, channel 1.

OMC_0A — Motor control PWM channel 0, output A.

I/O SSP1_SCK — Serial clock for SSP1.

OU2_OE — RS-485/EIA-485 output enable signal for UART2.

P1[20] 70 U7 K6 49 [3] I;

PU I/O P1[20] — General purpose digital input/output pin.

OUSB_TX_DP1 — D+ transmit data for USB port 1 (OTG

transceiver).

OPWM1[2] — Pulse Width Modulator 1, channel 2 outpu t.

IQEI_PHA — Quadrature Encoder Interface PHA input.

IMC_FB0 — Motor control PWM channel 0 feedback input.

I/O SSP0_SCK — Serial clock for SSP0.

OLCD_VD[6] — LCD data.

OLCD_VD[10] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 19 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P1[21] 72 R8 N6 50 [3] I;

PU I/O P1[21] — General purpose digital input/output pin.

OUSB_TX_DM1 — D transmit data for USB port 1 (OTG

transceiver).

OPWM1[3] — Pulse Width Modulator 1, channel 3 outpu t.

I/O SSP0_SSEL — Slave Select for SSP0.

IMC_ABORT — Motor control PWM, active low fast abort.

-R — Function reserved.

OLCD_VD[7] — LCD data.

OLCD_VD[11] — LCD data.

P1[22] 74 U8 M6 51 [3] I;

PU I/O P1[22] — General purpose digital input/output pin.

IUSB_RCV1 — Differential receive data for USB port 1 (OTG

transceiver).

IUSB_PWRD1 — Power Status for USB port 1 (host power

switch).

OT1_MAT0 — Match output for Timer 1, channel 0.

OMC_0B — Motor control PWM channel 0, output B.

I/O SSP1_MOSI — Master Out Slave In for SSP1.

OLCD_VD[8] — LCD data.

OLCD_VD[12] — LCD data.

P1[23] 76 P9 N7 53 [3] I;

PU I/O P1[23] — General purpose digital input/output pin.

IUSB_RX_DP1 — D+ receive data for USB port 1 (OTG

transceiver).

OPWM1[4] — Pulse Width Modulator 1, channel 4 outpu t.

IQEI_PHB — Quadrature Encoder Interface PHB input.

IMC_FB1 — Motor control PWM channel 1 feedback input.

I/O SSP0_MISO — Master In Slave Out for SSP0.

OLCD_VD[9] — LCD data.

OLCD_VD[13] — LCD data.

P1[24] 78 T9 P7 54 [3] I;

PU I/O P1[24] — General purpose digital input/output pin.

IUSB_RX_DM1 — D receive data for USB port 1 (OTG

transceiver).

OPWM1[5] — Pulse Width Modulator 1, channel 5 outpu t.

IQEI_IDX — Quadrature Encoder Interface INDEX input.

IMC_FB2 — Motor control PWM channel 2 feedback input.

I/O SSP0_MOSI — Master Out Slave in for SSP0.

OLCD_VD[10] — LCD data.

OLCD_VD[14] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 20 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P1[25] 80 T10 L7 56 [3] I;

PU I/O P1[25] — General purpose digital input/output pin.

OUSB_LS1 — Low Spee d status for USB port 1 (OTG

transceiver).

OUSB_HSTEN1 — Host Enabled status for USB port 1.

OT1_MAT1 — Match output for Timer 1, channel 1.

OMC_1A — Motor control PWM channel 1, output A.

OCLKOUT — Selectable clock output.

OLCD_VD[11] — LCD data.

OLCD_VD[15] — LCD data.

P1[26] 82 R10 P8 57 [3] I;

PU I/O P1[26] — General purpose digital input/output pin.

OUSB_SSPND1 — USB port 1 Bus Suspend status (OTG

transceiver).

OPWM1[6] — Pulse Width Modulator 1, channel 6 outpu t.

IT0_CAP0 — Capture input for Timer 0, channel 0.

OMC_1B — Motor control PWM channel 1, output B.

I/O SSP1_SSEL — Slave Select for SSP1.

OLCD_VD[12] — LCD data.

OLCD_VD[20] — LCD data.

P1[27] 88 T12 M9 61 [3] I;

PU I/O P1[27] — General purpose digital input/output pin.

IUSB_INT1 — USB port 1 OTG transceiver interrupt (OTG

transceiver).

IUSB_OVRCR1 — USB port 1 Over-Current st at us.

IT0_CAP1 — Capture input for Timer 0, channel 1.

OCLKOUT — Selectable clock output.

-R — Function reserved.

OLCD_VD[13] — LCD data.

OLCD_VD[21] — LCD data.

P1[28] 90 T13 P10 63 [3] I;

PU I/O P1[28] — General purpose digital input/output pin.

I/O USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver).

IPWM1_CAP0 — Capture input for PWM1, channel 0.

OT0_MAT0 — Match output for Timer 0, channel 0.

OMC_2A — Motor control PWM channel 2, output A.

I/O SSP0_SSEL — Slave Select for SSP0.

OLCD_VD[14] — LCD data.

OLCD_VD[22] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 21 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P1[29] 92 U14 N10 64 [3] I;

PU I/O P1[29] — General purpose digital input/output pin.

I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver).

IPWM1_CAP1 — Capture input for PWM1, channel 1.

OT0_MAT1 — Match output for Timer 0, channel 1.

OMC_2B — Motor control PWM channel 2, output B.

OU4_TXD — Transmitter output for USART4 (input/output in

smart card mode).

OLCD_VD[15] — LCD data.

OLCD_VD[23] — LCD data.

P1[30] 42 P2 K3 30 [5] I;

PU I/O P1[30] — General purpose digital input/output pin.

IUSB_PWRD2 — Power Status for USB port 2.

IUSB_VBUS — Monitors the presence of USB bus pow er.

This signal must be HIGH for USB reset to occur.

IADC0_IN[4] — A/D converter 0, input 4. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2C0_SDA — I2C0 data input/output (this pin does not use a

specialized I2C pad).

OU3_OE — RS-485/EIA-485 output enable signal for UART3.

P1[31] 40 P1 K2 28 [5] I;

PU I/O P1[31] — General purpose digital input/output pin.

IUSB_OVRCR2 — Over-Current status for USB port 2.

I/O SSP1_SCK — Serial Clock for SSP1.

IADC0_IN[5] — A/D converter 0, input 5. When configured as an

ADC input, the digital function of the pin must be disabled.

I/O I2C0_SCL — I2C0 clock input/output (this pin does not use a

specialized I2C pad).

P2[0] to

P2[31] I/O Port 2: Port 2 is a 32 bit I/O port with individual direction

controls for each bit. The operation of port 1 pins depends upon

the pin function selected via the pin connect block.

P2[0] 154 B17 D12 107 [3] I;

PU I/O P2[0] — General purpose digital input/outp ut pin.

OPWM1[1] — Pulse Width Modulator 1, channel 1 outpu t.

OU1_TXD — Transmitter output for UART1.

-R — Function reserved.

OLCD_PWR — LCD panel power enable.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 22 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P2[1] 152 E14 C14 106 [3] I;

PU I/O P2[1] — General purpose digital input/outp ut pin.

OPWM1[2] — Pulse Width Modulator 1, channel 2 outpu t.

IU1_RXD — Receiver input for UART1.

-R — Function reserved.

OLCD_LE — Line end signal.

P2[2] 150 D15 E11 105 [3] I;

PU I/O P2[2] — General purpose digital input/outp ut pin.

OPWM1[3] — Pulse Width Modulator 1, channel 3 outpu t.

IU1_CTS — Clear to Send input for UART1.

OT2_MAT3 — Match output for Timer 2, channel 3.

-R — Function reserved.

OTRACEDATA[3] — Trace data, bit 3.

-R — Function reserved.

OLCD_DCLK — LCD panel clock.

P2[3] 144 E16 E13 100 [3] I;

PU I/O P2[3] — General purpose digital input/outp ut pin.

OPWM1[4] — Pulse Width Modulator 1, channel 4 outpu t.

IU1_DCD — Data Carrier Detect input for UART1.

OT2_MAT2 — Match output for Timer 2, channel 2.

-R — Function reserved.

OTRACEDATA[2] — Trace data, bit 2.

-R — Function reserved.

OLCD_FP — Frame pulse (STN). Vertical synchronization pulse

(TFT).

P2[4] 142 D17 E14 99 [3] I;

PU I/O P2[4] — General purpose digital input/outp ut pin.

OPWM1[5] — Pulse Width Modulator 1, channel 5 outpu t.

IU1_DSR — Data Set Ready input for UART1.

OT2_MAT1 — Match output for Timer 2, channel 1.

-R — Function reserved.

OTRACEDATA[1] — Trace data, bit 1.

-R — Function reserved.

OLCD_ENAB_M — STN AC bias drive or TFT data enable

output.

Table 3. Pin description … continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 23 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P2[5] 140 F16 F12 97 [3] I;

PU I/O P2[5] — General purpose digital input/outp ut pin.

OPWM1[6] — Pulse Width Modulator 1, channel 6 outpu t.

OU1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal for

UART1.

OT2_MAT0 — Match output for Timer 2, channel 0.

-R — Function reserved.

OTRACEDATA[0] — Trace data, bit 0.

-R — Function reserved.

OLCD_LP — Line synchroni zation pulse (STN). Horizontal

synchronization pulse (TFT).

P2[6] 138 E17 F13 96 [3] I;

PU I/O P2[6] — General purpose digital input/outp ut pin.

IPWM1_CAP0 — Capture input for PWM1, channel 0.

IU1_RI — Ring Indicator inpu t for UART1.

IT2_CAP0 — Capture input for Timer 2, channel 0.

OU2_OE — RS-485/EIA-485 output enable signal for UART2.

OTRACECLK — Trace clock.

OLCD_VD[0] — LCD data.

OLCD_VD[4] — LCD data.

P2[7] 136 G16 G11 95 [3] I;

PU I/O P2[7] — General purpose digital input/outp ut pin.

ICAN_RD2 — CAN2 receiver input.

OU1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

-R — Function reserved.

OLCD_VD[1] — LCD data.

OLCD_VD[5] — LCD data.

P2[8] 134 H15 G14 93 [3] I;

PU I/O P2[8] — General purpose digital input/outp ut pin.

OCAN_TD2 — CAN2 transmitter output.

OU2_TXD — Transmitter output for UART2.

IU1_CTS — Clear to Send input for UART1.

OENET_MDC — Ethernet MIIM clock.

-R — Function reserved.

OLCD_VD[2] — LCD data.

OLCD_VD[6] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 24 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P2[9] 132 H16 H11 92 [3] I;

PU I/O P2[9] — General purpose digital input/outp ut pin.

OUSB_CONNECT1 — USB1 SoftConnect control. Signal used to

switch an external 1.5 k resistor under the software control.

Used with the SoftConnect USB feature.

IU2_RXD — Receiver input for UART2.

IU4_RXD — Receiver input for USART4.

I/O ENET_MDIO — Ethernet MIIM data input and output.

-R — Function reserved.

ILCD_VD[3] — LCD data.

ILCD_VD[7] — LCD data.

P2[10] 110 N15 M13 76 [10] I;

PU I/O P2[10] — General purpose digital input/output pin. This pin

includes a 10 ns input .

A LOW on this pin while RESET is LOW forces the on-chip boot

loader to take over control of the part after a reset and go into

ISP mode.

IEINT0 — External interrup t 0 in put.

INMI — Non-maskable interrupt input.

P2[11] 108 T17 M12 75 [10] I;

PU I/O P2[11] — General pu rpose digital input/output pin. This pin

includes a 10 ns input glitch filter.

IEINT1 — External interrup t 1 input.

I/O SD_DAT[1] — Data line 1 for SD card interface.

I/O I2S_TX_SCK — Transmit Clock. It is driven by the master and

received by the slave. Corresponds to the signal SCK in the

I2S-bus specification.

-R — Function reserved.

OLCD_CLKIN — LCD clock.

P2[12] 106 N14 N14 73 [10] I;

PU I/O P2[12] — General purpose digital input/output pin. This pin

includes a 10 ns input glitch filter.

IEINT2 — External interrup t 2 input.

I/O SD_DAT[2] — Data line 2 for SD card interface.

I/O I2S_TX_WS — Transmit Word Select. It is driven by the master

and received by the slave. Corresp onds to the signal WS in the

I2S-bus specification.

OLCD_VD[4] — LCD data.

OLCD_VD[3] — LCD data.

OLCD_VD[8] — LCD data.

OLCD_VD[18] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 25 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P2[13] 102 T16 M11 71 [10] I;

PU I/O P2[13] — General purpose digital input/output pin. This pin

includes a 10 ns input glitch filter.

IEINT3 — External interrup t 3 input.

I/O SD_DAT[3] — Data line 3 for SD card interface.

I/O I2S_TX_SDA — Transmit data. It is driven by the transmitter

and read by the receiver. Correspo nds to the signal SD in the

I2S-bus specification.

-R — Function reserved.

OLCD_VD[5] — LCD data.

OLCD_VD[9] — LCD data.

OLCD_VD[19] — LCD data.

P2[14] 91 R12 - - [3] I;

PU I/O P2[14] — General purpose digital input/output pin.

OEMC_CS2 — LOW active Chip Select 2 signal.

I/O I2C1_SDA — I2C1 data input/output (this pin does not use a

specialized I2C pad).

IT2_CAP0 — Capture input for Timer 2, channel 0.

P2[15] 99 P13 - - [3] I;

PU I/O P2[15] — General purpose digital input/output pin.

OEMC_CS3 — LOW active Chip Select 3 signal.

I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a

specialized I2C pad).

IT2_CAP1 — Capture input for Timer 2, channel 1.

P2[16] 87 R11 P9 - [3] I;

PU I/O P2[16] — General purpose digital input/output pin.

OEMC_CAS — LOW active SDRAM Column Address Strobe.

P2[17] 95 R13 P11 - [3] I;

PU I/O P2[17] — General purpose digital input/output pin.

OEMC_RAS — LOW active SDRAM Row Address S trobe.

P2[18] 59 U3 P3 - [6] I;

PU I/O P2[18] — General purpose digital input/output pin.

OEMC_CLK[0] — SDRAM clock 0.

P2[19] 67 R7 N5 - [6] I;

PU I/O P2[19] — General purpose digital input/output pin.

OEMC_CLK[1] — SDRAM clock 1.

P2[20] 73 T8 P6 - [3] I;

PU I/O P2[20] — General purpose digital input/output pin.

OEMC_DYCS0 — SDRAM chip select 0.

P2[21] 81 U11 N8 - [3] I;

PU I/O P2[21] — General purpose digital input/output pin.

OEMC_DYCS1 — SDRAM chip select 1.

P2[22] 85 U12 - - [3] I;

PU I/O P2[22] — General purpose digital input/output pin.

OEMC_DYCS2 — SDRAM chip select 2.

I/O SSP0_SCK — Serial clock for SSP0.

IT3_CAP0 — Capture input for Timer 3, channel 0.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 26 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P2[23] 64 U5 - - [3] I;

PU I/O P2[23] — General purpose digital input/output pin.

OEMC_DYCS3 — SDRAM chip select 3.

I/O SSP0_SSEL — Slave Select for SSP0.

IT3_CAP1 — Capture input for Timer 3, channel 1.

P2[24] 53 P5 P1 - [3] I;

PU I/O P2[24] — General purpose digital input/output pin.

OEMC_CKE0 — SDRAM clock enable 0.

P2[25] 54 R4 P2 - [3] I;

PU I/O P2[25] — General purpose digital input/output pin.

OEMC_CKE1 — SDRAM clock enable 1.

P2[26] 57 T4 - - [3] I;

PU I/O P2[26] — General purpose digital input/output pin.

OEMC_CKE2 — SDRAM clock enable 2.

I/O SSP0_MISO — Master In Slave Out for SSP0.

OT3_MAT0 — Match output for Timer 3, channel 0.

P2[27] 47 P3 - - [3] I;

PU I/O P2[27] — General purpose digital input/output pin.

OEMC_CKE3 — SDRAM clock enable 3.

I/O SSP0_MOSI — Master Out Slave In for SSP0.

OT3_MAT1 — Match output for Timer 3, channel 1.

P2[28] 49 P4 M2 - [3] I;

PU I/O P2[28] — General purpose digital input/output pin.

OEMC_DQM0 — Data mask 0 used with SDRAM and static

devices.

P2[29] 43 N3 L1 - [3] I;

PU I/O P2[29] — General purpose digital input/output pin.

OEMC_DQM1 — Data mask 1 used with SDRAM and static

devices.

P2[30] 31 L4 - - [3] I;

PU I/O P2[30] — General purpose digital input/output pin.

OEMC_DQM2 — Data mask 2 used with SDRAM and static

devices.

I/O I2C2_SDA — I2C2 data input/output (this pin does not use a

specialized I2C pad).

OT3_MAT2 — Match output for Timer 3, channel 2.

P2[31] 39 N2 - - [3] I;

PU I/O P2[31] — General purpose digital input/output pin.

OEMC_DQM3 — Data mask 3 used with SDRAM and static

devices.

I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a

specialized I2C pad).

OT3_MAT3 — Match output for Timer 3, channel 3.

P3[0] to

P3[31] I/O Port 3: Port 3 is a 32-bit I/O po rt with individual direction

controls for each bit. The operation of port 3 pins depends upon

the pin function selected via the pin connect block.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 27 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P3[0] 197 B4 D6 137 [3] I;

PU I/O P3[0] — General purpose digital input/outp ut pin.

I/O EMC_D[0] — External memory data line 0.

P3[1] 201 B3 E6 140 [3] I;

PU I/O P3[1] — General purpose digital input/outp ut pin.

I/O EMC_D[1] — External memory data line 1.

P3[2] 207 B1 A2 144 [3] I;

PU I/O P3[2] — General purpose digital input/outp ut pin.

I/O EMC_D[2] — External memory data line 2.

P3[3] 3 E4 G5 2 [3] I;

PU I/O P3[3] — General purpose digital input/outp ut pin.

I/O EMC_D[3] — External memory data line 3.

P3[4] 13 F2 D3 9 [3] I;

PU I/O P3[4] — General purpose digital input/outp ut pin.

I/O EMC_D[4] — External memory data line 4.

P3[5] 17 G1 E3 12 [3] I;

PU I/O P3[5] — General purpose digital input/outp ut pin.

I/O EMC_D[5] — External memory data line 5.

P3[6] 23 J1 F4 16 [3] I;

PU I/O P3[6] — General purpose digital input/outp ut pin.

I/O EMC_D[6] — External memory data line 6.

P3[7] 27 L1 G3 19 [3] I;

PU I/O P3[7] — General purpose digital input/outp ut pin.

I/O EMC_D[7] — External memory data line 7.

P3[8] 191 D8 A6 - [3] I;

PU I/O P3[8] — General purpose digital input/outp ut pin.

I/O EMC_D[8] — External memory data line 8.

P3[9] 199 C5 A4 - [3] I;

PU I/O P3[9] — General purpose digital input/outp ut pin.

I/O EMC_D[9] — External memory data line 9.

P3[10] 205 B2 B3 - [3] I;

PU I/O P3[10] — General purpose digital input/output pin.

I/O EMC_D[10] — External memory data line 10.

P3[11] 208 D5 B2 - [3] I;

PU I/O P3[11] — General pu rpose digital input/output pin.

I/O EMC_D[11] — External memory data line 11.

P3[12] 1 D4 A1 - [3] I;

PU I/O P3[12] — General purpose digital input/output pin.

I/O EMC_D[12] — External memory data line 12.

P3[13] 7 C1 C1 - [3] I;

PU I/O P3[13] — General purpose digital input/output pin.

I/O EMC_D[13] — External memory data line 13.

P3[14] 21 H2 F1 - [3] I;

PU I/O P3[14] — General purpose digital input/output pin.

I/O EMC_D[14] — External memory data line 14.

P3[15] 28 M1 G4 - [3] I;

PU I/O P3[15] — General purpose digital input/output pin.

I/O EMC_D[15] — External memory data line 15.

P3[16] 137 F17 - - [3] I;

PU I/O P3[16] — General purpose digital input/output pin.

I/O EMC_D[16] — External memory data line 16.

OPWM0[1] — Pulse Width Modulator 0, output 1.

OU1_TXD — Transmitter output for UART1.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 28 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P3[17] 143 F15 - - [3] I;

PU I/O P3[17] — General purpose digital input/output pin.

I/O EMC_D[17] — External memory data line 17.

OPWM0[2] — Pulse Width Modulator 0, output 2.

IU1_RXD — Receiver input for UART1.

P3[18] 151 C15 - - [3] I;

PU I/O P3[18] — General purpose digital input/output pin.

I/O EMC_D[18] — External memory data line 18.

OPWM0[3] — Pulse Width Modulator 0, output 3.

IU1_CTS — Clear to Send input for UART1.

P3[19] 161 B14 - - [3] I;

PU I/O P3[19] — General purpose digital input/output pin.

I/O EMC_D[19] — External memory data line 19.

OPWM0[4] — Pulse Width Modulator 0, output 4.

IU1_DCD — Data Carrier Detect input for UART1.

P3[20] 167 A13 - - [3] I;

PU I/O P3[20] — General purpose digital input/output pin.

I/O EMC_D[20] — External memory data line 20.

OPWM0[5] — Pulse Width Modulator 0, output 5.

IU1_DSR — Data Set Ready input for UART1.

P3[21] 175 C10 - - [3] I;

PU I/O P3[21] — General purpose digital input/output pin.

I/O EMC_D[21] — External memory data line 21.

OPWM0[6] — Pulse Width Modulator 0, output 6.

OU1_DTR — Data Terminal Ready output for UART1. Can also

be configured to be an RS-485/EIA-485 output enable signal for

UART1.

P3[22] 195 C6 - - [3] I;

PU I/O P3[22] — General purpose digital input/output pin.

I/O EMC_D[22] — External memory data line 22.

IPWM0_CAP0 — Capture input for PWM0, channel 0.

IU1_RI — Ring Indicator inpu t for UART1.

P3[23] 65 T6 M4 45 [3] I;

PU I/O P3[23] — General purpose digital input/output pin.

I/O EMC_D[23] — External memory data line 23.

IPWM1_CAP0 — Capture input for PWM1, channel 0.

IT0_CAP0 — Capture input for Timer 0, channel 0.

P3[24] 58 R5 N3 40 [3] I;

PU I/O P3[24] — General purpose digital input/output pin.

I/O EMC_D[24] — External memory data line 24.

OPWM1[1] — Pulse Width Modulator 1, output 1.

IT0_CAP1 — Capture input for Timer 0, channel 1.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 29 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P3[25] 56 U2 M3 39 [3] I;

PU I/O P3[25] — General purpose digital input/output pin.

I/O EMC_D[25] — External memory data line 25.

OPWM1[2] — Pulse Width Modulator 1, output 2.

OT0_MAT0 — Match output for Timer 0, channel 0.

P3[26] 55 T3 K7 38 [3] I;

PU I/O P3[26] — General purpose digital input/output pin.

I/O EMC_D[26] — External memory data line 26.

OPWM1[3] — Pulse Width Modulator 1, output 3.

OT0_MAT1 — Match output for Timer 0, channel 1.

ISTCLK — System tick timer clock input. The maximum STCLK

frequency is 1/4 of the ARM processor clock frequency CCLK.

P3[27] 203 A1 - - [3] I;

PU I/O P3[27] — General purpose digital input/output pin.

I/O EMC_D[27] — External memory data line 27.

OPWM1[4] — Pulse Width Modulator 1, output 4.

IT1_CAP0 — Capture input for Timer 1, channel 0.

P3[28] 5 D2 - - [3] I;

PU I/O P3[28] — General purpose digital input/output pin.

I/O EMC_D[28] — External memory data line 28.

OPWM1[5] — Pulse Width Modulator 1, output 5.

IT1_CAP1 — Capture input for Timer 1, channel 1.

P3[29] 11 F3 - - [3] I;

PU I/O P3[29] — General purpose digital input/output pin.

I/O EMC_D[29] — External memory data line 29.

OPWM1[6] — Pulse Width Modulator 1, output 6.

OT1_MAT0 — Match output for Timer 1, channel 0.

P3[30] 19 H3 - - [3] I;

PU I/O P3[30] — General purpose digital input/output pin.

I/O EMC_D[30] — External memory data line 30.

OU1_RTS — Request to Send output for UART1. Can also be

configured to be an RS-485/EIA-485 output enable signal for

UART1.

OT1_MAT1 — Match output for Timer 1, channel 1.

P3[31] 25 J3 - - [3] I;

PU I/O P3[31] — General purpose digital input/output pin.

I/O EMC_D[31] — External memory data line 31.

-R — Function reserved.

OT1_MAT2 — Match output for Timer 1, channel 2.

P4[0] to

P4[31] I/O Port 4: Port 4 is a 32-bit I/O po rt with individual direction

controls for each bit. The operation of port 4 pins depends upon

the pin function selected via the pin connect block.

P4[0] 75 U9 L6 52 [3] I;

PU I/O P4[0] — General purpose digital input/outp ut pin.

I/O EMC_A[0] — External memory address line 0.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 30 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P4[1] 79 U10 M7 55 [3] I;

PU I/O P4[1] — General purpose digital input/outp ut pin.

I/O EMC_A[1] — External memory address line 1.

P4[2] 83 T11 M8 58 [3] I;

PU I/O P4[2] — General purpose digital input/outp ut pin.

I/O EMC_A[2] — External memory address line 2.

P4[3] 97 U16 K9 68 [3] I;

PU I/O P4[3] — General purpose digital input/outp ut pin.

I/O EMC_A[3] — External memory address line 3.

P4[4] 103 R15 P13 72 [3] I;

PU I/O P4[4] — General purpose digital input/outp ut pin.

I/O EMC_A[4] — External memory address line 4.

P4[5] 107 R16 H10 74 [3] I;

PU I/O P4[5] — General purpose digital input/outp ut pin.

I/O EMC_A[5] — External memory address line 5.

P4[6] 113 M14 K10 78 [3] I;

PU I/O P4[6] — General purpose digital input/outp ut pin.

I/O EMC_A[6] — External memory address line 6.

P4[7] 121 L16 K12 84 [3] I;

PU I/O P4[7] — General purpose digital input/outp ut pin.

I/O EMC_A[7] — External memory address line 7.

P4[8] 127 J17 J11 88 [3] I;

PU I/O P4[8] — General purpose digital input/outp ut pin.

I/O EMC_A[8] — External memory address line 8.

P4[9] 131 H17 H12 91 [3] I;

PU I/O P4[9] — General purpose digital input/outp ut pin.

I/O EMC_A[9] — External memory address line 9.

P4[10] 135 G17 G12 94 [3] I;

PU I/O P4[10] — General purpose digital input/output pin.

I/O EMC_A[10] — External memory address line 10.

P4[11] 145 F14 F11 101 [3] I;

PU I/O P4[11] — General pu rpose digital input/output pin.

I/O EMC_A[11] — External memory address line 11.

P4[12] 149 C16 F10 104 [3] I;

PU I/O P4[12] — General purpose digital input/output pin.

I/O EMC_A[12] — External memory address line 12.

P4[13] 155 B16 B14 108 [3] I;

PU I/O P4[13] — General purpose digital input/output pin.

I/O EMC_A[13] — External memory address line 13.

P4[14] 159 B15 E8 110 [3] I;

PU I/O P4[14] — General purpose digital input/output pin.

I/O EMC_A[14] — External memory address line 14.

P4[15] 173 A11 C10 120 [3] I;

PU I/O P4[15] — General purpose digital input/output pin.

I/O EMC_A[15] — External memory address line 15.

P4[16] 101 U17 N12 - [3] I;

PU I/O P4[16] — General purpose digital input/output pin.

I/O EMC_A[16] — External memory address line 16.

P4[17] 104 P14 N13 - [3] I;

PU I/O P4[17] — General purpose digital input/output pin.

I/O EMC_A[17] — External memory address line 17.

P4[18] 105 P15 P14 - [3] I;

PU I/O P4[18] — General purpose digital input/output pin.

I/O EMC_A[18] — External memory address line 18.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 31 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P4[19] 111 P16 M14 - [3] I;

PU I/O P4[19] — General purpose digital input/output pin.

I/O EMC_A[19] — External memory address line 19.

P4[20] 109 R17 - - [3] I;

PU I/O P4[20] — General purpose digital input/output pin.

I/O EMC_A[20] — External memory address line 20.

I/O I2C2_SDA — I2C2 data input/output (this pin does not use a

specialized I2C pad).

I/O SSP1_SCK — Serial Clock for SSP1.

P4[21] 115 M15 - - [3] I;

PU I/O P4[21] — General purpose digital input/output pin.

I/O EMC_A[21] — External memory address line 21.

I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a

specialized I2C pad).

I/O SSP1_SSEL — Slave Select for SSP1.

P4[22] 123 K14 - - [3] I;

PU I/O P4[22] — General purpose digital input/output pin.

I/O EMC_A[22] — External memory address line 22.

OU2_TXD — Transmitter output for UART2.

I/O SSP1_MISO — Master In Slave Out for SSP1.

P4[23] 129 J15 - - [3] I;

PU I/O P4[23] — General purpose digital input/output pin.

I/O EMC_A[23] — External memory address line 23.

IU2_RXD — Receiver input for UART2.

I/O SSP1_MOSI — Master Out Slave In for SSP1.

P4[24] 183 B8 C8 127 [3] I;

PU I/O P4[24] — General purpose digital input/output pin.

OEMC_OE — LOW active Output Enable signal.

P4[25] 179 B9 D9 124 [3] I;

PU I/O P4[25] — General purpose digital input/output pin.

OEMC_WE — LOW active Write Enable signal.

P4[26] 119 L15 K13 - [3] I;

PU I/O P4[26] — General purpose digital input/output pin.

OEMC_BLS0 — LOW active Byte Lane select signal 0.

P4[27] 139 G15 F14 - [3] I;

PU I/O P4[27] — General purpose digital input/output pin.

OEMC_BLS1 — LOW active Byte Lane select signal 1.

P4[28] 170 C11 D10 118 [3] I;

PU I/O P4[28] — General purpose digital input/output pin.

OEMC_BLS2 — LOW active Byte Lane select signal 2.

OU3_TXD — Transmitter output for UART3.

OT2_MAT0 — Match output for Timer 2, channel 0.

-R — Function reserved.

OLCD_VD[6] — LCD data.

OLCD_VD[10] — LCD data.

OLCD_VD[2] — LCD data.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 32 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P4[29] 176 B10 B9 122 [3] I;

PU I/O P4[29] — General purpose digital input/output pin.

OEMC_BLS3 — LOW active Byte Lane select signal 3.

IU3_RXD — Receiver input for UART3.

OT2_MAT1 — Match output for Timer 2, channel 1.

I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a

specialized I2C pad).

OLCD_VD[7] — LCD data.

OLCD_VD[11] — LCD data.

OLCD_VD[3] — LCD data.

P4[30] 187 B7 C7 130 [3] I;

PU I/O P4[30] — General purpose digital input/output pin.

OEMC_CS0 — LOW active Chip Select 0 signal.

P4[31] 193 A4 E7 134 [3] I;

PU I/O P4[31] — General purpose digital input/output pin.

OEMC_CS1 — LOW active Chip Select 1 signal.

P5[0] to P5[4] I/O Port 5: Port 5 is a 5-bit I/O port with individual direction controls

for each bit. The operation of port 5 pins depends upon the pin

function selected via the pin connect block.

P5[0] 9 F4 E5 6 [3] I;

PU I/O P5[0] — General purpose digital input/outp ut pin.

I/O EMC_A[24] — External memory address line 24.

I/O SSP2_MOSI — Master Out Slave In for SSP2.

OT2_MAT2 — Match output for Timer 2, channel 2.

P5[1] 30 J4 H1 21 [3] I;

PU I/O P5[1] — General purpose digital input/outp ut pin.

I/O EMC_A[25] — External memory address line 25.

I/O SSP2_MISO — Master In Slave Out for SSP2.

OT2_MAT3 — Match output for Timer 2, channel 3.

P5[2] 117 L14 L12 81 [11] I I/O P5[2] — General purpose digital input/outp ut pin.

-R — Function reserved.

OT3_MAT2 — Match output for Timer 3, channel 2.

-R — Function reserved.

I/O I2C0_SDA — I2C0 data input/output (this pin uses a specialized

I2C pad that supports I2C Fast Mode Plus).

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 33 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

P5[3] 141 G14 G10 98 [11] I I/O P5[3] — General purpose digital input/output pin.

-R — Function reserved.

IU4_RXD — Receiver input for USART4.

I/O I2C0_SCL — I2C0 clock input/output (this pin uses a

specialized I2C pad that supports I2C Fast Mode Plus).

P5[4] 206 C3 C4 143 [3] I;

PU I/O P5[4] — General purpose digital input/outp ut pin.

OU0_OE — RS-485/EIA-485 output enable signal for UART0.

-R — Function reserved.

OT3_MAT3 — Match output for Timer 3, channel 3.

OU4_TXD — Transmitter output for USART4 (input/output in

smart card mode).

JTAG_TDO

(SWO) 2D3B11[3] O O Test Data Out for JTAG interface. Also used as Serial wire trace

output.

JTAG_TDI 4 C2 C3 3 [3] I;

PU I Test Data In for JTAG interface.

JTAG_TMS

(SWDIO) 6E3C24[3] I;

PU I Test Mode Select for JTAG interface. Also used as Serial wire

debug data input/output.

JTAG_TRST 8D1D45[3] I;

PU I Test Reset for JTAG interface.

JTAG_TCK

(SWDCLK) 10 E2 D2 7 [3] i I Test Clock for JTAG interface. This clock must be slower than

1/6 of the CPU clock (CCLK) for the JTAG interface to opera te.

Also used as serial wir e cl ock.

RESET 35 M2 J1 24 [12] I;

PU I External reset input with 20 ns glitch filter . A LOW -going pulse

as short as 50 ns on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor

execution to begin at address 0. This pin also serves as the

debug select input. LOW level selects the JTAG boundary scan.

HIGH level selects the ARM SWD debug mode.

RSTOUT 29 K3 H2 20 [3] OH O Reset status output. A LOW output on this pin indicates that the

device is in the reset state for any reason. This reflects the

RESET input pin and all internal reset sources.

RTC_ALARM 37 N1 H5 26 [13] OL O RTC controlled output. This pin has a low drive strength and is

generated.

RTCX1 34 K2 J2 23 [14]

[15] - I Input to the RTC 32 kHz ultra-low power oscillator circuit.

RTCX2 36 L2 J3 25 [14]

[15] - O Output from the RTC 32 kHz ultra-low power oscillator circuit.

USB_D252U1N237

[9] - I/O USB port 2 bidirectional D line.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 34 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

VBAT 38 M3 K1 27 - I RTC power suppl y: 3.0 V on this pin supplies power to the RTC.

VDD(REG)(3V3) 26,

86,

174

H4,

P11,

D11

G1,

N9,

18,

60,

121

- S 3.3 V regulator supply voltage: This is the power supply for the

on-chip voltage regulator that supplies intern al logic.

VDDA 20 G4 F2 14 - S Analog 3.3 V pad supply voltage: This can be connected to the

same supply as VDD(3V3) but should be isolated to minimize

noise and error. This voltage is used to power the ADC and

DAC. Note: This pin shou ld be tied to 3.3 V if the ADC and

DAC are not used.

VDD(3V3) 15,

60,

71,

89,

112,

125,

146,

165,

181,

198

G3,

P6,

P8,

U13,

P17,

K16,

C17,

B13,

C9,

E2,

L4,

K8,

L11,

J14,

E12,

E10,

41,

62,

77,

102,

114,

138

- S 3.3 V supply voltage: This is the power supply voltage for I/O

other than pins in the VBAT domain.

VREFP 24 K1 G2 17 - S ADC positive reference voltage: This should be the same

voltage as VDDA, but should be isolated to minimize noise and

error. The voltage level on this pin is used as a reference for

ADC and DAC. Note: This pin should be tied to 3.3 V if the

ADC and DAC are not used.

VSS 33,

63,

77,

93,

114,

133,

148,

169,

189,

200

L3,

T5,

R9,

P12,

N16,

H14,

E15,

A12,

B6,

H4,

P4,

L9,

L13,

G13,

D13,

C11,

44,

65,

79,

103,

117,

139

- G Ground: 0 V reference for digital IO pins.

VSSREG 32,

84,

172

D12,

K4,

P10

H3,

L8,

A10

22,

59,

119

- G Ground: 0 V reference for internal logic.

VSSA 22 J2 F3 15 - G Analog ground: 0 V power supply and reference for the ADC

and DAC. This should be the same voltage as VSS, but should

be isolated to minimize noise and error.

XTAL1 44 M4 L2 31 [14]

[16] - I Input to the oscillator circuit and internal clock generator circuits.

XTAL2 46 N4 K4 33 [14]

[16] - O Output from the oscillator amplifier.

Table 3. Pin description …continued

Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC

pins).

Symbol

Pin LQFP208

Ball TFBGA208

Ball TFBGA180

Pin LQFP144

Reset state[1]

Type[2]

Description

Product data sheet Rev. 5.5 — 26 April 2016 35 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating

pins, if not used, should be tied to ground or power to minimize power consumption.

[2] I = Input; O = Output; OL = Output driving LOW; G = Ground; S = Supply.

[3] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL

levels and hysteresis.

[4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with

TTL levels and hysteresis. This pad can be powered by VBAT.

[5] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exce ed 3.6 V)

providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the

pad is disabled.

[6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL

levels and hysteresis.

[7] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V)

providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the

pad is disabled.

[8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin.

[9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only).

[10] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 5 ns glitch filter providing digital I/O

functions with TTL levels and hysteresis.

[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin.

[12] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 20 ns glitch filter providing digital I/O

function with TTL levels and hysteresis.

[13] This pad can be powered from VBAT.

[14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be

used to drive the RTCX1 pin.

[15] If the RTC is not used, these pins can be left floating.

[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Row A

1 P3[27] 2 VSS 3 P1[0] 4 P4[31]

5 P1[4] 6 P1[9] 7 P1[14] 8 P1[15]

9 P1[17] 10 P1[3] 11 P4[15] 12 VSS

13 P3[20] 14 P1[11] 15 P0[8] 16 P1[12]

17 P1[5] - - -

Row B

1 P3[2] 2 P3[10] 3 P3[1] 4 P3[0]

5 P1[1] 6 VSS 7 P4[30] 8 P4[24]

9 P4[25] 10 P4[29] 11 P1[6] 12 P0[4]

13 VDD(3V3) 14 P3[19] 15 P4[14] 16 P4[13]

17 P2[0] - - -

Row C

Product data sheet Rev. 5.5 — 26 April 2016 36 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

1 P3[13] 2 JTAG_TDI 3 P5[4] 4 P0[2]

5 P3[9] 6 P3[22] 7 P1[8] 8 P1[10]

DD(3V3) 10 P3[21] 11 P4[28] 12 P0[5]

13 P0[7] 14 P0[9] 15 P3[18] 16 P4[12]

17 VDD(3V3)- - -

Row D

1 JTAG_TRST 2 P3[28] 3 JTAG_TDO (SWO) 4 P3[12]

5P3[11] 6P0[3] 7V

DD(3V3) 8 P3[8]

9 P1[2] 10 P1[16] 11 VDD(REG)(3V3) 12 VSSREG

13 P0[6] 14 P1[7] 15 P2[2] 16 P1[13]

17 P2[4] - - -

Row E

1 P0[26] 2 JTAG_TCK

(SWDCLK) 3 JTAG_TMS (SWDIO) 4 P3[3]

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 P2[1] 15 VSS 16 P2[3]

17 P2[6] - - -

Row F

1 P0[25] 2 P3[4] 3 P3[29] 4 P5[0]

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 P4[11] 15 P3[17] 16 P2[5]

17 P3[16] - - -

Row G

1 P3[5] 2 P0[24] 3 VDD(3V3) 4V

DDA

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 P5[3] 15 P4[27] 16 P2[7]

17 P4[10] - - -

Row H

1 P0[23] 2 P3[14] 3 P3[30] 4 VDD(REG)(3V3)

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 VSS 15 P2[8] 16 P2[9]

17 P4[9] - - -

Row J

1 P3[6] 2 VSSA 3 P3[31] 4 P5[1]

5- 6- 7- 8-

9 - 10 - 11 - 12 -

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Product data sheet Rev. 5.5 — 26 April 2016 37 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

13 14 P0[16] 15 P4[23] 16 P0[15]

17 P4[8] - - -

Row K

1 VREFP 2 RTCX1 3 RSTOUT 4 VSSREG

13 - 14 P4[22] 15 P0[18] 16 VDD(3V3)

17 P0[17] - - -

Row L

1 P3[7] 2 RTCX2 3 VSS 4 P2[30]

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 P5[2] 15 P4[26] 16 P4[7]

17 P0[19] - - -

Row M

1 P3[15] 2 RESET 3 VBAT 4 XTAL1

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 P4[6] 15 P4[21] 16 P0[21]

17 P0[20] - - -

Row N

1 RTC_ALARM 2 P2[31] 3 P2[29] 4 XTAL2

5- 6- 7- 8-

9 - 10 - 11 - 12 -

13 - 14 P2[12 15 P2[10] 16 VSS

17 P0[22] - - -

Row P

1 P1[31] 2 P1[30] 3 P2[27] 4 P2[28]

5 P2[24] 6 VDD(3V3) 7 P1[18] 8 VDD(3V3)

9 P1[23] 10 VSSREG 11 VDD(REG)(3V3) 12 VSS

13 P2[15] 14 P4[17] 15 P4[18] 16 P4[19]

17 VDD(3V3) ---

Row R

1 P0[12] 2 P0[13] 3 P0[28] 4 P2[25]

5 P3[24] 6 P0[30] 7 P2[19] 8 P1[21]

SS 10 P1[26] 11 P2[16] 12 P2[14]

13 P2[17] 14 P0[11] 15 P4[4] 16 P4[5]

17 P4[20] - - -

Row T

1 P0[27] 2 P0[31] 3 P3[26] 4 P2[26]

SS 6 P3[23] 7 P0[14] 8 P2[20]

9 P1[24] 10 P1[25] 11 P4[2] 12 P1[27]

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Product data sheet Rev. 5.5 — 26 April 2016 38 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

13 P1[28] 14 P0[1] 15 P0[10] 16 P2[13]

17 P2[11] - - -

Row U

1 USB_D-2 2 P3[25] 3 P2[18] 4 P0[29]

5 P2[23] 6 P1[19] 7 P1[20] 8 P1[22]

9 P4[0] 10 P4[1] 11 P2[21] 12 P2[22]

13 VDD(3V3) 14 P1[29] 15 P0[0] 16 P4[3]

17 P4[16] - - -

Table 4. Pin allocation table TFBGA208

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Table 5. Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Row A

5 P1[1] 6 P3[8] 7 P1[10] 8 P1[15]

9 P1[3] 10 VSSREG 11 P0[4] 12 P1[11]

13 P0[9] 14 P1[12] - -

Row B

1 JTAG_TDO (SWO) 2 P3[11] 3 P3[10] 4 V SS

5 P1[0] 6 P1[8] 7 P1[2] 8 P1[16]

9 P4[29] 10 P1[6] 11 P0[5] 12 P0[7]

13 P1[5] 14 P4[13] - -

Row C

1 P3[13] 2 JTAG_TMS (SWDIO) 3 JTAG_TDI 4 P5[4]

DD(3V3) 6 P1[4] 7 P4[30] 8 P4[24]

9 P1[17] 10 P4[15] 11 VSS 12 P0[8]

13 P1[7] 14 P2[1] - -

Row D

1 P0[26] 2 JTAG_TCK

(SWDCLK) 3 P3[4] 4 JTAG_TRST

5 P0[2] 6 P3[0] 7 P1[9] 8 P1[14]

9 P4[25] 10 P4[28] 11 P0[6] 12 P2[0]

13 VSS 14 P1[13] - -

Row E

1 P0[24] 2 VDD(3V3) 3 P3[5] 4 P0[25]

5 P5[0] 6 P3[1] 7 P4[31] 8 P4[14]

DD(REG)(3V3) 10 VDD(3V3) 11 P2[2] 12 VDD(3V3)

13 P2[3] 14 P2[4] - -

Row F

1 P3[14] 2 VDDA 3V

SSA 4 P3[6]

5 P0[23] 6 - 7 - 8 -

9 - 10 P4[12] 11 P4[11] 12 P2[5]

Product data sheet Rev. 5.5 — 26 April 2016 39 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

13 P2[6] 14 P4[27] - -

Row G

DD(REG)(3V3) 2 VREFP 3 P3[7] 4 P3[15]

5 P3[3] 6 - 7 - 8 -

9 - 10 P5[3] 11 P2[7] 12 P4[10]

13 VSS 14 P2[8] - -

Row H

1 P5[1] 2 RSTOUT 3V

SSREG 4V

5RTC_ALARM 6- 7- 8-

9 - 10 P4[5] 11 P2[9] 12 P4[9]

13 P0[15] 14 P0[16] - -

Table 5. Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Product data sheet Rev. 5.5 — 26 April 2016 40 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses are faster than the system bus and

are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for

instruction fetch (I-code) and one bus for data access (D-code). The use of two core

buses allows for simult aneous operations if concurrent operation s target dif ferent devices.

Row J

1 RESET 2 RTCX1 3 RTCX2 4 P0[12]

5 P0[13] 6 - 7 - 8 -

9 - 10 P0[19] 11 P4[8] 12 P0[17]

13 P0[18] 14 VDD(3V3) --

Row K

1 VBAT 2 P1[31] 3 P1[30] 4 XTAL2

5 P0[29] 6 P1[20] 7 P3[26] 8 VDD(3V3)

9 P4[3] 10 P4[6] 11 P0[21] 12 P4[7]

13 P4[26] 14 P0[20] - -

Row L

1 P2[29] 2 XTAL1 3 P0[27] 4 VDD(3V3)

5 P1[18] 6 P4[0] 7 P1[25] 8 VSSREG

SS 10 P0[10] 11 VDD(3V3) 12 P5[2]

13 VSS 14 P0[22] - -

Row M

1 P0[28] 2 P2[28] 3 P3[25] 4 P3[23]

5 P0[14] 6 P1[22] 7 P4[1] 8 P4[2]

9 P1[27] 10 P0[0] 11 P2[13] 12 P2[11]

13 P2[10] 14 P4[19] - -

Row N

1 P0[31] 2 USB_D-2 3 P3[24] 4 P0[30]

5 P2[19] 6 P1[21] 7 P1[23] 8 P2[21]

DD(REG)(3V3) 10 P1[29] 11 P0[1] 12 P4[16]

13 P4[17] 14 P2[12] - -

Row P

1 P2[24] 2 P2[25] 3 P2[18] 4 VSS

5 P1[19] 6 P2[20] 7 P1[24] 8 P1[26]

9 P2[16] 10 P1[28] 11 P2[17] 12 P0[11]

13 P4[4] 14 P4[18] - -

Table 5. Pin allocation table TFBGA180

Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).

Ball Symbol Ball Symbol Ball Symbol Ball Symbol

Product data sheet Rev. 5.5 — 26 April 2016 41 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and

other bus mast er s to pe rip her als in a fle xible ma nn e r tha t op tim ize s pe rform a nce by

allowing peripherals that are on different slaves ports of the matrix to be accessed

simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware division,

hardware single-cycle multiply, interruptable/continuable multiple load and store

instructions, automatic state save and restore for interrupts, tightly integrated interrupt

controller with wake-up interrupt controller, and multiple core buses capable of

simultaneous accesses.

Pipeline techniques are em ployed so that all p arts of the processing and memory system s

can operate continuously. Typically, while one instruction is bein g executed, its successor

is being decoded, and a thir d instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual that can be found on official ARM website.

7.3 On-chip flash program memory

The LPC178x/7x contain up to 512 kB of on-chip flash program memory. A new two-port

flash accelerator maximizes performance for use with the two fast AHB-Lite buses.

7.4 EEPROM

The LPC178x/7x contains up to 4032 byte of on-chip byte-erasab le and

byte-progr a mm a ble EEPROM da ta memory.

7.5 On-chip SRAM

The LPC178x/7x contain a total of up to 96 kB on-chip st atic RAM data memory. This

includes the main 64 kB SRAM, accessible by the CPU and DMA controller on a

higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a

separate slave port on the AHB multilayer matrix.

This architecture allows CPU and DMA accesses to be spr ead over three sep arate RAMs

that can be accessed simultaneously.

7.6 Memory Protection Unit (MPU)

The LPC178x/7x have a Memory Protection Unit (MPU) which can be used to improve the

reliability of an embedded system by protecting critical data within the user application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory r egio ns, allowing me mor y regi ons to be de fined as re ad -onl y

and detecting unexpected memory accesses that could potentially break the system.

Product data sheet Rev. 5.5 — 26 April 2016 42 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU support s up to eight r egions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

7.7 Memory map

The LPC178x/7x incorporate several distinct memory regions, shown in the following

figures. Figure 6 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral ar ea is 2 MB in size, and is divided to allow for up to 128 periph erals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

Table 6. LPC178x/177x memory usage and details

Address range General Use Address range details and description

0x0000 0000 to

0x1FFF FFFF On-chip non-volatile

memory 0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory.

0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory.

0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory.

0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory.

On-chip main SRAM 0x1000 0000 - 0x1000 FFFF For devices with 64 kB of main SRAM.

0x1000 0000 - 0x1000 7FFF For devices with 32 kB of main SRAM.

0x1000 0000 - 0x1000 3FFF For devices with 16 kB of main SRAM.

Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services.

0x2000 0000 to

0x3FFF FFFF On-chip SRAM

(typically used for

peripheral data)

0x2000 0000 - 0x2000 1FFF Peripheral RAM - bank 0 (first 8 kB)

0x2000 2000 - 0x2000 3FFF Peripheral RAM - bank 0 (second 8 kB)

0x2000 4000 - 0x2000 7FFF Peripheral RAM - bank 1 (16 kB)

AHB peripherals 0x2008 0000 - 0x200B FFFF See Figure 6 fo r details

0x4000 0000 to

0x7FFF FFFF APB Peripherals 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of

16 kB each.

0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of

16 kB each.

0x8000 0000 to

0xDFFF FFFF Off-chip Memory via

the External Memory

Controller

Four static memory chip selects:

0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 MB)

0x9000 0000 - 0x93FF FFFF Static memory chip select 1 (up to 64 MB)

0x9800 0000 - 0x9BFF FFFF Static memory chip select 2 (up to 64 MB)

0x9C00 0000 - 0x9FFF FFFF Static memory chip select 3 (up to 64 MB)

Four dynamic memory chip selects:

0xA000 0000 - 0xAFFF FFFF Dynamic memo ry chip select 0 (up to 256MB)

0xB000 0000 - 0xBFFF FFFF Dynamic memo ry chip select 1 (up to 256MB)

0xC000 0000 - 0xCFFF FFFF Dynamic memory chi p select 2 (up to 256MB)

0xD000 0000 - 0xDFFF FFFF Dynamic memory chi p select 3 (up to 256MB)

0xE000 0000 to

0xE00F FFFF Cortex-M3 Private

Peripheral Bus 0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC

and System Tick Timer.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 5.5 — 26 April 20 16 43 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

(1) Not available on all parts. See Table 2 and Table 6.

Fig 6. LPC178x/7x memory map

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4002 C000

0x4003 4000

0x4003 0000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 C000

0x4006 0000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

APB1 peripherals

0x4008 0000

0x4008 8000

0x4008 C000

0x4009 0000

0x4009 4000

0x4009 8000

0x4009 C000

0x400A 0000

0x400A 4000

0x400A 8000

0x400A C000

0x400B 0000

0x400B 4000

0x400B 8000

0x400B C000

0x400C 0000

0x400F C000

0x4010 0000

SSP0

DAC

timer 2

timer 3

UART2

UART3

USART4(1)

I2C2

1 - 0 reserved

SSP2

I2S

reserved

motor control PWM

reserved

30 - 17 reserved

system control31

reserved

64 kB main static RAM(1)

EMC 4 x static chip select(1)

EMC 4 x dynamic chip select(1)

reserved

private peripheral bus

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 0000

0x1001 0000

0x1FFF 0000

0x2000 0000

0x2000 8000

0x2008 0000

0x2200 0000

0x200A 0000

0x2400 0000

0x2800 0000

0x4000 0000

0x4008 0000

0x4010 0000

0x4200 0000

0x4400 0000

0x8000 0000

0xA000 0000

0xE000 0000

0xE010 0000

0xFFFF FFFF

reserved

APB0 peripherals

0xE004 0000

AHB peripherals

APB1 peripherals

peripheral

SRAM bit-band alias addressing

peripheral bit-band alias addressing

16 kB peripheral SRAM1(1) 0x2000 4000

16 kB peripheral SRAM0(1)

LPC178x/7x

0x0008 0000

512 kB on-chip flash(1)

QEI(1)

SD/MMC(1)

APB0 peripherals

WWDT

timer 0

timer 1

UART0

UART1

reserved

CAN AF RAM

CAN common

CAN1

CAN2

CAN AF registers

PWM0

I2C0

RTC/event recorder

+ backup registers

GPIO interrupts

pin connect

SSP1

ADC

22 - 19 reserved

I2C1

31 - 24 reserved

PWM1

8 kB boot ROM

0x0000 0000

0x0000 0400

active interrupt vectors

+ 256 words

I-code/D-code

memory space

002aaf574

reserved 0x1FFF 2000

0x2900 0000

reserved

0x2008 0000

0x2008 4000

0x2008 8000

0x2008 C000

0x200A 0000

0x2009 C000

AHB peripherals

LCD(1)

USB(1)

Ethernet(1)

GPDMA controller

0x2009 0000

CRC engine

0x2009 4000

50x2009 8000

GPIO

EMC registers

Product data sheet Rev. 5.5 — 26 April 2016 44 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.8 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral p art of the Cortex-M3. The tight co upling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.8.1 Features

•Controls system exceptions and peripheral interrupts.

•On the LPC178x/7x, the NVIC supports 40 vectored interrupt s.

•32 programmable interrupt priority levels, with hardware priority level masking.

•Relocatable vector table.

•Non-Maskable Interrupt (NMI).

•Software interrupt generation .

7.8.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

Any pin on port 0 and port 2 regardless of the selected function can be programmed to

generate an interrupt on a rising edge, a falling edge, or both.

7.9 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to th e appro priate pins prior to being activated and prior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

Most pins can also be con figured as open- drain output s or to have a pull- up, pull-do wn, or

no resistor enabled.

7.10 External memory controller

Remark: Supported memory size and type and EMC bus width vary for different parts

(see Table 2). The EMC pin configuration for each part is shown in Table 7.

Product data sheet Rev. 5.5 — 26 April 2016 45 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Table 7. External memory controller pin configuration

Part Data bus pins Address bus

pins Control pins

SRAM SDRAM

LPC1788FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1788FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1788FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0],

EMC_CS[1:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[1:0],

EMC_CLK[1:0], EMC_CKE[1:0],

EMC_DQM[1:0]

LPC1788FBD144 EMC_D[7:0] EMC_A[15:0] EMC_BLS[3:2],

EMC_CS[1:0],

EMC_OE, EMC_WE

not available

LPC1787FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS_[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1786FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1785FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1778FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1778FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1778FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0],

EMC_CS[1:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[1:0],

EMC_CLK[1:0], EMC_CKE[1:0],

EMC_DQM[1:0]

LPC1778FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0],

EMC_OE, EMC_WE not available

LPC1777FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1776FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1776FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[1:0],

EMC_CLK[1:0], EMC_CKE[1:0],

EMC_DQM[1:0]

LPC1774FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],

EMC_CS[3:0],

EMC_OE, EMC_WE

EMC_RAS, EMC_CAS, EMC_DYCS[3:0],

EMC_CLK[1:0], EMC_CKE[3:0],

EMC_DQM[3:0]

LPC1774FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0],

EMC_OE, EMC_WE not available

Product data sheet Rev. 5.5 — 26 April 2016 46 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral

offering support for asynchronous static memory devices such as RAM, ROM, and flash.

In addition, it can be used as an interface with off-chip memory-mapped devices and

peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

peripheral.

See Table 6 for EMC memory access.

7.10.1 Features

•Dynamic memory interface supp ort including single data rate SDRAM.

•Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

•Low transaction latency.

•Read and write buffers to reduce latency and to improve performance.

•8/16/32 data and 16/20/26 address lines wid e static memory support.

•16 bit and 32 bit wide chip select SDRAM memory support.

•Static memory features include:

–Asynchronous page mode read.

–Programmable Wait States.

–Bus turnaround delay.

–Output enable and write enable delays.

–Extended wait.

•Four chip selects for synchronous memory and four chip selects for static memory

devices.

•Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to

SDRAMs.

•Dynamic memory self-refresh mode controlled by software.

•Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB

parts, with 4, 8, 16, or 32 data bits per device.

•Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.11 General purpose DMA controller

The GPDMA is an AMBA AHB compliant periphe ral allowing selected peripherals to have

DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. The source and

destination areas can each be either a memory region or a peripheral and can be

accessed through the AHB master. The GPDMA controller allows data transfers between

the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the

I2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be

triggered by selected timer match conditions. Memory-to-memory transfers and transfers

to or from GPIO are supported.

Product data sheet Rev. 5.5 — 26 April 2016 47 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.11.1 Features

•Eight DMA channels. Each channel can support an unidirectional transfer.

•16 DMA request lines.

•Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

•Memory-to-memory, memory- to-peripheral, peripheral-to-memory, and

periphera l-to -p e rip he ra l tra ns fe rs ar e su pp or te d.

•Scatter or gather DMA is supported through the use of linked lists . This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Hardware DMA channel priority.

•AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

•One AHB bus master for transferring data. The interface transfers data when a DMA

request goes active.

•32-bit AHB master bus width.

•Incrementing or non-incrementing addressing for source and destination.

•Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

•Internal four-word FIFO per channel.

•Supports 8, 16, and 32-b it wid e tra n sac tio ns .

•Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.

•An interrupt to the pr ocessor ca n be gene rated o n a DMA comp letion or when a DMA

error has occurred.

•Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

prior to masking.

7.12 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings

supports several CRC standards commonly used. To save system power and bu s

bandwidth, the CRC engine supports DMA transfers.

7.12.1 Features

•Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

–CRC-CCITT: x16 + x12 + x5 + 1

–CRC-16: x16 + x15 + x2 + 1

–CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

•Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

•Programmable seed number setting.

•Supports CPU PIO or DMA back-to-ba ck tra nsfe r.

Product data sheet Rev. 5.5 — 26 April 2016 48 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

•Accept any size of data width per write: 8, 16 or 32-bit.

–8-bit write: 1-cycle operation.

–16-bit write: 2-cycle operation (8-bit x 2-cycle).

–32-bit write: 4-cycle operation (8-bit x 4-cycle).

7.13 LCD controller

Remark: The LCD controller is available on parts LPC1788/87/86/85.

The LCD controller provides all of the necessary control signals to interface directly to a

variety of color and mono chro me LCD panels. Both ST N (sing le a nd dua l panel) and TFT

panels can be oper ated. The disp lay resolutio n is se lect able a nd can be up to 1024 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the

displayed data) while still supporting a large number of colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other sys te m fu nc tion s. A built-in FIF O acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time needed to operate the display.

7.13.1 Features

•AHB master interface to access frame buffer.

•Setup and control via a separate AHB slave interface.

•Dual 16-deep program mable 64-bit wide FIFOs for buffering incoming display data.

•Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

•Supports single and du al-panel color STN displays.

•Supports Thin Film Transistor (TFT) color displays.

•Programmable display resolution including, but not limited to: 320 200, 320 240,

640 200, 640 240, 640 480, 800 600, and 1024 768.

•Hardware cursor support for single-panel displays.

•15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

•1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

•1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

•16 bpp true-color non-palettized, for color STN and TFT.

•24 bpp true-color non-palettized, for color TFT.

•Programmable timing for different display pan els.

•256 entry, 16-bit palette RAM, arr a ng ed as a 12 8 32-bit RAM.

•Frame, line, and pix el cloc k si gn als .

•AC bias signal for STN, data enable signal fo r TFT panels.

•Supports little and big-endian, and Windows CE data formats.

•LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

Product data sheet Rev. 5.5 — 26 April 2016 49 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.14 Ethernet

Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76.

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance thro ugh the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering an d wa ke-u p o n LAN activity. Automatic frame transmissio n and recep tion

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus

through the AHB-multilayer matrix to access the various on-chip SRAM blocks for

Ethernet data, control, and status information.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Media

Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media

Independent Interface Management (MIIM) serial bus.

7.14.1 Features

•Ethernet st andards support:

–Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

–Fully compliant with IEEE standard 802.3.

–Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back

pressure.

–Flexible transmit and receive frame options.

–Vir tual Local Area Network (VLAN) frame support

–.

•Memory management:

–Independent transmit and receive buffers memory mapped to shared SRAM.

–DMA managers with scatter/gather DMA and arrays of frame descriptors.

–Memory traffic optimized by buffering and pre-fetching.

•Enhanced Ethernet features:

–Receive filtering.

–Multicast and broadcast frame support for both transmit and receive.

–Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

–Selectable automatic transmit frame padding.

–Over-length frame suppor t for both transmit and receive allows any length frames.

–Promiscuous receive mode.

–Automatic collision back-off and frame retransmission.

–Includes power management by clock switching.

–Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

Product data sheet Rev. 5.5 — 26 April 2016 50 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

•Physical interface:

–Attachment of external PHY chip through standard MII or RMII interface.

–PHY register access is available via the MIIM interface.

7.15 USB interface

Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85

and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774.

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices th rough a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

Details on typical USB interfacing solutions can be found in Section 14.1.

7.15.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, endpoint buffer mem ory, and a

DMA controller. The serial interface engi ne decodes the USB dat a stream a nd writes dat a

to the appropriate endpoint buffer. The status of a completed USB transfer or error

condition is indicated via status registers. An interrupt is also generated if enabled. When

enabled, the DMA controller transfer s data between the endpoint buffer and the USB

RAM.

7.15.1.1 Features

•Fully compliant with USB 2.0 Specification (full speed).

•Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

•Supports Control, Bulk, Interrupt and Isochronous endpoints.

•Scalable realization of endpoi nts at run time.

•Endpoint Maximum pa cket size selection (up to USB maximum specification) by

software at run time.

•Supports SoftConnect and GoodLink features.

•While USB is in the Suspend mode, the LPC178x/7x can enter one of the reduced

power modes and wake up on USB activity.

•Supports DMA transfers with all on -chip SRAM blocks on all non- co nt ro l endpoints.

•Allows dynamic switching between CPU-controlled and DMA modes.

•Double buffer implementation for Bulk and Isochronous endpoints.

7.15.2 USB host controller

The host controller enables full- and low-speed dat a exchange with USB devices attached

to the bus. It consists of register in terface, serial interface engine and DMA controller . The

7.15.2.1 Features

•OHCI compliant.

Product data sheet Rev. 5.5 — 26 April 2016 51 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

•Two down str e am ports.

•Supports per-port power switching.

7.15.3 USB OTG controller

USB OTG is a supplement to the USB 2.0 Specification that augments the capability of

existing mobile devices and USB peripherals by adding host functionali ty for connecti on to

USB peripherals.

The OTG Controller integra tes the host controller, device controller , a nd a master-only I2C

interface to implement OTG dual-role device functionality. The dedicated I2C interface

controls an external OTG transceiver.

7.15.3.1 Features

•Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

1.0a.

•Hardware support for Host Negotiation Protocol (HNP).

•Includes a programmable timer required for HNP and Session Request Protocol

(SRP).

•Supports any OTG transceiver compliant with the OTG Transceiver Specification

(CEA-2011), Rev. 1.0.

7.16 SD/MMC card interface

Remark: The SD/MMC card interface is available on parts LPC1788/87/86/85 and parts

LPC1778/77/76.

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the SD Multimedia Card Specification

Version 2.11.

7.16.1 Features

•The MCI provides all functions specific to the SD/MMC memory card. These include

the clock generation unit, power management control, and command and dat a

transfer.

•Conforms to Multimedia Card Specification v2.11.

•Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

•Can be used as a multimedia card bus or a secure d igit al memo ry card bus ho st. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

•DMA supported through the GPDMA controller.

7.17 Fast general purpose parallel I/O

Device pins that are not connected to a specific perip heral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any numbe r of outp uts simultan eou sly. The value of the

output register may be read back as well as the current state of the port pins.

LPC178x/7x use accelerated GPIO functions:

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NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

•GPIO registe rs are accessed throug h the AHB mu ltila ye r bus s o that th e fa ste st

possible I/O timing can be achieved.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All GPIO registers are byte and half-word addressable.

•Entire port value can be written in one instruction.

•Support for Cortex-M3 bit banding.

•Support for use with the GPDMA controller.

Additionally, any pin on Port 0 and Por t 2 pr ovid in g a dig ital function can be pr og ra m m ed

to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is

asynchronous, so it may operate when clocks are not present such as during Power-down

mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.

7.17.1 Features

•Bit level set and clear registers allow a single instr uction to set or clear any nu mber of

bits in one port.

•Direction control of individual bits.

•All I/O default to inputs after reset.

•Pull-up/pull-down resistor configuration and open-drain configuration can be

programmed through the pin connect block for each GPIO pin.

7.18 12-bit ADC

The LPC178x/7x contain one ADC. It is a single 12-bit successive approximation ADC

with eight channels and DMA support.

7.18.1 Features

•12-bit successive approximation ADC.

•Input multiplexing among eight pins.

•Power-down mode.

•Measurement range VSS to VREFP.

•12-bit conversion rate: up to 400 kHz.

•Individual channels can be selected for conversion.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pin or Timer Match signal.

•Individual result registers for each ADC channel to reduce interrupt overhead.

•DMA support.

7.19 10-bit DAC

The LPC178x/7x cont ain one DAC. The DAC allo ws to generate a variable an alog output.

The maximum output value of the DAC is VREFP.

Product data sheet Rev. 5.5 — 26 April 2016 53 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.19.1 Features

•10-bit DAC.

•Resistor string architecture.

•Buff ered output.

•Power-down mode.

•Selectable output drive.

•Dedicated conversion timer.

•DMA support.

7.20 UARTs

Remark: USART4 is not available on part LPC1774FBD144.

The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data

lines, UART1 also provides a full modem control handshake interface and support for

RS-485/9-bit mode allowing both software address detection and automatic address

detection using 9-bit mode.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal fr equency above 2 MHz.

7.20.1 Features

•Maximum UART data bit rate of 7.5 MBit/s.

•16 B Receive and Transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•Auto-baud capability.

•Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

•Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing.

•All UARTs have D MA supp or t for bo th tr an smit an d re ce ive.

•UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

•USART4 includes an IrDA mode to support infrared communication.

•USART4 supports syn chronous mode and a smart card mode conforming to

ISO7816-3.

7.21 SSP serial I/O controller

The LPC178x/7x contain three SSP controllers. The SSP controller is capable of

operation on a SPI, 4-wir e SSI, or Microwire bus . It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

Product data sheet Rev. 5.5 — 26 April 2016 54 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flowing from the ma ster to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.

7.21.1 Features

•Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave).

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses.

•Synchronous serial communication.

•Master or slave operation.

•8-frame FIFOs for both transmit and receive.

•4-bit to 16-bit frame.

•DMA transfers suppor te d by GPDM A.

7.22 I2C-bus serial I/O controllers

The LPC178x/7x contain three I2C-bus controllers.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C is a mu lti-m a ste r bu s and ca n be

controlled by more than one bus master connected to it.

7.22.1 Features

•All I2C-bus controllers can use stan dard GPIO pins with bit rates of up to 400 kbit/s

(Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of

up to 400 kbit/s.

•The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0

using pins P5[2] and P5[3].

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with differ ent bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer.

•The I2C-bus can be used for test an d diagnostic purposes.

•Both I2C-bus controllers support multiple address recognition and a bus monitor

mode.

Product data sheet Rev. 5.5 — 26 April 2016 55 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.23 I2S-bus serial I/O controllers

The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard

communication interface for digital audio applications.

The I2S-bus specificatio n defines a 3-wire serial bus using one da ta line, one clock line,

and one word select signal. The basic I2S connection has one master, which is always the

master , and one slave. The I2S interface on the LPC178x/7x provides a separate transmit

and receive channel, each of which can operate as either a master or a slave.

7.23.1 Features

•The interface has sep arate input/output channels each of which can o perate in master

or slave mode.

•Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

•Mono and stereo audio data supported.

•The sampling frequency can range from 16 kHz to 48 kHz ( 16, 22.05, 32, 44.1,

48) kHz.

•Configurable word select period in master mode (separately for I2S input and output).

•Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

•Generates interrupt requests when buffer levels cross a programmable boundary.

•Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

•Controls include reset, stop and mute optio ns separately for I2S input and I2S output.

7.24 CAN controller and acceptance filters

The LPC178x/7x contain one CAN controller with two ch annels.

The Controller Area Network (C AN) is a serial communications protocol which efficiently

supports distributed real-time control with a very high level of security. Its domain of

application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the

device to be used as a ga teway, switch, or router between two of CAN buses in industrial

or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN

Library block, but the 8-bit registers of those devices have been combined in 32-bit words

to allow simult aneous access in the ARM environment. Th e main operationa l dif ference is

that the recognition of received Identifiers, known in CAN terminology as Acceptance

Filtering, has been removed from the CAN controllers and centralized in a global

Acceptance Filter.

7.24.1 Features

•Two CAN controllers and buses.

•Data rates to 1 Mbit/s on each bus.

•32-bit register and RAM access.

•Compatible with CAN specification 2.0B, ISO 11898-1.

Product data sheet Rev. 5.5 — 26 April 2016 56 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

•Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

buses.

•Acceptance Filter can provide FullC AN-style automatic reception for selected

Standard Identifiers.

•FullCAN messages can generate interrupts.

7.25 General purpose 32-bit timers/external event counters

The LPC178x/7x include four 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture input s to trap the timer value when

an input signal transitio ns, optionally generating an interrupt.

7.25.1 Features

•A 32-bit timer/counter with a progra mmable 32-bit prescaler.

•Counter or time r op er a tion .

•Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

•Up to two match registers can be used to generate timed DMA requests.

7.26 Pulse Width Modulator (PWM)

The LPC178x/7x contain two standard PWMs.

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC178x/7x. The Timer is designed to count

cycles of the system derived clock and optionally switch pins, generate interrupts or

perform other actions when spe cified timer values occur , based on seven match registers.

The PWM function is in addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires

three non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Product data sheet Rev. 5.5 — 26 April 2016 57 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Two match registers can be used to provide a single edge controlled PWM output. One

match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon

match. The other match register controls the PWM edge position. Additional single edge

controlled PWM ou tp u ts require on ly on e m atc h register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM output s will all have a

rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edge s co ntr o lled .

Again, the PWMMR0 match register controls the PWM cycle rate. The other match

registers control the two PWM edge positions. Additional double edge controlled PWM

outputs require only two match registers each, since the repetition rate is the same for all

PWM outputs.

With double edge controlled PWM outputs, specific match registers control the rising and

falling edge of the output. This allows both positive going PWM pulses (when the rising

edge occurs prior to the falling edge), and negative going PWM pulses (when the falling

edge occurs prior to the rising edge).

7.26.1 Features

•LPC178x/7x has two PWM blocks with Counter or Timer operation (may use the

peripheral clock or one of the capture inputs as the clock source).

•Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless the

output is a constant low. Double edge controlled PWM outputs can have either edge

occur at any position within a cycle. This allows for both positive going and negative

going pulses.

•Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will

occur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to preven t ge ne ra tio n of

erroneous pulses. Sof tware must ‘release’ new ma tch values before they can b ecome

effective.

•May be used as a stand ard 32-bit timer /counter with a programma ble 32-bit p rescaler

if the PWM mode is not enabled.

7.27 Motor control PWM

The LPC178x/7x contain one motor control PWM.

The motor control PWM is a specialized PWM supporting 3-phase motors and other

combinations. Feedback input s are provided to automatically sense rotor position and use

that information to ramp sp eed up or down. An abort input is also provided that causes the

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NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

PWM to immediately release all motor drive outputs. At the same time, the motor control

PWM is highly configurable for other generalized timing, counting, capture, and compare

applications.

The maximum PWM speed is determined by the PWM resolution (n) and the operating

frequency f: PWM speed = f/2n (see Table 8).

7.28 Quadrature Encoder Interface (QEI)

Remark: The QEI is available on parts LPC1788/87/86 and LPC1778/77/76

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two sign als, th e use r can track th e position, d ire ction of rotation, and

velocity. In addition, a third channel, or index signal, can be used to reset the position

counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

7.28.1 Features

•Tracks encoder position.

•Increments/decrements depending on direction.

•Programmable for 2 or 4 position counting.

•Velocity capture using built-in timer.

•Velocity compare function with “less than” interrupt.

•Uses 32-bit regis ter s for po sitio n an d ve loc ity.

•Three position co mpare registers with interrup ts.

•Index counter for revolution counting.

•Index compare regis te r with int er ru p ts.

•Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

•Digital filter with programmable delays for encoder input signals.

•Can accept decoded signal inputs (clk and direction).

•Connected to APB.

7.29 ARM Cortex-M3 system tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval. In the LPC178x/7x, this timer can be

clocked from the internal AHB clock or from a device pin.

Table 8. PWM speed at operating frequency 120 MHz

PWM resolution PWM speed

6 bit 1.875 MHz

8 bit 0.468 MHz

10 bit 0.117 MHz

Product data sheet Rev. 5.5 — 26 April 2016 59 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.30 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if sof tware fails to periodically

service it within a programmable time window.

7.30.1 Features

•Internally resets chip if not periodically reloaded during the programmable time-out

period.

•Optional windowed operation re quires reload to occur between a minimum and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is

always running if the watchdog timer is enabled.

7.31 RTC and backup registers

The R TC is a set of counte rs for measur ing time when system power is on, and optiona lly

when it is of f. The RTC on the L PC178x/7x is designed to have very low power

consumption. The RTC will typically run from the main chip power supply conserving

battery power while the rest of the de vice is powered up. When operating from a battery,

the RTC will continue working down to 2.1 V. Battery power can be provided from a

standard 3 V lithium button cell.

An ultra-low power 32 kHz oscillator provides a 1 Hz clock to the time counting portion of

the RTC, moving most of the power consumption out of the time counting function.

The R TC includes a calibration mechanism to allow fine-tuning the count rate in a way

that will provide less than 1 second per day error when operated at a const ant voltage and

temperature.

The RTC contains a small set of backup registers (20 bytes) for holding dat a while the

main part of the LPC178x/7x is powered off.

The R TC includes an alarm function that can wake up the LPC178x/7x from all reduced

power modes with a time resolution of 1 s.

7.31.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra low power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

Day of Year.

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NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

•Dedicated power supply pin can be connected to a batte ry or to the main 3.3 V.

•Periodic interrup t s can be gene rated fro m increment s of a ny field of th e time registe rs.

•Backup registe rs (20 bytes) powered by VBAT.

•RTC power supply is isolated from the rest of the chip.

7.32 Event monitor/recorder

The event monitor/recor der allows recording of tampering events in sealed product

enclosures. Sensors report any attempt to open the enclosure, or to tamper with the

device in any other way. The event monitor/recorder stores records of such events when

the device is powered only by the backup battery.

7.32.1 Features

•Supports three digital event inputs in the VBAT power do m ain .

•An event is defined as a level change at the digital event inputs.

•For each event channel, two timestamps mark the first and the last occurrence of an

event. Each channe l also has a dedicated counter tr acking the total numb er of events.

Timestamp values are taken from the RTC.

•Runs in VBAT power domain, independent of system power supply. The

event/reco rd er /m o nito r can th er ef or e op erate in Deep power -d own mode.

•Very lo w po we r co nsu m pt ion .

•Interrupt available if system is running.

•A qualified event can be used as a wake-up trigger.

•State of event interrupts accessible by software through GPIO.

7.33 Clocking and power control

7.33.1 Crystal oscillators

The LPC178x/7x include four independent oscillators. These are the main oscillator, the

IRC oscillator, the watchdog oscillator, and the RTC oscillator.

Following reset, the LPC178x/7x will operate from the Internal RC oscillator until switched

by software. This allows systems to operate without any external crystal and the boot

loader code to operate at a known frequency.

See Figure 7 for an overview of the LPC178x/7x clock generation.

Product data sheet Rev. 5.5 — 26 April 2016 61 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.33.1.1 Internal RC oscillator

The IRC may be used as the clock that drives the PLL and subsequently the CPU. The

nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire

voltage and temperature range.

Upon power-up or any chip reset, the LPC178x/7x use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.33.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or withou t using the

PLL. The main oscillator also provides the clock source for the alternate PLL1.

The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequenc y can be

boosted to a highe r fr equen cy, up to the maximum CPU o peratin g freque ncy, by the main

PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock

frequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The

clock frequency for each peripheral can be selected individually and is referr ed to as

PCLK. Refer to Section 7.33.2 for additional information.

Fig 7. LPC178x/7x clock generation block diagram

MAIN PLL0

IRC oscillator

main oscillator

(osc_clk)

CLKSRCSEL

(system clock select)

sysclk

pll_clk

CCLKSEL

(CPU clock select)

002aaf531

pll_clk

ALT PLL1

CPU CLOCK

DIVIDER

alt_pll_clk

cclk

EMC

CLOCK DIVIDER

pclk

Peripheral

CLOCK DIVIDER

emc_clk

sysclk

alt_pll_clk

pll_clk

USBCLKSEL

(USB clock select)

USB

CLOCK DIVIDER usb_clk

sysclk

LPC178x/7x

Product data sheet Rev. 5.5 — 26 April 2016 62 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.33.1.3 RTC oscillator

The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can

be output on the CLKOUT pin in order to allow trimming the RTC oscillator without

interference from a probe.

7.33.1.4 Watchdog oscillator

The W atchdog T imer has a dedicated watchdog oscillator that provides a 500 kHz clock to

the Watchdog Timer. The watchdog oscillator is always running if the Watchdog Timer is

enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to

allow observe its frequency.

In order to allow Watchdog Timer oper ation with minimum power consu mption, which can

be important in reduced power modes, the Watchdog oscillator frequency is not tightly

controlled. The Watchdog oscillator frequency will vary over temperature and power

supply within a particular part, and may vary by processing across different parts. This

variation should be taken into acc ou n t whe n dete rm in ing Watchdog reload values.

Within a particular part, temperature and power supply variations can pr oduce up to a

17 % frequency vari ation. Frequency variation be tween devices under the same

operating conditions can be up to 30 %.

7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1)

PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally

identical but have somewhat different input possibilities and output connections. These

possibilities are shown in Figure 7. The Main PLL can receive its input from either the IRC

or the main oscillator and can potentially be used to provide the clocks to nearly

everything on the device. The Alternate PLL receives its input only from the main oscillator

and is intended to be used as an alternate source of clocking to the USB. The USB has

timing needs that may not always be filled by the Main PLL.

Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the

USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB

clock through that route. The source for each clock must be selected via the CLKSEL

registers and can be further reduced by clock dividers as needed.

PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only

the Main PLL is used, then its output frequency must be an integer multiple of all other

clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring

an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled

Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional

dividers to bring the output down to the desired frequencies. The minimum output divider

value is 2, insuring that the output of the PLLs have a 50 % duty cycle.

If the USB is used, the possibilities for the CPU clock and other clocks will be limited by

the requirements that the frequency be precise and very low jitter, and that the PLL0

output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the

operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in

conjunction with the PLL can me et the precision and jitter specifications for USB. It is du e

to these limitations that the Alternate PLL is provided.

Product data sheet Rev. 5.5 — 26 April 2016 63 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The alternate PLL accepts an input clock frequency from the main oscillator in the range

of 10 MHz to 25 MHz only. When used as the USB clock, the input fre quency is multiplied

up to a multiple of 48 MHz (192 MHz or 288 MHz as described above).

7.33.3 Wake-up timer

The LPC178x/7x begin operation at power-up and when awakened from Power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the main oscillator or the PLL is needed by the application, software

will need to enable these features and wait for them to stabilize before they are used as a

clock source.

When the main oscillator is initially activated, the wake-up timer allows sof twa re to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The wake-up timer monitors the cryst al oscillator to check whether it is safe to begin code

execution. When power is applied to the chip, or when some event caused the chip to exit

Power-down mode, some time is required for the oscillator to produce a signal of suf ficient

amplitude to drive the clock logic. Th e amount of time depends on many factors, includ ing

the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical

characterist ics (if a qu ar tz crystal is used), as well as any other external circuitry (e.g.,

capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.33.4 Power control

The LPC178x/7x support a variety of power control features. There are four special

modes of processor power reduction: Sleep mode, Deep-sleep mode, Powe r-down mode,

and Deep power-down mode. The CPU clock rate may also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This allows a trade-off of power versus processing speed based on application

requirements. In addition, the peripheral power control allows shutting down the clocks to

individual on-chip peripherals, allowing fine tunin g of power consumption by eliminating all

dynamic power use in a ny peripherals that are not required for the application. Each of the

peripherals has its own clock divider which provides even better power control.

The integrated PMU (Power Management Unit) automatically adjusts internal regulators

to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep

power-down modes.

The LPC178x/7x also implement a separate power domain to allow turning off power to

the bulk of the device while maintaining operation of the RTC and a small set of registers

for storing data during any of the power-down modes.

7.33.4.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need any special sequence other than re-enabling the clock to the ARM

core.

Product data sheet Rev. 5.5 — 26 April 2016 64 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

In Sleep mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution . Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

The DMA controller can conti nue to wo rk in Sleep m ode and ha s access to th e per iphera l

RAMs and all peripheral registers. The flash memory and the main SRAM are not

available in Sleep mode, they are disabled in order to save power.

Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.

7.33.4.2 Deep-sleep mode

In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM value s ar e

preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.

The output of the IRC is disabled but the IRC is not power ed down to allow fast wake-up.

The RTC oscillator is not stopped because the RTC interrupts may be used as the

wake-up source. The PLL is automatically turned off and disconnected. The clock divider

registers are automa tically reset to zero.

The Deep-sleep mode can be terminated and normal operation resumed by either a

Reset or certain specific interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power

consumptio n to a ve ry low value . Pow er to the flash memory is left on in Deep-sleep

mode, allowing a very quick wake-up.

Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0

through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,

an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input

pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled.

Wake-up will occur whenever any enabled interrupt occurs.

On wake-up from Deep-sleep mode, the code execution and peripherals activities will

resume after four cycles expire if the IRC was used before entering Deep- sleep mode. If

the main external oscillator was used, the code execution will resume when 4096 cycles

expire. PLL and clock dividers need to be reconfigured accordingly.

7.33.4.3 Power-down mode

Power-down mode does everything that Deep-sleep mode does but also turns off th e

power to the IRC oscillator and the flash memory. This saves more power but requires

waiting for resumption of flash operation before execution of code or data access in the

flash memory can be accomplished.

When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are

stopped. The RTC remains running if it has been enabled and RTC interrupts may be

used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are

automatically turned off and the clock selection multiplexers are set to use the system

clock sysclk (the reset state). The clock divider control registers are automatically reset to

zero. If the Watchdog timer is running, it will continue running in Power-down mode.

Product data sheet Rev. 5.5 — 26 April 2016 65 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60 s to start-up. After this, four IRC cycles will expire before the

code execution can then be resumed if the code was running from SRAM. In the

meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the

100 s flash start-up time. When it times out, access to the flash will be allowed. Users

need to reconfigure the PLL and clock dividers accordingly.

7.33.4.4 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

RTC module and the RESET pin.

To optimize power conservation, the user has the additional option of turning off or

retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn

off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the

VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before

device operation can be restarted.

The LPC178x/7x can wake up from Deep power-down mode via the RESET pin or an

alarm match event of the RTC.

7.33.4.5 Wake-up Interrupt Controller (WIC)

The WIC allows the CPU to auto matically wake up fro m any ena bled pr iority inte rrup t that

can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep

power-down modes.

The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). Wh en

the CPU enters Deep-sleep, Powe r-down, o r Deep po wer- do wn mod e, the NVIC se nds a

mask of the current interrupt situation to the WIC.This mask includes all of the interrupts

that are both enabled and of sufficient priority to be serviced immediately. With this

information, the WIC simply notices when one of the interrupts has occurred and then it

wakes up the CPU.

The WIC eliminates the need to periodically wake up the CPU and poll the interrupts

resulting in addit ion a l powe r savin gs.

7.33.5 Peripheral power control

A power control for peripherals feature allows individual peripherals to be turned off if they

are not needed in the application, resulting in additional power savings.

7.33.6 Power domains

The LPC178x/7x provide two independent power domains that allow the bulk of the

device to have power removed while maintaining operation of the RTC and the backup

registers.

On the LPC178x/7x, I/O pads are powered by VDD(3V3), while VDD(REG)(3V3) powers the

on-chip voltage regulator which in turn provides power to the CPU and most of the

peripherals.

Depending on the LPC178x/7x application, a design can use two power options to

manage power consumption.

Product data sheet Rev. 5.5 — 26 April 2016 66 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

The first option assumes that power consumption is not a concern and the de sign ties the

VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only on e 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplie s; a 3.3 V supply for the I/O pads (VDD(3V3)) and

a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator

powered independently from the I/O p ad ring enables sh utting do wn of the I/O p a d power

supply “on the fly” while the C P U and peripherals stay active.

The VBAT pin supplies power only to the RTC domain. The RTC operates at very low

power, which can be supplied by an external battery. The device core power

(VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. There is no

power drain from the RTC battery when VDD(REG)(3V3) is at nominal levels and

VDD(REG)(3V3) > VBAT.

Fig 8. Power distribu tio n

REAL-TIME CLOCK

BACKUP REGISTERS

REGULATOR

32 kHz

OSCILLATOR

POWER

SELECTOR

ULTRA-LOW

POWER

REGULATOR

RTC POWER DOMAIN

MAIN POWER DOMAIN

002aaf530

RTCX1

VBAT

(typical 3.0 V)

DD(REG)(3V3)

(typical 3.3 V)

RTCX2

DD(3V3)

to memories,

peripherals,

oscillators,

PLLs

to core

to I/O pads

ADC

DAC

ADC POWER DOMAIN

DDA

VREFP

SSA

LPC178x/7x

Product data sheet Rev. 5.5 — 26 April 2016 67 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.34 System control

7.34.1 Reset

Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset,

Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip Reset by any source , once the operating

voltage attains a usable level, starts the Wake-up timer (see description in

Section 7.33.3), causing reset to re main asserted until the external Reset is de-asserted,

the oscillator is running, a fixed number of clocks have passed, and the flash controller

has completed its initialization.

When the internal Reset is removed, th e processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.34.2 Brownout detection

The LPC178x/7x include 2-stage monitoring of the volt age on the VDD(REG)(3V3) pins. If this

voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored

Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable

signal by reading a dedicated status register.

The second stage of low-voltage detection asserts a reset to inactivate the LPC178x/7x

when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V (typical). This reset prevent s

alteration of the flash as operation of th e va rio us elem en ts of the chip wou ld oth er wise

become unreliable due to low voltage. The BOD circuit maintains this reset down below

1 V, at which point the power-on reset circuitry maintains the overall reset.

Both the 2.2 V and 1.85 V thresholds include some hyster esis. In normal operation, this

hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

7.34.3 Code security (Code Read Protection - CRP)

This feature of the LPC178x/7x allows user to enable different levels of security in the

system so that access to the on-chip fla sh and use of the JTAG and ISP can be restricted.

When needed, CRP is invoke d by pr og ram m ing a specific pattern into a dedicated flash

location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and flash field updates are needed but all sectors can not be erased.

CRP2 disables ac cess to ch ip via th e JTAG and on ly allows full fla sh er as e an d upd at e

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too .

It is up to the user’s application to provide (if needed) flash update mechanism using IAP

calls or call reinvoke ISP command to enable flash update via UART0.

Product data sheet Rev. 5.5 — 26 April 2016 68 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.34.4 APB interface

The APB peripherals are split into two separate APB buses in order to distribute the bus

bandwidth and thereby re ducing stalls caused by contention be tween the CPU and the

GPDMA controller.

7.34.5 AHB multilayer matrix

The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction

(I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the

main (64 kB) SRAM, and the Boot ROM. The GPDMA can also access all of these

memories. Additionally, the matrix connects the CPU system bus and all of the DMA

controllers to th e var io us perip h er al fu nc tion s.

7.34.6 External interrupt inputs

The LPC178x/7x include up to 30 edge sensitive interrupt inputs combined with one level

sensitive external interrupt input as select able pin function. The external interrupt input

can optionally be used to wake up the processor fro m Power-down mode.

7.34.7 Memory mapping control

The Cortex-M3 incorp orates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 128 word (512 byte) boundary because the

NVIC on the LPC178x/7x is configured for 128 total interrupts.

7.35 Debug control

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and

trace functions are su pported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four

watch points.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 5.5 — 26 April 2016 69 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on the required shelf lifetime. Please refer to the JEDEC spec for further details.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Table 9. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V

VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V

VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V

Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V

Vi(VREFP) input voltage on pin VREFP 0.5 +4.6 V

VIA analog input voltage on ADC related

pins 0.5 +5.1 V

VIinput voltage 5 V tolerant digital

I/O pins;

VDD(3V3) 2.4V

[2] 0.5 +5.5 V

VDD(3V3) 0 V 0.5 +3.6 V

other I/O pins [2][3] 0.5 VDD(3V3) +

0.5 V

IDD supply current per supply pin - 100 mA

ISS ground current per ground pin - 100 mA

Ilatch I/O latch-up current (0.5VDD(3V3)) < VI

< (1.5VDD(3V3));

Tj < 125 C

- 100 mA

Tstg storage temperature non-operating [4] 65 +150 C

Ptot(pack) total power dissipation (per package) ba sed on package

heat transfer, not

device power

consumption

-1.5W

VESD electrostatic discharge voltage human body

model; all pins [5] -4000V

Product data sheet Rev. 5.5 — 26 April 2016 70 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

9. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

Table 10. Thermal characteristics

VDD = 3.0 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified;

Symbol Parameter Min Typ Max Unit

Tj(max) maximum juncti on

temperature - - 125 C

Table 11. Thermal resistance (LQFP packages)

Tamb =





C to +85



C unless otherwise specified.

Symbol Conditions Thermal resistance in C/W ±15 %

LQFP208 LQFP144

ja JEDEC (4.5 in  4 in)

0 m/s 27.4 31.5

1 m/s 25.7 28.1

2.5 m/s 24.4 26.2

Single-layer (4.5 in  3 in)

0 m/s 35.4 43.2

1 m/s 31.2 35.7

2.5 m/s 29.2 32.8

jc - 8.8 7.8

jb - 15.4 13.8

Table 12. Therm al resistance value (TFBGA packages)

Tamb =





C to +85



C unless otherwise specified.

Symbol Conditions Thermal resistance in C/W ±15 %

TFBGA208 TFBGA180

ja JEDEC (4.5 in  4 in)

0 m/s 41 45.5

1 m/s 35 38.3

2.5 m/s 31 33.8

8-layer (4.5 in  3 in)

0 m/s 34.9 38

1 m/s 30.9 33.5

2.5 m/s 28 29.8

jc - 8.3 8.9

jb - 13.6 12

TjTamb PDRth j a–

+=

Product data sheet Rev. 5.5 — 26 April 2016 71 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

10. Static characteristics

Table 13. Static characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Supply pins

VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V

VDD(REG)(3V3) regulator supply voltage

(3.3 V) 2.4 3.3 3.6 V

VDDA analog 3.3 V pad supply

voltage [3] 2.7 3.3 3.6 V

Vi(VBAT) input voltage on pin

VBAT [4] 2.1 3.0 3.6 V

Vi(VREFP) input voltage on pin

VREFP [3] 2.7 3.3 VDDA V

IDD(REG)(3V3) regulator supply current

(3.3 V) ac ti ve mode; code

while(1){}

executed from flash; all

peripherals disabled

PCLK = CCLK/4

CCLK = 12 MHz; PLL

disabled [5][6] -7-mA

CCLK = 120 MHz; PLL

enabled [5][7] -51-mA

active mode; code

while(1){}

executed from flash; all

peripherals enabled;

PCLK = CCLK/4

CCLK = 12 MHz; PLL

disabled [5][6] 14

CCLK = 120 MHz; PLL

enabled [5][7] 100 mA

Sleep mode [5][8] -5-mA

Deep-sleep mode [5][9] -550-A

Power-down mode [5][9] -280-A

IBAT battery supply current RTC running;

part powered down;

VDD(REG)(3V3) =0 V;

Vi(VBAT) = 3.0 V;

VDD(3V3) = 0 V.

[10] -

1- A

part powered;

VDD(REG)(3V3) = 3.3 V;

Vi(VBAT) = 3.0 V

[11] <10 nA

Product data sheet Rev. 5.5 — 26 April 2016 72 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Standard port pins, RESET

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled - 0.5 10 nA

IIH HIGH-level input

current VI=V

DD(3V3); on-chip

pull-down resistor

disabled

- 0.5 10 nA

IOZ OFF-state output

current VO=0V; V

O=V

DD(3V3);

on-chip pull-up/down

resistors disabled

- 0.5 10 nA

VIinput voltage pin configured to provide

a digital function [15][16]

[17] 0- 5.0V

VOoutput voltage output active 0 - VDD(3V3) V

VIH HIGH-level input

voltage 0.7VDD(3V3) --V

VIL LOW-level input voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage IOH =4 mA VDD(3V3) 

0.4 --V

VOL LOW-level output

voltage IOL =4 mA --0.4V

IOH HIGH-level output

current VOH =V

DD(3V3) 0.4 V 4--mA

IOL LOW-level output

current VOL =0.4V 4--mA

IOHS HIGH-level short-circuit

output current VOH =0V [18] --45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD(3V3) [18] --50mA

Ipd pull-down curre nt VI=5V 10 50 150 A

Ipu pull-up current VI=0V 15 50 85 A

VDD(3V3) <V

I<5V 000A

I2C-bus pins (P0[27] and P0[28])

VIH HIGH-level input

voltage 0.7VDD(3V3) --V

VIL LOW-level input voltage - - 0.3VDD(3V3) V

Vhys hysteresis voltage - 0.05 

VDD(3V3)

-V

VOL LOW-level output

voltage IOLS =3 mA --0.4V

ILI input leakage current VI=V

DD(3V3) [19] -24A

VI=5V - 10 22 A

USB pins

IOZ OFF-state output

current 0V<V

I<3.3V [20] --10 A

VBUS bus supply voltage [20] --5.25V

Table 13. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 5.5 — 26 April 2016 73 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] For USB operation 3.0 V  VDD(3V3)  3.6 V. Guaranteed by design.

[3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.

[4] The RTC typically fails when Vi(VBAT) drops below 1.6 V.

[5] VDD(REG)(3V3) = 3.3 V; Tamb =25C for all power consumption measurements.

[6] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470).

[7] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470).

[8] IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4.

[9] BOD disabled.

[10] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 0; Tamb =25C.

[11] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; Tamb =25C.

[12] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb =25C.

[13] VDDA = 3.3 V; Tamb =25C.

[14] Vi(VREFP) = 3.3 V; Tamb =25C.

[15] Including voltage on outputs in 3-state mode.

[16] VDD(3V3) supply voltages must be present.

[17] 3-state outputs go into 3-state mode in Deep power-down mode.

[18] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[19] To VSS.

[20] 3.0 V  VDD(3V3)  3.6 V.

VDI differential input

sensitivity voltage (D+) (D)[20] 0.2--V

VCM differential common

mode voltage range includes VDI range [20] 0.8 - 2.5 V

Vth(rs)se single-ended recei v er

switching threshold

voltage

[20] 0.8 - 2.0 V

VOL LOW-level output

voltage for

low-/full-speed

RL of 1.5 k to 3.6 V [20] --0.18V

VOH HIGH-level output

voltage (driven) for

low-/full-speed

RL of 15 k to GND [20] 2.8 - 3.5 V

Ctrans transceiver capacitance pin to GND [20] --20pF

Oscillator pins (see Section 14.2)

Vi(XTAL1) input voltage on pin

XTAL1 0.5 1.8 1.95 V

Vo(XTAL2) output voltage on pin

XTAL2 0.5 1.8 1.95 V

Vi(RTCX1) input voltage on pin

RTCX1 0.5 - 3.6 V

Vo(RTCX2) output voltage on pin

RTCX2 0.5 - 3.6 V

Table 13. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 5.5 — 26 April 2016 74 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

10.1 Power consumption

Conditions: BOD disabled.

Fig 9. Deep-sleep mode: Typical regulator su pply current IDD(REG)(3V3) versus

temperature

Conditions: BOD disabled.

Fig 10. Power-d own mode: Typical regulator supply current IDD(REG)(3V3) versus

temperature

temperature (°C)

-40 853510 60-15

002aah051

0.7

1.1

1.5

0.3

VDD(REG)(3V3) = 3.6 V

3.3 V

3.0 V

2.4 V

IDD(REG)(3V3)

(mA)

temperature (°C)

-40 853510 60-15

002aah052

300

600

900

VDD(REG)(3V3) = 3.6 V

3.3 V

3.0 V

2.4 V

IDD(REG)(3V3)

(μA)

Product data sheet Rev. 5.5 — 26 April 2016 75 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD(REG)(3V3) = VDDA = VDD(3V3) = 0; VBAT = 3.0 V.

Fig 11. Part powered off: Typical battery supply current (IBAT) versus temperature

002aah074

temperature (°C)

-40 853510 60-15

0.8

1.6

0.4

1.2

2.0

IBAT

(μA)

Product data sheet Rev. 5.5 — 26 April 2016 76 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

10.2 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the PCONP register. All

other blocks are disabled and no code is executed. Measured on a typical sample at

Tamb =25C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz,

48 MHz, and 12 0 MHz.

The combined current of several peripherals running at the same time can be less than

the sum of each individual peripheral current measured separately.

Table 14. Power consumption for individual analog an d digital blocks

Tamb =25



C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4.

Peripheral

Conditions Typical supply current in mA

12 MHz[1] 48 MHz[1] 120 MHz[2]

Timer0 - 0.01 0.06 0.15

Timer1 - 0.02 0.07 0.16

Timer2 - 0.02 0.07 0.17

Timer3 - 0.01 0.07 0.16

Timer0 + Timer1 + Timer2 + Timer3 - 0.07 0.28 0.67

UART0 - 0.05 0.19 0.45

UART1 - 0.06 0.24 0.56

UART2 - 0.05 0.2 0.47

UART3 - 0.06 0.23 0.56

USART4 - 0.07 0.27 0.66

UART0 + UART1 + UART2 + UART3 +

USART4 - 0.29 1.13 2.74

PWM0 + PWM1 - 0.08 0.31 0.75

Motor control PWM - 0.04 0.15 0.36

I2C0 - 0.01 0.03 0.08

I2C1 - 0.01 0.03 0.1

I2C2 - 0.01 0.03 0.08

I2C0 + I2C1 + I2C2 - 0.02 0.1 0.26

SSP0 - 0.03 0.1 0.26

SSP1 - 0.02 0.11 0.27

DAC - 0.3 0.31 0.33

ADC (12 MHz clock) - 1.51 1.61 1.7

CAN1 - 0.11 0.44 1.08

CAN2 - 0.1 0.4 0.98

CAN1 + CAN2 - 0.15 0.59 1.44

DMA PCLK = CCLK 1.1 4.27 10.27

QEI - 0.02 0.11 0.28

GPIO - 0.4 1.72 4.16

LCD - 0.99 3.84 9.25

I2S - 0.04 0.18 0.46

Product data sheet Rev. 5.5 — 26 April 2016 77 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470).

[2] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470).

EMC - 0.82 3.17 7.63

RTC - 0.01 0.01 0.05

USB + PLL1 - 0.62 0.97 1.67

Ethernet PCENET bit set

to 1 in the

PCONP register

0.54 2.08 5.03

Table 14. Power consumption for individual analog an d digital blocks …continued

Tamb =25



C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4.

Peripheral

Conditions Typical supply current in mA

12 MHz[1] 48 MHz[1] 120 MHz[2]

Product data sheet Rev. 5.5 — 26 April 2016 78 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

10.3 Electrical pin characteristics

Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.

Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.

Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL

IOH (mA)

0 24168

002aaf112

2.8

2.4

3.2

3.6

VOH

(V)

2.0

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf111

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 5.5 — 26 April 2016 79 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.

Fig 14. Typical pull-up current Ipu versus input voltage VI

Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.

Fig 15. Typical pull-down current Ipd versus input voltage VI

0 54231

002aaf108

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

VI (V)

002aaf109

VI (V)

0 53241

Ipd

(μA)

−10

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 5.5 — 26 April 2016 80 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11. Dynamic characteristics

11.1 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

[1] EEPROM clock frequency = 375 kHz. Programming/erase times increase with decreasing EEPROM clock

frequency.

Table 15. Flash ch aracteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance - [1] 10000 100000 - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

ter erase time secto r or multiple

consecutive sectors 95 100 105 ms

tprog programming

time -[2] 0.95 1 1.05 ms

Table 16. EEPROM characteristics

Tamb =





Cto+85



C; VDD(REG)(3V3) = 2.7 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency - 200 375 400 kHz

Nendu endurance - 100000 500000 - cycles

tret retention time powered 10 - - years

unpowered 10 - - years

ter erase time 64 bytes [1] -1.8-ms

tprog programming

time 64 bytes [1] -1.1-ms

Product data sheet Rev. 5.5 — 26 April 2016 81 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.2 External memory interface

Table 17. Dy namic characteristics: Static external memory interface

CL=30pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter[1] Conditions[1] Min Typ Max Unit

Read cycle parameters[2]

tCSLAV CS LOW to address

valid time RD12.7 3.5 4.7 ns

tCSLOEL CS LOW to OE LOW

time RD2[3] 2.7 + Tcy(clk) 

WAITOEN 3.4 + Tcy(clk) 

WAITOEN 4.6 + Tcy(clk) 

WAITOEN ns

tCSLBLSL CS LOW to BLS LOW

time RD3; PB = 1 [3] 2.8 3.8 5.1 ns

tOELOEH OE LOW to OE HIGH

time RD4[3] (WAITRD 

WAITOEN + 1) 

Tcy(clk)  2.26

(WAITRD 

WAITOEN + 1) 

Tcy(clk)  2.83

(WAITRD 

WAITOEN + 1) 

Tcy(clk)  3.7

tam memory access time RD5[3][4] (WAITRD 

WAITOEN + 1) 

Tcy(clk)  8.6

(WAITRD 

WAITOEN + 1) 

Tcy(clk)  11.9

(WAITRD 

WAITOEN + 1) 

Tcy(clk)  18.0

th(D) data input hold time RD6[3][5] 4.1 5.8 - ns

tCSHBLSH CS HIGH to BLS HIGH

time PB = 1 2.8 3.7 5.1 ns

tCSHOEH CS HIGH to OE HIGH

time [3] 2.7 3.5 4.6 ns

tOEHANV OE HIGH to address

invalid time [3] 0.1 0.1 0.16 ns

tdeact deactivation time RD7[3] -3.4 4.7 ns

Write cycle parameters[2]

tCSLAV CS LOW to address

valid time WR12.7 3.5 4.7 ns

tCSLDV CS LOW to data valid

time WR22.8 3.9 5.1 ns

tCSLWEL CS LOW to WE LOW

time WR3; PB =1 [3] 2.7 + Tcy(clk) 

(1 + WAITWEN) 3.5 + Tcy(clk) 

(1 + WAITWEN) 4.6 + Tcy(clk) 

(1 + WAITWEN) ns

tCSLBLSL CS LOW to BLS LOW

time WR4; PB = 1 [3] 2.8 3.9 5.1 ns

tWELWEH WE LOW to WE HIGH

time WR5; PB =1 [3] (WAITWR 

WAITWEN + 1) 

Tcy(clk)  2.3

(WAITWR 

WAITWEN + 1) 

Tcy(clk)  2.8

(WAITWR 

WAITWEN + 1) 

Tcy(clk)  3.8

tBLSLBLSH BLS LOW to BLS HIGH

time PB = 1 [3] (WAITWR 

WAITWEN + 3) 

Tcy(clk)  2.6

(WAITWR 

WAITWEN + 3) 

Tcy(clk)  3.4

(WAITWR 

WAITWEN + 3) 

Tcy(clk)  4.9

tWEHDNV WE HIGH to data

invalid time WR6; PB =1 [3] 2.5 + Tcy(clk) 3.3 + Tcy(clk) 4.3 + Tcy(clk) ns

tWEHEOW WE HIGH to end of

write time WR7; PB = 1 [3][6] Tcy(clk)  2.7 Tcy(clk)  3.4 Tcy(clk)  4.6 ns

tBLSHDNV BLS HIGH to data

invalid time PB = 1 2.7 3.6 4.8 ns

tWEHANV WE HIGH to address

invalid time PB = 1 [3] 2.4 + Tcy(clk) 3.0 + Tcy(clk) 3.9 + Tcy(clk) ns

Product data sheet Rev. 5.5 — 26 April 2016 82 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Parameters are shown as RDn or WDn in Figure 16 as indicated in the Conditions column.

[2] Parameters specified for 40 % of VDD(3V3) for rising edges and 60 % of VDD(3V3) for falling edges.

[3] Tcy(clk) = 1/EMC_CLK (see LPC178x/7x User manual UM10470).

[4] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).

[5] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

[6] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).

tdeact deactivation time WR 8; PB = 0;

PB = 1 [3] 2.7 3.4 4.7 ns

tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [3] 2.8 + Tcy(clk) 

(1 + WAITWEN) 3.7 + Tcy(clk) 

(1 + WAITWEN) 5.1 + Tcy(clk) 

(1 + WAITWEN) ns

tBLSLBLSH BLS LOW to BLS HIGH

time WR10; PB = 0 [3] (WAITWR 

WAITWEN + 3) 

Tcy(clk)  2.6

(WAITWR 

WAITWEN + 3) 

Tcy(clk)  3.4

(WAITWR 

WAITWEN + 3) 

Tcy(clk)  4.9

tBLSHEOW BLS HIGH to end of

write time WR11; PB = 0 [3][6] 2.6 + Tcy(clk) 3.3 + Tcy(clk) 4.4 + Tcy(clk) ns

tBLSHDNV BLS HIGH to data

invalid time WR12;

PB = 0 [3] 2.7 + Tcy(clk) 3.6 + Tcy(clk) 4.8 + Tcy(clk) ns

Table 17. Dy namic characteristics: Static external memory interface …continued

CL=30pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter[1] Conditions[1] Min Typ Max Unit

Fig 16. External static memory read/write access (PB = 0)

EOR EOW

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

002aag214

Product data sheet Rev. 5.5 — 26 April 2016 83 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 17. External static memory read/write access (PB =1)

RD1WR1

EMC_Ax

WR8

WR4

WR8

EMC_CSx

RD2

RD7

RD4

EMC_OE

EMC_BLSx

EMC_WE

RD5

WR6

WR2

RD5

RD6

RD3

EOR EOW

EMC_Dx

WR3WR5WR7

002aag215

Fig 18. External static memory burst read cy cle

RD5RD5RD5RD5

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

002aag216

Product data sheet Rev. 5.5 — 26 April 2016 84 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] tclkndly represents tclk0dly when EMC_CLKOUT0 clocks SDRAM. tclkndlyrepresents tclk1dly when EMC_CLKOUT1 clocks SDRAM.

Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00

CL=10pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. tfbdly is programmable delay

value for the feedback clock that controls input data sampling; tclk0dly is programmable delay value for the EMC_ CLKOUT0

output; tclk1dly is programmable delay value for the EMC_CLKOUT1 output.

Symbol Parameter Min Typ Max Unit

Common to read and write cycles

Tcy(clk) clock cycle time [1] 12.5 - - ns

td(SV) chip select valid delay time [2] -t

clkndly + 4.2 tclk0dly + 6.2 ns

th(S) chip select hold time [2] tclkndly + 1.2 tclkndly + 1.8 - ns

td(RASV) row address strobe valid delay

time [2] -t

clkndly + 4.2 tclkndly + 6.2 ns

th(RAS) row address strobe hold time [2] tclkndly+ 1.3 tclkndly + 1.9 - ns

td(CASV) column address strobe valid

delay time [2] -t

clkndly + 4.2 tclkndly + 6.2 ns

th(CAS) column address strobe hold

time [2] tclkndly + 1.3 tclkndly + 1.9 - ns

td(WV) write valid delay time [2] -t

clkndly + 5.2 tclkndly + 7.7 ns

th(W) write hold time [2] tclkndly + 1.6 tclkndly + 2.4 ns

td(AV) address valid delay time [2] -t

clkndly + 5.0 tclkndly + 7.4 ns

th(A) address hold time [2] tclkndly + 1.1 tclkndly + 1.7 - ns

Read cycle parameters when EMC_CLKOUT0 used

tsu(D) data input set-up time 7.1 - tfbdly 4.8 - tfbdly -ns

th(D) data input hold time -1.9 + tfbdly -2.5 + tfbdly -ns

Read cycle parameters when EMC_CLKOUT1 used

tsu(D) data input set-up time 7.1 - tfbdly + (tclk1dly

- tclk0dly) 4.8 - tfbdly + (tclk1dly

- tclk0dly)-ns

th(D) data input hold time -1.9 + tfbdly -

(tclk1dly - tclk0dly) -2.5 + tfbdly -

(tclk1dly - tclk0dly) -ns

Write cycle parameters

td(QV) data output valid delay time [2] -t

clkndly + 5.8 tclkndly + 8.7 ns

th(Q) data output hold time [2] tclkndly  0.4 tclkndly + 0.6 - ns

Product data sheet Rev. 5.5 — 26 April 2016 85 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] tclkndly represents tclk0dly when EMC_CLKOUT0 clocks SDRAM. tclkndlyrepresents tclk1dly when EMC_CLKOUT1 clocks SDRAM.

Table 19. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00

CL=30pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. tfbdly is programmable delay

value for the feedback clock that controls input data sampling; tclk0dly is programmable delay value for the EMC_ CLKOUT0

output; tclk1dly is programmable delay value for the EMC_CLKOUT1 output.

Symbol Parameter Min Typ Max Unit

Common to read and write cycles

Tcy(clk) clock cycle time [1] 12.5 - - ns

td(SV) chip select valid delay time [2] -t

clkndly + 5.7 tclk0dly + 8.4 ns

th(S) chip select hold time [2] tclkndly + 0.5 tclkndly + 1.1 - ns

td(RASV) row address strobe valid delay

time [2] -t

clkndly + 5.8 tclkndly + 8.4 ns

th(RAS) row address strobe hold time [2] tclkndly+ 0.6 tclkndly + 1.2 - ns

td(CASV) column address strobe valid

delay time [2] -t

clkndly + 5.8 tclkndly + 8.4 ns

th(CAS) column address strobe hold

time [2] tclkndly + 0.6 tclkndly + 1.2 - ns

td(WV) write valid delay time [2] -t

clkndly + 6.6 tclkndly + 9. 9 n s

th(W) write hold time [2] tclkndly + 0.9 tclkndly + 1.7 ns

td(AV) address valid delay time [2] -t

clkndly + 6.6 tclkndly + 9.6 ns

th(A) address hold time [2] tclkndly + 0.4 tclkndly + 0.8 - ns

Read cycle parameters when EMC_CLKOUT0 used

tsu(D) data input set-up time 8.3 - tfbdly 5.5 - tfbdly -ns

th(D) data input hold time -1.9 + tfbdly -2.5 + tfbdly -ns

Read cycle parameters when EMC_CLKOUT1 used

tsu(D) data input set-up time 8.3 - tfbdly + (tclk1dly

- tclk0dly) 5.5 - tfbdly + (tclk1dly

- tclk0dly)-ns

th(D) data input hold time -1.9 + tfbdly -

(tclk1dly - tclk0dly) -2.5 + tfbdly -

(tclk1dly - tclk0dly) -ns

Write cycle parameters

td(QV) data output valid delay time [2] -t

clkndly+ 6.8 tclkndly+ 9.8 ns

th(Q) data output hold time [2] tclkndly  0.4 tclkndly -ns

Product data sheet Rev. 5.5 — 26 April 2016 86 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

Table 20. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01

CL=10pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. tcmddly is programmable delay

value for EMC command outputs in command delayed mode; t fbdly is programmable delay value for the feedback clock that

controls input data sampling; tclk0dly is programmable de lay value for the EMC_CLKOUT0 output; tclk1dly is programmable

delay value for the EMC_CLKOUT1 output.

Symbol Parameter Min Typ Max Unit

For RD = 1 tclk0dly = 0 and tclk1dly = 0

Common to read and write cycles

Tcy(clk) clock cycle time [1] 12.5 - - ns

td(SV) chip select valid delay time - tcmddly + 4.1 tcmddly + 6.0 ns

th(S) chip select hold time tcmddly + 1.0 tcmddly + 1.6 - ns

td(RASV) row address strobe valid

delay time -t

cmddly + 4.1 tcmddly + 6.0 ns

th(RAS) row address strobe hold

time tcmddly + 1.1 tcmddly + 1.7 - ns

td(CASV) column address strobe valid

delay time -t

cmddly + 4.1 tcmddly + 6.1 ns

th(CAS) column address strobe hold

time tcmddly + 1.2 tcmddly + 1.8 - ns

td(WV) write valid delay time - tcmddly + 4. 8 tcmddly + 7.1 ns

th(W) write hold time tcmddly + 1.6 tcmddly + 2.3 - ns

td(AV) address valid delay time - tcmddly + 4. 9 tcmddly + 7.3 ns

th(A) address hold time tcmddly + 1.0 tcmddly + 1.6 - ns

Read cycle parameters

tsu(D) data input set-up time 7.1 - tfbdly 4.8 - tfbdly -ns

th(D) data input hold time -1.9 + tfbdly -2.5 + tfbdly -ns

Write cycle parameters

td(QV) data output valid delay time - tcmddly + 4.9 tcmddly + 7.3 ns

th(Q) data output ho l d time tcmddly + 0.2 tcmddly + 0.5 - ns

Product data sheet Rev. 5.5 — 26 April 2016 87 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

Table 21. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01

CL=30pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. tcmddly is programmable delay

value for EMC command outputs in command delayed mode; t fbdly is programmable delay value for the feedback clock that

controls input data sampling; tclk0dly is programmable de lay value for the EMC_CLKOUT0 output; tclk1dly is programmable

delay value for the EMC_CLKOUT1 output.

Symbol Parameter Min Typ Max Unit

For RD = 1 tclk0dly = 0 and t clk1dly = 0

Common to read and write cycles

Tcy(clk) clock cycle time [1] 12.5 - - ns

td(SV) chip select valid delay time - tcmddly + 6.4 tcmddly + 9.5 ns

th(S) chip select hold time tcmddly + 0.9 tcmddly + 1.7 - ns

td(RASV) row address strobe valid

delay time -t

cmddly + 6.4 t cmddly + 9.5 ns

th(RAS) row address strobe hold

time tcmddly + 1.0 t cmddly + 1.8 - ns

td(CASV) column address strobe valid

delay time -t

cmddly + 6.5 t cmddly + 9.6 ns

th(CAS) column address strobe hold

time tcmddly + 1.0 t cmddly + 1.8 - ns

td(WV) write valid delay time - tcmddly + 7. 1 tcmddly + 10.6 ns

th(W) write hold time tcmddly + 1.4 tcmddly + 2.4 - ns

td(AV) address valid delay time - tcmddly + 7. 2 tcmddly + 10.6 ns

th(A) address hold time tcmddly + 0.8 tcmddly + 1.5 - ns

Read cycle parameters

tsu(D) data input set-up time 8.3 - tfbdly 5.5 - tfbdly -ns

th(D) data input hold time -1.9 + tfbdly -2.5 + tfbdly -ns

Write cycle parameters

td(QV) data output valid delay time - tcmddly + 7.4 t cmddly + 10.8 ns

th(Q) data output ho l d time tcmddly + 0.02 tcmddly + 0.6 - ns

Product data sheet Rev. 5.5 — 26 April 2016 88 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 19. Dynamic extern al memory interface signal timing

002aah129

Tcy(clk)

EMC_DYCSn,

EMC_RAS,

EMC_CAS,

EMC_WE,

EMC_CKEOUTn,

EMC_A[22:0],

EMC_DQMOUTn

th(Q)

th(D)

tsu(D)

EMC_D[31:0]

write

EMC_D[31:0]

read

td(QV)

th(x)

td(xV)

EMC_CLKOUT0

EMC_CLKOUT1

delay = 0

Product data sheet Rev. 5.5 — 26 April 2016 89 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[1] The programmable delay blocks are controlled by the EMCD LYCTL register in the EMC register block. All

delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user

manual for details.

Table 22. Dynamic characteristics: Dynamic external me mory interface programmable clock delays (CMDDLY,

FBCLKDLY, CLKOUT0DLY and CLKOUT1DLY)

Tamb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design. tcmddly is programmable delay value for EMC

command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input

data sampling; tclk0dly is programmable delay value for the EMC_CLKOUT0 output; tclk1dly is programmable delay value for the

EMC_CLKOUT1 output.

Symbols Parameter Five bit value for each delay in EMCDLY CTL[1] Min Typ Max Unit

tcmddly, tfbdly, tclk0dly, tclk1dly delay time b00000 0.0 0.0 0.0 ns

b00001 0.1 0.1 0.2 ns

b00010 0.2 0.3 0.5 ns

b00011 0.3 0.4 0.7 ns

b00100 0.5 0.8 1.3 ns

b00101 0.6 0.9 1.5 ns

b00110 0.7 1.1 1.8 ns

b00111 0.8 1.2 2.0 ns

b01000 1.2 1.8 2.9 ns

b01001 1.3 1.9 3.1 ns

b01010 1.4 2.0 3.4 ns

b01011 1.5 2.1 3.6 ns

b01100 1.7 2.6 4.2 ns

b01101 1.8 2.7 4.4 ns

b01110 1.9 2.9 4.7 ns

b01111 2.0 3.0 4.9 ns

b10000 2.4 3.7 6.0 ns

b10001 2.5 3.8 6.2 ns

b10010 2.6 4.0 6.5 ns

b10011 2.7 4.1 6.7 ns

b10100 2.9 4.5 7.3 ns

b10101 3.0 4.6 7.5 ns

b10110 3.1 4.8 7.8 ns

b10111 3.2 4.9 8.0 ns

b11000 3.6 5.4 8.9 ns

b11001 3.7 5.5 9.1 ns

b11010 3.8 5.7 9.4 ns

b11011 3.9 5.8 9.6 ns

b11100 4.1 6.2 10.2 ns

b11101 4.2 6.3 10.4 ns

b11110 4.3 6.6 10.7 ns

b11111 4.4 6.7 10.9 ns

Product data sheet Rev. 5.5 — 26 April 2016 90 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.3 External clock

11.4 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

11.5 I/O pins

[1] Applies to standard port pins.

Table 23. Dynamic chara cteristic: external clock (see Figure 36)

Tamb =





C to +85



C; VDD(3V3) over specified range s .

Symbol Parameter Min Typ Max Unit

fosc oscillator frequency 1 12 25 MHz

Tcy(clk) clock cycle time 40 83.3 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4 - - ns

tCLCX clock LOW time Tcy(clk) 0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

tCHCL tCLCX tCHCX

Tcy(clk)

tCLCH

002aaa907

Table 24. Dynamic characteristic: internal oscillators

Tamb =





C to +85



C; 2.7 V



VDD(REG)(3V3)



3.6 V.[1]

Symbol Parameter Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency 11.88 12 12.12 MHz

fi(RTC) RTC input frequency - 32.768 - kHz

Table 25. Dynamic characteristic: I/O pins[1]

CL=10pF, T

amb =





C to +85



C; VDD(3V3) = 3.0 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin configured as

output 3.0 - 5.0 ns

tffall time pin configured as

output 2.5 - 5.0 ns

Product data sheet Rev. 5.5 — 26 April 2016 91 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.6 SSP interface

[1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is l imited

by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster

than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain.

5The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the

SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register),

and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

[2] Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V.

[3] Tcy(clk) = 12  Tcy(PCLK). The maximum clock rate in slave mode is 1/12th of the PCLK rate.

[4] Tamb = 25 C; VDD(3V3) = 3.3 V.

Table 26. Dynamic characteristics: SSP pins in SPI mode

CL=10pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter Conditions Min Max Unit

SSP master

Tcy(clk) clock cycle time full-duplex

mode [1] 30 - ns

when only

transmitting 30 - ns

tDS data set-up time in SPI mode [2] 14.8 - ns

tDH data hold time in SPI mode [2] 2- ns

tv(Q) data output valid

time in SPI mode [2] -6.3 ns

th(Q) data output hold time in SPI mode [2] 2.4 - ns

SSP slave

Tcy(clk) clock cycle time [3] 100 - ns

tDS data set-up time in SPI mode [3][4] 14.8 - ns

tDH data hold time in SPI mode [3][4] 2- ns

tv(Q) data output valid

time in SPI mode [3][4] -3*T

cy(PCLK) + 6.3 ns

th(Q) data output hold time in SPI mode [3][4] 2.4 - ns

Product data sheet Rev. 5.5 — 26 April 2016 92 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 21. SSP master timing in SPI mode

Fig 22. SSP slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

CPHA = 1

CPHA = 0

002aae830

Product data sheet Rev. 5.5 — 26 April 2016 93 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.7 I2C-bus

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for S tandard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a S tandard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period

of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus

specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Table 27. Dynamic chara cteristic: I2C-bus pins[1]

Tamb =





C to +85



C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT data hold time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 5.5 — 26 April 2016 94 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.8 I2S-bus interface

[1] CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) =

1600 ns, corresponds to the SCK signal in the I2S-bus specification.

Fig 23. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Table 28. Dynamic chara cteristics: I2S-bus interface pins

CL=10pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter Conditions Min Max Unit

common to input and ou tput

trrise time [1] -6.7ns

tffall time [1] -8.0ns

tWH pulse width HIGH on pins I2S_TX_S CK and

I2S_RX_SCK [1] 25 - -

tWL pulse width LOW on pins I2S_TX_SCK and

I2S_RX_SCK [1] -25ns

output

tv(Q) data output valid time on pin I2S_TX_SDA; [1] -6ns

input

tsu(D) data input set-up time on pin I2S_RX_SDA [1] 5- ns

th(D) data input hold time on pin I2S_RX_SDA [1] 2- ns

Product data sheet Rev. 5.5 — 26 April 2016 95 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.9 LCD

Remark: The LCD controller is available on parts LPC1788/87/86/85.

Fig 24. I2S-bus timing (transmit)

Fig 25. I2S-bus timing (receive)

002aag202

I2S_TX_SCK

I2S_TX_SDA

I2S_TX_WS

Tcy(clk) tftr

tWH tWL

tv(Q)

002aag203

Tcy(clk) tftr

tWH

tsu(D) th(D)

tsu(D) tsu(D)

tWL

I2S_RX_SCK

I2S_RX_SDA

I2S_RX_WS

Table 29. Dynamic characteristics: LCD

CL=10pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter Conditions Min Max Unit

fclk clock frequency on pin LCD_DCLK - 50 MHz

td(QV) data output valid delay time - 9 ns

th(Q) data output hold time 0.5 - ns

Product data sheet Rev. 5.5 — 26 April 2016 96 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.10 SD/MMC

Remark: The SD/MMC card interface is available on parts LPC1788/87/86 and parts

LPC1778/77/76.

The LCD panel clock is shown with the default polarity. The clock can be inverted via the IPC bit in

the LCD_POL register . Typically, the LCD panel uses the falling edge of the LCD_DCLK to sample

the data.

Fig 26. LCD timing

002aah325

LCD_DCLK

td(QV)

Tcy(clk)

th(Q)

LCD_VD[n]

Table 30. Dynamic chara cteristics: SD/MMC

CL=10pF, T

amb =





C to 85



C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter Conditions Min Max Unit

fclk clock frequency on pin SD_CLK; data transfer mode - 25 MHz

on pin SD_CLK; identifi cation mode 25 MH z

tsu(D) data input set-up time on pins SD_CMD, SD_DAT[3:0] as

inputs 6- ns

th(D) data input hold time on pins SD_CMD, SD_DAT[3:0] as

inputs 6- ns

td(QV) data output valid

delay time on pins SD_CMD, SD_DAT[3:0] as

outputs -23ns

th(Q) data output hold time on pins SD_CMD, SD_DAT[3:0] as

outputs 3.5 - ns

Fig 27. SD/MMC timing

002aag204

SD_CLK

SD_DATn (O)

SD_DATn (I)

td(QV)

th(D)

tsu(D)

Tcy(clk)

th(Q)

SD_CMD (O)

SD_CMD (I)

Product data sheet Rev. 5.5 — 26 April 2016 97 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

12. ADC electrical characteristics

[1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.

[2] Conditions: VSSA =0V, V

DDA =3.3V.

[3] The ADC is monotonic, there are no missing codes.

[4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 28.

[5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 28.

Table 31. 12-bit ADC characteristics

VDDA = 2.7 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified.[1]

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDDA V

12-bit resolution

EDdifferential linearity

error [2][3][4] --1LSB

EL(adj) integral non-linearity [2][5] --6LSB

EOoffset error [2][6] --5LSB

EGgain error [2][7] --5LSB

ETabsolute error [2][8] --<8LSB

fclk(ADC) ADC clock frequency - - 12.4 MHz

fc(ADC) ADC conversion

frequency single conversion

mode --400kSa

mple

s/s

burst mode - - 375 kSa

mple

s/s

Cia analog input

capacitance --5pF

Rvsi voltage source

interface resistance [9] --1k

8-bit resolution[10]

EDdifferential linearity

error [2][3][4] -1- LSB

EL(adj) integral non-linearity [2][5] -1- LSB

EOoffset error [2][6] -1- LSB

EGgain error [2][7] -1- LSB

ETabsolute error [2][8] --<1.5 LSB

fclk(ADC) ADC clock frequency - - 36 MHz

fc(ADC) ADC conversion

frequency --1.16Msa

mple/

Cia analog input

capacitance --5pF

Rvsi voltage source

interface resistance [9] --1k

Product data sheet Rev. 5.5 — 26 April 2016 98 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

[6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 28.

[7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer

curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 28.

[8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer

curve of the non-calibrated ADC and the ideal transfer curve. See Figure 28.

[9] See Figure 29.

[10] 8-bit resolution is achieved by ignoring the lower four bits of the ADC conversion result.

Product data sheet Rev. 5.5 — 26 April 2016 99 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 28. 12-bit A DC ch a ra c t er i stics

002aaf436

4095

4094

4093

4092

4091

(2)

(1)

40964090 4091 4092 4093 4094 4095

7123456

4090

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VREFP - VSS

4096

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 5.5 — 26 April 2016 100 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

13. DAC electrical characteristics

The values of resistor components Rcmp and Rsw vary with temperature and input voltage and are

process-dependent.

Fig 29. ADC interface to pins ADC0_IN[n]

Table 32. ADC interface components

Component Range Description

Rcmp 90  to 300 Switch-on resistance for the comparator input switch. Varies

with temperature, input voltage, and process.

Rsw 500  to 2 kSwitch-on resistance for channel selection switch. Varies with

temperature, input voltage, and process.

C1 110 fF Parasitic capacitance from the ADC block level.

C2 80 fF Parasitic capacitance from the ADC block level.

C3 1.6 pF Sampling capacitor.

LPC178x/7x

AD0[n]

110 fF 80 fF Cia

1.6 pF

Rvsi

Rsw

500 Ω - 2 kΩ

Rcmp

90 Ω - 300 Ω

VSS VEXT

002aag613

ADC

COMPARATOR

BLOCK

Table 33. 10-bit DAC electr ical characteristics

VDDA = 2.7 V to 3.6 V; Tamb =





C to +85



C unless otherwise specified

Symbol Parameter Min Typ Max Unit

EDdifferential linearity error - 1- LSB

EL(adj) integral non-linearity - 1.5 - LSB

EOoffset error - 0.6 - %

EGgain error - 0.6 - %

CLload capacitance - - 200 pF

RLload resistance 1 - - k

Product data sheet Rev. 5.5 — 26 April 2016 101 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

14. Application information

14.1 Suggested USB interface solutions

Remark: The USB controller is available as a device/Host/OTG controller on parts

LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774.

Fig 30. USB interface on a self-powered device

LPC17xx

USB-B

connector

USB_D+

USB_CONNECT

SoftConnect switch

USB_D−

BUS

DD(3V3)

1.5 kΩ

RS = 33 Ω

002aad939

RS = 33 Ω

USB_UP_LED

Fig 31. USB interface on a bus-powered device

LPC17xx

VDD(3V3)

1.5 kΩ

USB_UP_LED

002aad940

USB-B

connector

USB_D+

USB_D−

VBUS

VSS

RS = 33 Ω

Product data sheet Rev. 5.5 — 26 April 2016 102 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 32. USB OTG port configuration: port 1 OTG dual-role device, port 2 host

USB_UP_LED1

USB_D+1

USB_D-1

USB_PWRD2

USB_SDA1

USB_SCL1

RSTOUT

15 kΩ 15 kΩ

LPC178x/7x

USB-A

connector

Mini-AB

connector

33 Ω

VDD

USB_UP_LED2

VDD

USB_OVRCR2

LM3526-L

ENA

5 V

OUTA

FLAGA

VDD

D+

D-

VBUS

USB_PPWR2

USB_D+2

USB_D-2

002aag506

R4 R5 R6

R1 R2 R3 R4

USB_INT1

RESET_N

ADR/PSW

SPEED

SUSPEND

OE_N/INT_N

SCL

SDA

INT_N

VBUS

ISP1302

VSSIO,

VSSCORE

VSSIO,

VSSCORE

Product data sheet Rev. 5.5 — 26 April 2016 103 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 33. USB OTG port configuration: VP_VM mode

USB_TX_DP1

USB_TX_DM1

USB_RCV1

USB_RX_DP1

USB_RX_DM1

USB_SCL1

USB_SDA1

SPEED

ADR/PSW

SDA

SCL

RESET_N

INT_N

SUSPEND

OE_N/INT_N

SE0_VM

DAT_VP

RCV

VBUS

LPC178x/7x ISP1302

USB MINI-AB

connector

33 Ω

002aag507

USB_TX_E1

RSTOUT

VDD

USB_INT1

USB_UP_LED1

VDD

VSSIO,

VSSCORE

Product data sheet Rev. 5.5 — 26 April 2016 104 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 34. USB host port configuration: por t 1 and p ort 2 as h osts

USB_UP_LED1

USB_D+1

USB_D-1

USB_PWRD1

USB_PWRD2

15 kΩ

15 kΩ 15 kΩ

15 kΩ

LPC178x/7x

USB-A

connector

USB-A

connector

33 Ω

002aag508

VDD

USB_UP_LED2

VDD

USB_OVRCR1

USB_OVRCR2

USB_PPWR1

LM3526-L

ENA

ENB

5 V

FLAGA

OUTA

OUTB

FLAGB

VDD

D+

D-

D+

D-

VBUS

USB_PPWR2

USB_D+2

USB_D-2

VSSIO,

VSSCORE

VSSIO,

VSSCORE

Product data sheet Rev. 5.5 — 26 April 2016 105 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

14.2 Crystal oscillator XTAL input and component selection

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled th rough a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

Fig 35. USB device port configuration : port 1 host and port 2 device

USB_UP_LED1

USB_D+1

USB_D-1

USB_PWRD1

15 kΩ 15 kΩ

LPC178x/7x

USB-A

connector

USB-B

connector

33 Ω

002aag509

VDD

USB_UP_LED2

USB_CONNECT2

VDD

USB_OVRCR1

USB_PPWR1

LM3526-L

ENA

5 V

FLAGA

OUTA

VDD

D+

D-

D+

D-

VBUS

USB_D+2

USB_D-2

VBUS VBUS

VSSIO,

VSSCORE

VSSIO,

VSSCORE

Product data sheet Rev. 5.5 — 26 April 2016 106 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 36), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 37 and in

Table 34 and Table 35. Since the feedback resistance is integrated on ch ip, only a crystal

and the capacitances CX1 and CX2 nee d to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 37 represent s the p arallel p ackage cap acitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the cry stal

manufacturer.

Fig 36. Slave mode operation of the on-chip oscillator

Fig 37. Oscillator modes and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

Table 34. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components par ameters): low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1/CX2

1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 300 39 pF, 39 pF

30 pF < 300 57 pF, 57 pF

LPC1xxx

XTAL1

100 pF Cg

002aae835

002aaf424

LPC1xxx

XTALIN XTALOUT

CX2

CX1

XTAL

=CLCP

Product data sheet Rev. 5.5 — 26 April 2016 107 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

14.3 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load cap acitors C x1, Cx2, and Cx3 in case o f

third overtone crystal usage have a common ground plane. The external components

must also be conne cted to the g round p lane. Lo op s must be made as small as possible in

order to keep the noise coup le d in via the PCB as sm all as po ss ible . A lso parasitics

should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen

according to the increase in parasitics of the PCB layout.

14.4 Standard I/O pin configuration

Figure 38 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver: Open -d rai n mo d e enab le d/ disa b l ed .

•Digital input: Pull-up enabled/disabled.

•Digital input: Pull-down enabled/disabled.

•Digital input: Repeater mode enabled/disabled.

•Analog input.

The default configuration for standard I/O pins is input with pull-up enabled. The weak

MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.

5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 200 39 pF, 39 pF

30 pF < 100 57 pF, 57 pF

10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 60 39 pF, 39 pF

15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF

Table 35. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters): high frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF

20 pF < 100 39 pF, 39 pF

20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 80 39 pF, 39 pF

Table 34. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components par ameters): low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1/CX2

Product data sheet Rev. 5.5 — 26 April 2016 108 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

14.5 Reset pin configuration

14.6 Reset pin configuration for RTC operation

Under certain circumstances, the RTC may temporarily pause and lose fractions of a

second during the rising and falling edges of the RESET signal.

Fig 38. Standard I/O pin configuration with analog input

VDD VDD

ESD

VSS

ESD

strong

pull-up

strong

pull-down

VDD

weak

pull-up

weak

pull-down

open-drain enable

output enable

repeater mode

enable

pull-up enable

pull-down enable

data output

data input

analog input

select analog input

002aaf272

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

Fig 39. Reset pin configuration

VSS

reset

002aaf274

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Product data sheet Rev. 5.5 — 26 April 2016 109 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the

RESET signal, connect an RC filter between the RESET pin and the external reset input.

Fig 40. Reset input with RC filter

002aag552

External

RESET input

10 kΩ

0.1 μF

RESET pin

Product data sheet Rev. 5.5 — 26 April 2016 110 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

15. Package outline

Fig 41. LQFP208 package

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 1.45

1.35 0.25 0.27

0.17 0.20

0.09 28.1

27.9 0.5 30.15

29.85 1.43

1.08 7

0.080.121 0.08

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT459-1 136E30 MS-026 00-02-06

03-02-20

D(1)

28.1

27.9

30.15

29.85

1.43

1.08

pin 1 index

EA1

detail X L

(A )

HA2

vMB

vMA

208

157

156 105

104

0 5 10 mm

scale

LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1

max.

1.6

Product data sheet Rev. 5.5 — 26 April 2016 111 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 42. TFBGA208 package

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT950-1 - - -

SOT950-1

06-06-01

06-06-14

UNIT A

max

mm 1.2 0.4

0.3 0.8

0.6 15.1

14.9 15.1

14.9 0.8 12.8 0.15 0.08 0.1

DIMENSIONS (mm are the original dimensions)

TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm

0 5 10 mm

scale

A2b

0.5

0.4

D E e e1e2

12.8

v w y

0.12

ball A1

index area

eAC B

∅ vMC∅ wM

246810121416

1357911131517

ball A1

index area

B A

detail X

AA2

Product data sheet Rev. 5.5 — 26 April 2016 112 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 43. TFBGA180 package

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT570-3

08-07-09

10-04-15

UNIT

mm max

nom

min

1.20

1.06

0.95

0.40

0.35

0.30

0.50

0.45

0.40

12.1

12.0

11.9

12.1

12.0

11.9 0.8 10.4 0.15 0.12

DIMENSIONS (mm are the original dimensions)

TFBGA180: thin fine-pitch ball grid array package; 180 balls

0 5 10 mm

scale

A1A2

0.80

0.71

0.65

b D E e e1

10.4

e2v w

0.05

y y1

0.1

ball A1

index area

2468101214

135791113

1/2 e

1/2 e AC B

∅ vMC∅ wM

ball A1

index area

detail X

AA2

Product data sheet Rev. 5.5 — 26 April 2016 113 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 44. LQFP144 package

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 1.45

1.35 0.25 0.27

0.17 0.20

0.09 20.1

19.9 0.5 22.15

21.85 1.4

1.1 7

0.080.2 0.081

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT486-1 136E23 MS-026 00-03-14

03-02-20

D(1) (1)(1)

20.1

19.9

22.15

21.85

1.4

1.1

0 5 10 mm

scale

EA1

detail X

(A )

HA2

HvMB

vMA

max.

1.6

LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1

108

109

pin 1 index

144 36

Product data sheet Rev. 5.5 — 26 April 2016 114 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

16. Soldering

Fig 45. Reflow soldering of the LQFP208 package

SOT459-1

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP208 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx HyP1 P2 C

sot459-1_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

31.300 31.300 28.300 28.3000.500 0.560 0.2801.500 0.400 28.500 28.500 31.550 31.550

Product data sheet Rev. 5.5 — 26 April 2016 115 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 46. Reflow solderin g of the TFBGA180 package

SOT570-3

solder land plus solder paste

Footprint information for reflow soldering of TFBGA180 package

solder land (SL)

solder paste deposit (SP)

Dimensions in mm

PSLSP

0.80 0.40

0.40

0.50

12.30

see detail X

sot570-3_fr

Issue date 14-01-30

15-08-27

Recommend stencil thickness: 0.1 mm

detail X

SL = SP

occupied area

solder resist opening (SR)

Product data sheet Rev. 5.5 — 26 April 2016 116 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Fig 47. Reflow soldering of the LQFP144 package

SOT486-1

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP144 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx HyP1 P2 C

sot486-1_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

23.300 23.300 20.300 20.3000.500 0.560 0.2801.500 0.400 20.500 20.500 23.550 23.550

Product data sheet Rev. 5.5 — 26 April 2016 117 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

17. Abbreviations

Table 36. Abbre viations

Acronym Description

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

AMBA Advanced Microcontrol ler Bus Archite cture

APB Advanced Peripheral Bus

BOD BrownOut Detection

CAN Controller Area Network

DAC Digital-to-Analog Converter

DMA Direct Memory Access

EOP End Of Packet

ETM Embedded Trace Macrocell

GPIO General Purpose Input/Output

GPS Global Positioning System

HVAC Heating, Venting, and Air Conditioning

IRC Internal RC

IrDA Infrared Data Association

JTAG Joint Test Action Group

MAC M edia Access Control

MIIM Media Independent Interface Management

OHCI Open Host Controller Interface

OTG On-The-Go

PHY Physical Layer

PLC Programmable Logic Controller

PLL Phase-Locked Loop

PWM Pulse Width Modulator

RMII Reduced Media Independent Interface

SE0 Single Ended Zero

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

TCM Tightly Coupled Memory

TTL Transistor-Transistor Log i c

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

Product data sheet Rev. 5.5 — 26 April 2016 118 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

18. References

[1] LPC178x/7x User manual UM10470:

http://www.nxp.com/documents/user_manual/UM10470.pdf

[2] LPC177x/8x Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC177X_8X.pdf

[3] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

Product data sheet Rev. 5.5 — 26 April 2016 119 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

19. Revision history

Table 37. Revision history

Document ID Release date Data sheet status Chang e notice Supersedes

LPC178X_7X v.5.5 20160426 Product data sheet - LPC178X_7X v.5.4

Modifications: •Updated Table 29 “Dynamic characteristics: LCD”: td(QV) max value is 9 ns for accuracy;

was 12 ns.

LPC178X_7X v.5.4 20160321 Product data sheet CIN 201603016I LPC178X_7X v.5.3

Modifications: •Added Table 18 “Dynamic characteristics: Dynamic external memory inte rface, read

strategy bits (RD bits) = 00” for 10 pF load.

•Updated Table 19 “Dynamic characteristics: Dynamic external memory interface, read

strategy bits (RD bits) = 00” for 30 pF load.

•Added Table 20 “Dynamic characteristics: Dynamic external memory inte rface, read

strategy bits (RD bits) = 01” for 10 pF load.

•Updated Table 21 “Dynamic characteristics: Dynamic external memory interface, read

strategy bits (RD bits) = 01” for 30 pF load.

•Updated Table 22 “Dynamic characteristics: Dynamic external memory interface

programmable clock delays (CMDDLY, FBCLKDLY, CLKOUT0DLY and CLKOUT1DLY)”.

•Updated Figure 19 “Dynamic external memory interface signal timing”.

LPC178X_7X v.5.3 20151015 Product data sheet - LPC178X_7X v.5.2

Modifications: •Corrected max value of tv(Q) (data output valid time) in SPI mode to 3*Tcy(PCLK) +

6.3 ns. Was: 3*Tcy(PCLK) + 2.5 ns. See Table 26 “Dynamic characteristics: SSP pins in SPI

mode”.

LPC178X_7X v.5.2 20150814 Product data sheet - LPC178X_7X v.5.1

Modifications: •Updated max value of tv(Q) (data output valid time) in SPI mode to 3*Tcy(PCLK) +

2.5 ns. See Table 24 “Dynamic characteristics: SSP pins in SPI mode”.

•Added a column for GPIO pins and device order part number to the ordering options table.

See Table 2 “LPC178x/7x ordering options”.

LPC178X_7X v.5.1 20140501 Product data sheet - LPC178X_7X v.5

Modifications: •Updated parameter tsu(D) in Table 18 “Dynamic characteristics: Dynamic external memory

interface, read strategy bits (RD bits) = 00”: Minimum value changed to (FBCLKDLY + 1) 

0.25 + 0.3. Maximum value removed.

•Removed max value from parameter th(D) in Table 17.

•Removed min value from parameter tdeact in Table 17.

•Specified ADC conversion rate in burst mode in Table 29 “12-bit ADC characteristics”.

Product data sheet Rev. 5.5 — 26 April 2016 120 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

LPC178X_7X v.5 201405 01 Product data sheet - LPC178X_7X v.4.1

Modifications: •Removed overbar from NMI.

•Table 3:

–Added minimum reset pulse width of 50 ns to RESET pin.

–Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC).

–Added boundary scan information to description for RESET pin.

–Updated pin description of STCLK.

•Table 13: Added Table note 3 “VDDA and VREF P should be tied to VDD(3V3) if the ADC

and DAC are not used.”.

•Table 23: Removed reference to RESET pin from Table note 1.

•Table 24:

–Removed Tcy(PCLK) spec; already given by the maximum chip frequency.

–Changed min clock cycle time for SSP slave from 120 to 100.

–Updated Table note 1 and Table note 3.

•Table 29: Added Table note 1 “VDDA and VREF P should be tied to VDD(3V3) if the ADC

and DAC are not used.”.

•Section 7.21.1 “Features”: Changed max speed for SSP master from 60 to 33.

• and added typical specs Table 17, Table 18, Table 19.

•SOT570-2 obsolete; replaced with SOT570-3.

•Table 17:

–Updated EMC timing specs to CL = 30 pF.

–Added typical specs.

–Table note 3: Changed Tcy(clk) = 1/CCLK to Tcy(clk) = 1/EMC_CLK.

•Table 18:

–Updated EMC timing specs to CL = 30 pF

–Added typical specs.

–Removed “All programmable delays EMCDLYCTL are bypassed” from table title.

•Table 19:

–Updated EMC timing specs to CL = 30 pF

–Added typical specs.

–Removed “All programmable delays EMCDLYCTL are bypassed” from table title.

Table 37. Revision history …continued

Document ID Release date Data sheet status Chang e notice Supersedes

Product data sheet Rev. 5.5 — 26 April 2016 121 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

LPC178X_7X v.4.1 20121115 Product data sheet - LPC178X_7X v.4

Modifications: •LCD timing characteristics up dated in Table 27 “Dynamic characteristics: LCD” and

Figure 26 added.

•Removed table note “The peak current is limited to 25 times the corresponding maximum

current.” in Table 9.

•Removed deep power-down spec Table 13 and associated table note.

•Updated min value for tWEHEOW Table 15.

•Removed Fig 21 Internal RC oscillator frequency versus temperature.

•Updated 12-bit and 8-bit value s for ET Table 29.

•Changed data sheet status to Product.

LPC178X_7X v.4 20120501 Preliminary data sheet - LPC178X_7X v.3

Modifications: •Editorial updates.

•BOD values added in Section 7.34.2.

•Parameters tCSLBLSL, tCSHOEH, tOEHANV, tdeact, tBLSHEOW, tBLSHDNV updated in Table 17.

•CL = 10 pF added to Table 24, Table 26, Table 28.

•IDD(REG)(3V3) corrected in Table 13 for conditions Deep-sleep mode, Power-down mode, and

Deep-pow er do w n mode.

•IBAT corrected in Table 13 for condition Deep power-down mode.

•Power consumption data in Figure 9 and Figure 10 corrected.

•I/O voltage VDD(3V3) specified in Table 17, Table 18, Table 19, Table 24, Table 28.

•VDD(3V3) range corrected in Table 23.

•Parameter CL changed to 10 pF for EMC timing in Table 17 to Table 20.

•USB and Ethernet dynamic characteristics removed. Timing characteristics follow USB 2.0

Specification (full speed) and IEEE standard 802.3 standards (see Section 7.15 and

Section 7.14 for compliance statements).

•Pad characteristics updated in Table 3.

•Parameter IBAT updated in Table 13.

•Figure 11 added.

•SDRAM timing corrected in Figure 19.

•EEPROM erase and programming times added (Table 16).

•Data sheet status changed to preliminary.

Table 37. Revision history …continued

Document ID Release date Data sheet status Chang e notice Supersedes

Product data sheet Rev. 5.5 — 26 April 2016 122 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

LPC178X_7X v.3 20111220 Objective data sheet - LPC178X_7X v.2

Modifications: •Removed BOOT function from pin P3[14].

•IBAT and IDD(REG)(3V3) updated for Deep power-down mode in Table 13.

•Maximum SDRAM clock of 80 MHz specified in Section 2, Table 18, and Tabl e 19.

•Power consumption data added (Figure 9 and Figure 10).

•Removed parameter ZDRV in Table 13.

•Specified maximum value for parameter CL in Table 33 and remove typical value.

•Specified setting of boost bits in Table 14, Table note 5 and in Table 1 3, Table note 6 .

•USB connection diagrams updated (Figure 33 to Figure 36).

•Current drain condition on battery supply specified in Section 7.33.6.

•Table note 10 in Table 13 updated.

•ADC characteristics updated (Table 31).

•Section 14.6 “Reset pin configuration for RTC operation” added.

•EEPROM size for parts LPC1774 corrected in Table 2 and Figure 1.

•Changed function LCD_VD[5] on pin P0[10] to Reserved.

•Changed function LCD_VD[10] on pin P0[11] to Reserved.

•Changed function LCD_VD[13] on pin P0[19] to Reserved.

•Changed function LCD_VD[14] on pin P0[20] to Reserved.

•ADC interface model updated (see Table 32 and Figure 30).

LPC178X_7X v.2 20110527 Objective data sheet - LPC178X_7X v. 1

Modifications: •Symbol names in Table 3 to Table 5 abbreviated .

•Reserved functions added in Table 3.

•Added function LCD_VD[5] to pin P0[10].

•Added function LCD_VD[10] to pin P0[11].

•Added function LCD_VD[13] to pin P0[19].

•Added function LCD_VD[14] to pin P0[20].

•Added function U4_SCLK to pin P0[21].

•Added function

•Added function MOSI to pin P5[0].

•Added function SSP2_MISO to pin P5[1].

•Added EMC dynamic characteristics.

LPC178X_7X v.1 2011052 4 Objective data sheet - -

Table 37. Revision history …continued

Document ID Release date Data sheet status Chang e notice Supersedes

Product data sheet Rev. 5.5 — 26 April 2016 123 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

20.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specificati on for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] data sheet Production This document contains the product specifica tion.

Product data sheet Rev. 5.5 — 26 April 2016 124 of 126

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifica tions, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product cl aims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

20.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 5.5 — 26 April 2016 125 of 126

continued >>

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 5

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Functional description . . . . . . . . . . . . . . . . . . 40

7.1 Architectural overview . . . . . . . . . . . . . . . . . . 40

7.2 ARM Cortex-M3 processor. . . . . . . . . . . . . . . 41

7.3 On-chip flash program memory . . . . . . . . . . . 41

7.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.5 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 41

7.6 Memory Protection Unit (MPU). . . . . . . . . . . . 41

7.7 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.8 Nested Vectored Interrupt Controller (NVIC) . 44

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.8.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 44

7.9 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 44

7.10 External memory controller. . . . . . . . . . . . . . . 44

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.11 General purpose DMA controller . . . . . . . . . . 46

7.11 .1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.12 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.13 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 48

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.14 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.15 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.15.1 USB device controller. . . . . . . . . . . . . . . . . . . 50

7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.15.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 50

7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.15.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 51

7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.16 SD/MMC card interface . . . . . . . . . . . . . . . . . 51

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.17 Fast general purpose parallel I/O . . . . . . . . . . 51

7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.18 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.19 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.20 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.21 SSP serial I/O controller. . . . . . . . . . . . . . . . . 53

7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.22 I2C-bus serial I/O controllers . . . . . . . . . . . . . 54

7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.23 I2S-bus serial I/O controllers . . . . . . . . . . . . . 55

7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.24 CAN controller and acceptance filters . . . . . . 55

7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.25 General purpose 32-bit timers/external event

counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.26 Pulse Width Modulator (PWM). . . . . . . . . . . . 56

7.26.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.27 Motor control PWM . . . . . . . . . . . . . . . . . . . . 57

7.28 Quadrature Encoder Interface (QEI) . . . . . . . 58

7.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.29 ARM Cortex-M3 system tick timer . . . . . . . . . 58

7.30 Windowed WatchDog Timer (WWDT) . . . . . . 59

7.30.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.31 RTC and backup registers. . . . . . . . . . . . . . . 59

7.31.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.32 Event monitor/recorder . . . . . . . . . . . . . . . . . 60

7.32.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.33 Clocking and power control . . . . . . . . . . . . . . 60

7.33.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 60

7.33.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 61

7.33.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 61

7.33.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 62

7.33.1.4 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 62

7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1) . 62

7.33.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 63

7.33.4 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 63

7.33.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.33.4.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 64

7.33.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 64

7.33.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 65

7.33.4.5 Wake-up Interrupt Controller (WIC) . . . . . . . . 65

7.33.5 Peripheral power control . . . . . . . . . . . . . . . . 65

7.33.6 Power domains . . . . . . . . . . . . . . . . . . . . . . . 65

7.34 System control. . . . . . . . . . . . . . . . . . . . . . . . 67

7.34.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.34.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 67

7.34.3 Code security (Code Read Protection - CRP) 67

7.34.4 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 68

7.34.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 68

7.34.6 External interrupt inputs. . . . . . . . . . . . . . . . . 68

7.34.7 Memory mapping control . . . . . . . . . . . . . . . . 68

7.35 Debug control. . . . . . . . . . . . . . . . . . . . . . . . . 68

NXP Semiconductors LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 April 2016

Document identifier: LPC178X_7X

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69

9 Thermal characteristics . . . . . . . . . . . . . . . . . 70

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 71

10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 74

10.2 Peripheral power consumption. . . . . . . . . . . . 76

10.3 Electrical pin characteristics. . . . . . . . . . . . . . 78

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 80

11 .1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 80

11.2 External memory interface . . . . . . . . . . . . . . . 81

11 .3 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 90

11.4 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 90

11 .5 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 91

11.7 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.8 I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . . 94

11 .9 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

11 .10 SD/MMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12 ADC electrical characteristics . . . . . . . . . . . . 97

13 DAC electrical chara cteristics . . . . . . . . . . . 100

14 Application information. . . . . . . . . . . . . . . . . 101

14.1 Suggested USB interface solutions . . . . . . . 101

14.2 Crystal oscillator XTAL input and component

selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.3 XTAL Printed-Circuit Board (PCB) layout

guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

14.4 Standard I/O pin configuration . . . . . . . . . . . 107

14.5 Reset pin configuration. . . . . . . . . . . . . . . . . 108

14.6 Reset pin configuration for RTC operation . . 108

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . 110

16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 117

18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

19 Revision history. . . . . . . . . . . . . . . . . . . . . . . 119

20 Legal information. . . . . . . . . . . . . . . . . . . . . . 123

20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 123

20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 123

20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 123

20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 124

21 Contact information. . . . . . . . . . . . . . . . . . . . 124

22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125