VC-709-0029-100M000000 - MICROCHIP TECHNOLOGY

VC-709

HCSL, LVDS, LVPECL Crystal Oscillator Data Sheet

Vectron’s VC-709 Crystal Oscillator is a quartz stabilized, diﬀ erential output oscillator, operating oﬀ a 2.5 or 3.3 volt supply in a

hermetically sealed 5x7 ceramic package.

• Ultra Low Jitter Performance, 3rd OT or Fundamental Crystal Design

• 13.500-220.0000MHz Output Frequencies

• Low Power

• 400ps max Rise and Fall Time

• Excellent Power Supply Rejection Ratio

• Enable/Disable

• 3.3 or 2.5V operation

• -10/70°C or -40/85°C Operation

• Hermetically Sealed 5x7 Ceramic Package

• Product is compliant to RoHS directive

and fully compatible with lead free assembly

Features Applications

Description

VC-709

Block Diagram Phase Noise

• PCI Express

• Ethernet, GbE, Synchronous Ethernet

• Fiber Channel

• Enterprise Servers

• Telecom

• Clock source for A/D’s, D/A’s

• Driving FPGA’s

• Test and Measurement

• PON

• Medical

• COTS

VDD Output

E/D or NC GND

Oscillator

Crystal

E/D or NC

Complementary

Output

Voltage Regulator

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Page2

Performance Speci cations

Table 1. Electrical Performance, LVPECL Option

Parameter Symbol Min Typical Maximum Units

Voltage1VDD 3.135

2.375

3.3

2.5

3.465

2.625

Current2, 3.3V

2.5V

IDD 45

Frequency

Nominal Frequency : 3.3V Supply

2.5V Supply

fN13.5

125.0

220.000

220.00

MHz

Stability3 (Ordering Option) ±20, ±25, ±50 or ±100 ppm

Outputs

Output Logic Levels2

Output Logic High

Output Logic Low

VOH

VOL

VDD-1.025

VDD-1.810

VDD-0.880

VDD-1.650

Output Rise and Fall Time2tR/tF400 ps

Load 50 ohms into VDD-2.0V

Duty Cycle445 55 %

Jitter5, 156.250MHz

12kHz-50MHz

12kHz -20MHz

10kHz-1MHz

фJ

200

150

100

Period Jitter6, 156.250MHz,

RMS

P/P

Cycle-Cycle6

RMS

P/P

Random Jitter7

Deterministic Jitter7

фJ

1.1

10.5

1.9

17.7

2.2

21.0

3.8

35.4

4.4

Enable/Disable

Outputs Enabled8

Outputs Disabled

VIH

VIL

0.7*VDD

0.3*VDD

Disable Time tD200 ns

Enable/Disable Leakage Current ±200 uA

Start-Up Time tSU 10 ms

Operating Temp. (Ordering Option) TOP -10/70 or -40/85 °C

Package Size 5.0 x 7.0 x 1.5 mm

1. The VC-709 power supply pin should be ﬁ ltered, eg, a 10uf, 0.1uf and 0.01uf capacitor.

2. Figure 1 deﬁ nes the test circuit and Figure 2 deﬁ nes these parameters.

3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reﬂ ow.

4. Duty Cycle is deﬁ ned as the On/Time Period.

5. Measured using an Agilent E5052.

6. Measured using a LeCroy Wavemaster 8600A, 90K samples

7. Measured using a Wavecrest SIA3300C, 90K samples.

8. Outputs will be Enabled if Enable/Disable is left open. tRtF

VAMP*0.8

VAMP*0.2

Cross Point

On Time

Period

VAMP

Figure 2.

-1.3V

VDD -1.3V

50 ȍ50 ȍ

Figure 1.

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Performance Speci cations

1. The VC-709 power supply pin should be ﬁ ltered, eg, a 10uf, 0.1uf and 0.01uf capacitor.

2. Figure 2 deﬁ nes these parameters and Figure 3 deﬁ nes the test circuit.

3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reﬂ ow.

4. Duty Cycle is deﬁ ned as the On/Time Period.

5. Measured using an Agilent E5052.

6. Measured using a LeCroy Wavemaster 8600A, 90K samples.

7. Measured using a Wavecrest SIA3300C, 90K samples.

8. Outputs will be Enabled if Enable/Disable is left open.

Table 2. Electrical Performance, LVDS Option

Parameter Symbol Min Typical Maximum Units

Supply

Voltage1VDD 3.135

2.375

3.3

2.5

3.465

2.625

Current2, 3.3V

2.5V

IDD 17

Frequency

Nominal Frequency fN13.5 220.000 MHz

Stability3 (Ordering Option) ±20, ±25, ±50 or ±100 ppm

Outputs

Output Logic Levels2

Output Logic High

Output Logic Low

VOH

VOL 0.9

1.43

1.10

1.6 V

Output Amplitude 250 350 450 mV

Diﬀ erential Output Error 50 mV

Oﬀ set Voltage 1.125 1.25 1.375 V

Oﬀ set Voltage Error 50 mV

Output Leakage Current, Outputs Disabled 10 uA

Output Rise and Fall Time3tR/tF400 ps

Load 100 ohms diﬀ erential

Duty Cycle445 55 %

Jitter5, 156.250MHz

12kHz - 50MHz

12kHz - 20MHz

10kHz - 1MHz

фJ

200

150

100

Period Jitter6, 156.250MHz

RMS

P/P

Cycle-Cycle Jitter6

RMS

P/P

Random Jitter7

Deterministic Jitter7

фJ

1.1

10.5

1.9

17.7

2.2

21.0

3.8

35.4

4.4

Enable/Disable

Outputs Enabled8

Outputs Disabled

VIH

VIL

0.7*VDD

0.3*VDD

Disable Time tD200 ns

Enable/Disable Leakage Current IE/D ±200 uA

Start-Up Time tSU 10 ms

Operating Temp. (Ordering Option) TOP -10/70 or -40/85 °C

Package Size 5.0 x 7.0 x 1.5 mm

6 5

0.01 uF

Out

Figure 3.

Performance Speci cations

Table 3. Electrical Performance, HCSL Output

Parameter Symbol Min Typical Maximum Units

Supply

Voltage1VDD 2.375

3.165

2.5

3.3

2.625

3.465

Current2IDD 39 mA

Frequency

Nominal Frequency fN13.5 170 MHz

Stability3 (Ordering Options) ±25, ±50 or ±100 ppm

Outputs

Output High, 3.3V

Output High, 2.5V

VOH 600

580

850

Output Low VOL -150 150 mV

Output Logic Swing, 3.3V

Output Logic Swing, 2.5V

VOPP 0.65

0.60

Output Rise and Fall Time3tR/tF500 ps

Load 50 ohms to ground

Duty Cycle445 55 %

Jitter5 (12 kHz - 20 MHz ) 100.000MHz фJ 300 fs

Period Jitter6, 100.000MHz

RMS

P/P

Cycle-Cycle Jitter6

RMS

P/P

Random Jitter7

Deterministic Jitter7

фJ

1.0

9.7

1.8

18.3

2.2

2.0

19.4

3.6

36.6

4.4

Enable/Disable

Outputs Enabled8

Outputs Disabled

VIH

VIL

0.7*VDD

0.3*VDD

Disable Time tD200 ns

Enable/Disable Leakage Current IE/D ±200 uA

Start-Up Time tSU 10 ms

Operating Temp. (Ordering Option) TOP -10/70 or -40/85 °C

Package Size 5.0 x 7.0 x 1.5 mm

1. The VC-709 power supply pin should be ﬁ ltered, e.g., a 10uf, 0.1uf and 0.01uf capacitor.

2. Figure 4 deﬁ nes the test circuit and Figure 5 deﬁ nes these parameters.

3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reﬂ ow.

4. Duty Cycle is deﬁ ned as the On Time/Period.

5. Measured using an Agilent E5052.

6. Measured using a LeCroy Wavemaster 8600A, 90K samples.

7. Measured using a Wavecrest SIA3300C, 90K samples.

8. Outputs will be Enabled if the Enable/Disable pad is left open.

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tRtF

0.8*Vopp

0.2*Vopp

Cross Point

On Time

Period

Figure 5.

VAMP

Figure 4.

50 Ω50 Ω

1 6

2 5

3 4

Package and Pinout

Table 4. Pinout

Pin # Symbol Function

1 E/D or NC Enable/Disable or No Connection

2 E/D or NC Enable/Disable or No Connection

3 GND Electrical and Lid Ground

4 fOOutput Frequency

5 CfOComplementary Output Frequency

6 VDD Supply Voltage

Figure 7. Package Outline Drawing

7.0±0.15

5.0±0.15

1.40

1.10

3.7

2.54

5.08

VC-709

XXMXXX

YYWW C

Bottom View

2 3

6 5 4

6 4

1.7 max

Figure 6. Pad Layout

HCSL Application Diagrams

The VC-709 incorporates a standard High Speed Current Logic, HCSL ,output scheme which is a 15mA current source switched between Out and Comple-

mentary Out. Being un-terminated drains, as shown in Figure 8, they require external 50 ohm resistors to ground as shown in Figure 9. HCSL is a high im-

pedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in Figure 10, to help reduce overshoot/

ringing.

Figure 8.

Standard HCSL Output Con guration

Figure 9.

Single Resistor Termination Scheme

Figure 10.

In some cases a 10-30 ohm series resistor is

used to help reduce overshoot.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-

nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching

into account. Load matching and power supply noise are the main contributors to jitter related problems.

15mA

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50 Ω50 Ω

1 6

2 5

3 4

ZL=50 ohms

50 Ω

1 6

2 5

3 4

50 Ω

ZL=50 ohms

10-30 Ω

1.96

3.66

5.08

2.54

1.78

Dimensions are in mm

Marking Information

XXXMXX - Frequency (Example: 100M00)

YY - Year of Manufacture

WW - Week of the Year

C - Manufacturing Location

- Pin 1 Indicator

Environmental and IR Compliance

Table 5. Environmental Compliance

Parameter Condition

Mechanical Shock MIL-STD-883 Method 2002

Mechanical Vibration MIL-STD-883 Method 2007

Temperature Cycle MIL-STD-883 Method 1010

Solderability MIL-STD-883 Method 2003

Fine and Gross Leak MIL-STD-883 Method 1014

Resistance to Solvents MIL-STD-202 Method 215

Moisture Sensitivity Level MSL1

Contact Pads Gold (0.3-1.0um) over Nickel

ThetaJC (bottom of case) 31 °C/W

Wieght 167 mg

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LVPECL Application Diagrams

LVDS Application Diagrams

The VC-709 incorporates a standard PECL output scheme, which are un-terminated FET drains. There are numerous application notes on terminating and

interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 11, or for best 50 ohm matching a pull-up/pull-down

scheme as shown in Figure 12 should be used. AC coupling capacitors are optional, depending on the application and the input logic requirements of the

next stage.

VDD

140 ȍ140 ȍ0.01uF

0.01uF

Figure 11. Single Resistor Termination Scheme

Resistor values are typically 140 ohms for 3.3V operation and

84 ohms for 2.5V operation.

Figure 12. Pull-Up Pull Down Termination

Resistor values shown are typical for 3.3 V opertaion. For 2.5V operation, the

resistor to ground is 62 ohms and the resistor to supply is 250 ohms

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-

nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching

into account. Load matching and power supply noise are the main contributors to jitter related problems.

100ȍLVDS

Driver

LVDS

Receiver

100ȍLVDS

Driver Receiver

Figure 13. LVDS to LVDS Connection, Internal 100ohm Resistor

Some LVDS structures have an internal 100 ohm resistor on the in-

put and do not need additional components. AC blocking capacitors

can be used if the DC levels are incompatible.

Figure 14. LVDS to LVDS Connection

Some input structures may not have an internal 100 ohm resis-

tor on the input and will need an external 100ohm resistor for

impedance matching. Also, the input may have an internal DC

bias which may not be compatible with LVDS levels, AC block-

ing capacitors can be used.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-

nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching

into account. Load matching and power supply noise are the main contributors to jitter related problems.

Table 6. Reﬂ ow Proﬁ le

Parameter Symbol Value

PreHeat Time ts 200 sec Max

Ramp Up RUP 3°C/sec Max

Time above 217°C tL 150 sec Max

Time to Peak Temperature tAMB-P 480 sec Max

Time at 260°C tP 30 sec Max

Time at 240°C tP2 60 sec Max

Ramp down RDN 6°C/sec Max

Suggested IR Pro le

Devices are built using lead free epoxy and can be subjected to

standard lead free IR reﬂ ow conditions shown in Table 6. Contact

pads are gold over nickel and lower maximum temperatures can also

be used, such as 220C.

IR Compliance

Absolute Maximum Ratings and Handling Precautions

Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other

excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended

periods may adversely aﬀ ect device reliability.

Although ESD protection circuitry has been designed into the VC-709, proper precautions should be taken when handling and mounting,

VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation.

ESD thresholds are dependent on the circuit parameters used to deﬁ ne the model. Although no industry standard has been adopted for

the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes.

Table 7. Maximum Ratings

Parameter Unit

Storage Temperature -55 to 125 °C

Junction Temperature 150 C

Supply Voltage -0.5 to 5.0 V

Enable Disable Voltage -0.5 to VDD+0.5 V

ESD, Human Body Model 1500 V

ESD, Charged Device Model 1500 V

Maximum Ratings, Tape & Reel

Table 8. Tape and Reel Information

Tape Dimensions (mm) Reel Dimensions (mm)

W F Do Po P1 A B C D N W1 W2 #/Reel

16 7.5 1.5 4 8 180 2 13 21 50 17 21 250

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VC-709- PCIE2 - 100M000000*

Product

Options

Supply =2.25-3.63V

Output = HCSL

Stability = ±50 ppm over -40/85°C

Enable/Disable on Pin 1

Frequency in MHz

Package

5x7

*Parts compliant to PCIe Generation 1 and 2 Speciﬁ cations

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For Additional Information, Please Contact

Ordering Information

Example: VC-709-ECE-KAAN-156M250000

VC-709- E C E - K A A N - xxxMxxxxxx

Product

Voltage Options

E: +3.3 Vdc ±5%

H: +2.5 Vdc ±5%

Output

H: HCSL

C: LVPECL

D: LVDS

Frequency in MHz

Temp Range

W: -10/70°C

E: -40/85°C

Other (Future Use)

N: Standard

Stability

F: ±25ppm

K: ±50ppm

S: ±100ppm

Enable/Disable Pin

A: Pin 1 (Pin 2 = No Connection)

B: Pin 2 (Pin 1 = No Connection)

Package

5x7

Enable/Disable Logic

A: Output is Enabled with a Logic High or open,

Output is Disabled with a Logic Low

PCI Express Ordering Information

VC-709-107-frequency= LVPECL, +3.3V, ±20ppm over -10/70°C, E/D on Pin1

VC-709-109-frequency= LVDS, +3.3V, ±20ppm over -10/70°C, E/D on Pin1

VC-709-110-frequency= LVPECL, +2.5V, ±20ppm over -10/70°C, E/D on Pin1

VC-709-111-frequency= LVDS, +2.5V, ±20ppm over -10/70°C, E/D on Pin1

VC-709-119-frequency= LVPECL, +3.3V, ±20ppm over -40/85°C, E/D on Pin1

VC-709-120-frequency= LVPECL, +2.5V, ±20ppm over -40/85°C, E/D on Pin1

VC-709-121-frequency= LVDS, +3.3V, ±20ppm over -40/85°C, E/D on Pin1

VC-709-122-frequency= LVDS, +2.5V, ±20ppm over -40/85°C, E/D on Pin1

±20ppm Options

* Add _SNPBDIP for tin lead solder dip

Example: VC-709-ECE-KAAN-156M250000_SNPBDIP

Revision Date Approved Description

Sep 05, 2014 VN VC-709 Product Initial Release.

Dec 12, 2014 VN Added min and max values for LVDS output amplitude.

Apr 27, 2016 VN Updated LVDS 100MHz noise information and added maximum jitter numbers.

Aug 10, 2018 FB Update logo and contact information, add SNPBDIP ordering option, marking detials, thetaJC and wieght

Revision History

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