VC-709 HCSL, LVDS, LVPECL Crystal Oscillator Data Sheet VC-709 Description Vectron's VC-709 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off a 2.5 or 3.3 volt supply in a hermetically sealed 5x7 ceramic package. Features * * * * * * * * * Applications Ultra Low Jitter Performance, 3rd OT or Fundamental Crystal Design 13.500-220.0000MHz Output Frequencies Low Power 400ps max Rise and Fall Time Excellent Power Supply Rejection Ratio Enable/Disable 3.3 or 2.5V operation -10/70C or -40/85C Operation Hermetically Sealed 5x7 Ceramic Package * Product is compliant to RoHS directive and fully compatible with lead free assembly PCI Express Ethernet, GbE, Synchronous Ethernet Fiber Channel Enterprise Servers Telecom Clock source for A/D's, D/A's Driving FPGA's Test and Measurement PON Medical COTS Phase Noise Block Diagram Complementary Output Output VDD Voltage Regulator Crystal Oscillator E/D or NC E/D or NC * * * * * * * * * * * GND Page1 Performance Specifications Table 1. Electrical Performance, LVPECL Option Parameter Voltage 1 Symbol Min Typical Maximum Units VDD 3.135 2.375 3.3 2.5 3.465 2.625 V V 45 42 mA 220.000 220.00 MHz Current2, 3.3V 2.5V IDD Nominal Frequency : 3.3V Supply 2.5V Supply fN Frequency 13.5 125.0 Stability3 (Ordering Option) 20, 25, 50 or 100 ppm Outputs Output Logic Levels2 Output Logic High Output Logic Low VOH VOL Output Rise and Fall Time2 tR/tF VDD-1.025 VDD-1.810 Load VDD-0.880 VDD-1.650 V V 400 ps 55 % 200 150 100 fs fs fs 1.1 10.5 2.2 21.0 ps ps 1.9 17.7 2.2 0 3.8 35.4 4.4 ps ps ps ps 50 ohms into VDD-2.0V Duty Cycle4 45 5 Jitter , 156.250MHz 12kHz-50MHz 12kHz -20MHz 10kHz-1MHz J Period Jitter6, 156.250MHz, RMS P/P Cycle-Cycle6 RMS P/P Random Jitter7 Deterministic Jitter7 J Outputs Enabled8 Outputs Disabled VIH VIL Disable Time tD Enable/Disable 0.7*VDD Enable/Disable Leakage Current Start-Up Time tSU Operating Temp. (Ordering Option) TOP Package Size 200 ns 200 uA 10 ms -10/70 or -40/85 C 5.0 x 7.0 x 1.5 mm 1. The VC-709 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor. 2. Figure 1 defines the test circuit and Figure 2 defines these parameters. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Duty Cycle is defined as the On/Time Period. 5. Measured using an Agilent E5052. 6. Measured using a LeCroy Wavemaster 8600A, 90K samples 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if Enable/Disable is left open. tR VDD -1.3V 1 V V 0.3*VDD tF VAMP*0.8 6 Cross Point NC 2 5 3 4 VAMP*0.2 NC 50 VAMP On Time 50 -1.3V Period Figure 2. Figure 1. Page2 Performance Specifications Table 2. Electrical Performance, LVDS Option Parameter Symbol Min Typical Maximum Units 3.135 2.375 3.3 2.5 3.465 2.625 V V 17 14 mA 220.000 MHz Supply Voltage1 VDD Current2, 3.3V 2.5V IDD Frequency Nominal Frequency fN 13.5 3 Stability (Ordering Option) 20, 25, 50 or 100 ppm Outputs Output Logic Levels2 Output Logic High Output Logic Low VOH VOL Output Amplitude 1.43 1.10 1.6 0.9 V V 250 350 450 mV 50 mV 1.125 1.25 1.375 V 50 mV 10 uA 400 ps 55 % 200 150 100 fs fs fs 1.1 10.5 2.2 21.0 ps ps 1.9 17.7 2.2 0 3.8 35.4 4.4 ps ps ps ps Differential Output Error Offset Voltage Offset Voltage Error Output Leakage Current, Outputs Disabled 3 Output Rise and Fall Time tR/tF Load 100 ohms differential Duty Cycle4 45 5 Jitter , 156.250MHz 12kHz - 50MHz 12kHz - 20MHz 10kHz - 1MHz J Period Jitter6, 156.250MHz RMS P/P Cycle-Cycle Jitter6 RMS P/P Random Jitter7 Deterministic Jitter7 J Enable/Disable 8 0.3*VDD V V tD 200 ns Enable/Disable Leakage Current IE/D 200 uA Start-Up Time tSU 10 ms Operating Temp. (Ordering Option) TOP Outputs Enabled Outputs Disabled VIH VIL Disable Time 0.7*VDD Package Size -10/70 or -40/85 C 5.0 x 7.0 x 1.5 mm 1. The VC-709 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor. 2. Figure 2 defines these parameters and Figure 3 defines the test circuit. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Duty Cycle is defined as the On/Time Period. 5. Measured using an Agilent E5052. 6. Measured using a LeCroy Wavemaster 8600A, 90K samples. 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if Enable/Disable is left open. 6 5 4 1 2 3 0.01 uF DC Figure 3. Page3 Out 50 50 Out Performance Specifications Table 3. Electrical Performance, HCSL Output Parameter Symbol Min Typical Maximum Units 2.5 3.3 2.625 3.465 V V 39 mA 170 MHz Supply Voltage1 VDD Current2 IDD Nominal Frequency fN 2.375 3.165 Frequency 13.5 3 Stability (Ordering Options) 25, 50 or 100 ppm Outputs Output High, 3.3V Output High, 2.5V VOH 600 580 850 850 mV mV Output Low VOL -150 150 mV Output Logic Swing, 3.3V Output Logic Swing, 2.5V VOPP 0.65 0.60 Output Rise and Fall Time3 tR/tF Load V V 500 ps 55 % 300 fs 1.0 9.7 2.0 19.4 ps ps 1.8 18.3 2.2 0 3.6 36.6 4.4 ps ps ps ps 50 ohms to ground Duty Cycle4 45 5 Jitter (12 kHz - 20 MHz ) 100.000MHz 6 Period Jitter , 100.000MHz RMS P/P Cycle-Cycle Jitter6 RMS P/P Random Jitter7 Deterministic Jitter7 J J Enable/Disable 8 0.3*VDD V V tD 200 ns IE/D 200 uA 10 ms Outputs Enabled Outputs Disabled VIH VIL Disable Time Enable/Disable Leakage Current Start-Up Time tSU Operating Temp. (Ordering Option) TOP 0.7*VDD Package Size -10/70 or -40/85 C 5.0 x 7.0 x 1.5 mm 1. The VC-709 power supply pin should be filtered, e.g., a 10uf, 0.1uf and 0.01uf capacitor. 2. Figure 4 defines the test circuit and Figure 5 defines these parameters. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Duty Cycle is defined as the On Time/Period. 5. Measured using an Agilent E5052. 6. Measured using a LeCroy Wavemaster 8600A, 90K samples. 7. Measured using a Wavecrest SIA3300C, 90K samples. 8. Outputs will be Enabled if the Enable/Disable pad is left open. tR 1 6 2 5 3 4 tF 0.8*Vopp Cross Point VAMP 0.2*Vopp 50 On Time 50 Period Figure 4. Figure 5. Page4 Package and Pinout Marking Information XXXMXX - Frequency (Example: 100M00) YY - Year of Manufacture WW - Week of the Year C - Manufacturing Location - Pin 1 Indicator Table 4. Pinout Pin # Symbol Function 1 E/D or NC Enable/Disable or No Connection 2 E/D or NC Enable/Disable or No Connection 3 GND Electrical and Lid Ground 4 fO Output Frequency 5 CfO Complementary Output Frequency 6 VDD Supply Voltage 7.00.15 5 6 4 VC-709 XXMXXX YYWW C 1.96 1 2 5.00.15 3 1.7 max 1.40 1.10 1.78 3.66 1 6 2 3 Bottom View 5 4 3.7 Dimensions are in mm 2.54 2.54 5.08 5.08 Figure 7. Package Outline Drawing Figure 6. Pad Layout HCSL Application Diagrams 15mA 1 6 2 5 1 6 2 5 10-30 ZL=50 ohms ZL=50 ohms 10-30 3 4 50 Figure 8. Standard HCSL Output Configuration ZL=50 ohms 50 Figure 9. Single Resistor Termination Scheme 3 4 ZL=50 ohms 50 50 Figure 10. In some cases a 10-30 ohm series resistor is used to help reduce overshoot. The VC-709 incorporates a standard High Speed Current Logic, HCSL ,output scheme which is a 15mA current source switched between Out and Complementary Out. Being un-terminated drains, as shown in Figure 8, they require external 50 ohm resistors to ground as shown in Figure 9. HCSL is a high impedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in Figure 10, to help reduce overshoot/ ringing. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Page5 LVPECL Application Diagrams VDD 0.01uF 1 6 2 5 3 4 NC 0.01uF NC 0.01uF 140 140 Figure 11. Single Resistor Termination Scheme Resistor values are typically 140 ohms for 3.3V operation and 84 ohms for 2.5V operation. Figure 12. Pull-Up Pull Down Termination Resistor values shown are typical for 3.3 V opertaion. For 2.5V operation, the resistor to ground is 62 ohms and the resistor to supply is 250 ohms The VC-709 incorporates a standard PECL output scheme, which are un-terminated FET drains. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 11, or for best 50 ohm matching a pull-up/pull-down scheme as shown in Figure 12 should be used. AC coupling capacitors are optional, depending on the application and the input logic requirements of the next stage. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. LVDS Application Diagrams LVDS Driver 100 LVDS Receiver LVDS Driver Figure 13. LVDS to LVDS Connection, Internal 100ohm Resistor Some LVDS structures have an internal 100 ohm resistor on the input and do not need additional components. AC blocking capacitors can be used if the DC levels are incompatible. 100 Receiver Figure 14. LVDS to LVDS Connection Some input structures may not have an internal 100 ohm resistor on the input and will need an external 100ohm resistor for impedance matching. Also, the input may have an internal DC bias which may not be compatible with LVDS levels, AC blocking capacitors can be used. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Environmental and IR Compliance Table 5. Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002 Mechanical Vibration MIL-STD-883 Method 2007 Temperature Cycle MIL-STD-883 Method 1010 Solderability MIL-STD-883 Method 2003 Fine and Gross Leak MIL-STD-883 Method 1014 Resistance to Solvents MIL-STD-202 Method 215 Moisture Sensitivity Level MSL1 Contact Pads Gold (0.3-1.0um) over Nickel ThetaJC (bottom of case) 31 C/W Wieght 167 mg Page6 S IR Compliance Suggested IR Profile Devices are built using lead free epoxy and can be subjected to standard lead free IR reflow conditions shown in Table 6. Contact pads are gold over nickel and lower maximum temperatures can also be used, such as 220C. Table 6. Reflow Profile Parameter Symbol Value PreHeat Time ts 200 sec Max Ramp Up RUP 3C/sec Max Time above 217C tL 150 sec Max Time to Peak Temperature tAMB-P 480 sec Max Time at 260C tP 30 sec Max Time at 240C tP2 60 sec Max Ramp down RDN 6C/sec Max S Maximum Ratings, Tape & Reel Absolute Maximum Ratings and Handling Precautions Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Although ESD protection circuitry has been designed into the VC-709, proper precautions should be taken when handling and mounting, VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes. Table 7. Maximum Ratings Parameter Unit Storage Temperature -55 to 125 C Junction Temperature 150 C Supply Voltage -0.5 to 5.0 V Enable Disable Voltage -0.5 to VDD+0.5 V ESD, Human Body Model 1500 V ESD, Charged Device Model 1500 V Table 8. Tape and Reel Information Tape Dimensions (mm) Reel Dimensions (mm) W F Do Po P1 A B C D N W1 W2 #/Reel 16 7.5 1.5 4 8 180 2 13 21 50 17 21 250 Page7 Ordering Information VC-709- E C E - K A A N - xxxMxxxxxx Frequency in MHz Product XO Package 5x7 Voltage Options E: +3.3 Vdc 5% H: +2.5 Vdc 5% Other (Future Use) N: Standard Enable/Disable Pin A: Pin 1 (Pin 2 = No Connection) B: Pin 2 (Pin 1 = No Connection) Enable/Disable Logic A: Output is Enabled with a Logic High or open, Output is Disabled with a Logic Low Output H: HCSL C: LVPECL D: LVDS Stability F: 25ppm K: 50ppm S: 100ppm Temp Range W: -10/70C E: -40/85C Example: VC-709-ECE-KAAN-156M250000 20ppm Options VC-709-107-frequency= VC-709-109-frequency= VC-709-110-frequency= VC-709-111-frequency= VC-709-119-frequency= VC-709-120-frequency= VC-709-121-frequency= VC-709-122-frequency= LVPECL, LVDS, LVPECL, LVDS, LVPECL, LVPECL, LVDS, LVDS, +3.3V, +3.3V, +2.5V, +2.5V, +3.3V, +2.5V, +3.3V, +2.5V, 20ppm over -10/70C, 20ppm over -10/70C, 20ppm over -10/70C, 20ppm over -10/70C, 20ppm over -40/85C, 20ppm over -40/85C, 20ppm over -40/85C, 20ppm over -40/85C, E/D on Pin1 E/D on Pin1 E/D on Pin1 E/D on Pin1 E/D on Pin1 E/D on Pin1 E/D on Pin1 E/D on Pin1 PCI Express Ordering Information VC-709- PCIE2 - 100M000000* Product XO Frequency in MHz Package 5x7 Options Supply =2.25-3.63V Output = HCSL Stability = 50 ppm over -40/85C Enable/Disable on Pin 1 *Parts compliant to PCIe Generation 1 and 2 Specifications For Additional Information, Please Contact * Add _SNPBDIP for tin lead solder dip Example: VC-709-ECE-KAAN-156M250000_SNPBDIP Page8 Revision History Revision Date Approved Sep 05, 2014 VN Description VC-709 Product Initial Release. Dec 12, 2014 VN Added min and max values for LVDS output amplitude. Apr 27, 2016 VN Updated LVDS 100MHz noise information and added maximum jitter numbers. Aug 10, 2018 FB Update logo and contact information, add SNPBDIP ordering option, marking detials, thetaJC and wieght Page9