19-4011; Rev 1; 12/96 Voltage-Output, 12-Bit Multiplying DACs General Description The MAXSO1/MAX502 are 12-bit, 4-quadrant, voltage- output, multiplying digital-to-analog converters (DACs) with an cutput amplifier. Thin-tilm resistors, laser trimmed at the wafer level, maintain accuracy over the full operating temperature range. The MAX501/MAX502 have buffered latches that are easily interfaced with microprocessors. Data is trans- ferred into the input register in either a right-justified 8+4-bit format (MAX501) or with a 12-bit-wide data path (MAX502). In the MAX501, an LDAC signal transfers data from the Input register to the DAG register. In the MAX502, the input registers are controlled by standard CHIP SELECT (CS) and WRITE (WR} signals. For stand- alone operation, the CS and WR inputs are grounded, making all latches transparent. All logic inputs are level triggered and compatible with TTL and +5V GMQS logic levels. The internally compensated, low-input offset-voltage output amplifier provides an output voltage from +10V to -10 while sourcing and sinking up to 5mA. Applications Digital Attenuators Programmable-Gain Amplifiers Servo Controls Digital to 4mA-to-20mA Converters Automatic Test Equipment Programmable Power Supplies MAAIM je ooooe 12-Bit Voltage Output DAC +10V and SmA Output Drive Monotonic Over Temperature Four Range-Scaling Resistors +4 (MAX501) and 12-Bit (MAX502) interface 24-Pin DIP and Wide SO Packages Features Ordering information PART TEMA RANGE PIN- PACKAGE ERROR {LSBs} MAXSO1ACNG Gio 470C 24 Narrow Plastic DIP 12 MAX501BCNG ercta+7o 24 Narrow Plastic DIP V4 MAXSO1ACWG 0C to +70C 24 Wide SO a2 MAX501BCWG OFC ta +70C 24 Wide SO a4 MAXS01BC/D OG ta +70C Dice 13/4 MAXS501AENG -40S to 185C 24 Narrow Plastic DIP +1/2 MAX501BENG 40C ta +86C 24 Narrow Plastic DIP 24 MAXS01AEWG -40C to +85C 24 Wide SQ 41/2 MAX501 BEWG -40C to 485C 24 Wide 50 to/4 MAXSO1 AMRG -55C to +125C 24 Narrow CERDIP** 12 MAXSCIBMRG -55C to +126C 24 Narrow CERDIP** +3/4 Ordering Information continued on leet page. * Contact factory for dica specifications. Contact factory for availability and processing to MIL-STD-883. Functional Diagram Pin Configurations TOP VIEW Voo RA RB AC AFB ww | 20 a [22 [23 | 24 Vour [4 [24] RFA q YL on [2] zat RC $48 SRDS IASA nv GB] [22] RB . 7 7 po Ca] nae [27] RA 7 . JREFF] 12-BIT DAC h pe Cay = MAXS02 [201 Von PAX Your b7 Ls] [78] V5 MAXS02 8 os ZZ] [7a] AGNG - 3 AGND ps [a] a7] VREF 12-Bi o4 [2] aes CONTROL LOGIC be DATA LATCH s 03 Gi FS] Wa 4 , Ee 5 02 Ga] [44] 00 pend Liz] 7] Di tal [2 an a DO..01 OGND CS WR DIFSO MAX501 on last page MAAXLA Maxim Integrated Products 1 For free samples & the latest literature: hitp://www.maxim-ic.com, or phone 1-800-998-8800 ZOSXVW/LOSXVNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs ABSOLUTE MAXIMUM RATINGS VoptoDOGND .............. vere necee es OV HIV VsstODGNO 2... ccc cece e asec wees TOBY -17V VREF tOAGND ,.......... cnc eaaaceee eorea TB5V RFBtoAGND .....,...0005. te veee een eceaee TEBV RAtOAGND 2. cece essa sce e teen senescence +25 ABtoAGND ..... bane ena du eenaae baw eeee 25 RC to AGND .,..... tanec enaieae rarenenees E25V Vout to AGND (Note 1) ......0.... Voo +0.3V, Ves -0.35V VDDtoAGND .........--.08 ewe e eee -O0.8V, +17V AGND to DGND te tee eee eet eeewenee ries O3 VoD Digital Input Voltage to GND .........., +++ O.3V Von Continuous Power Dissipation (any package) LOFTS viaccess neers taastanecetaveae 650mw derate above t75C oo. a... cece eens 10miW/? G Operating Temperature Ranges: MAXSO1_C_)MAX502_C wou acces eee OC to +70C MAXSO1_E_.MAXS502_E_ 2... eo, -40C to +86C MAXS01_M_,MAX502. M_ ........, -65C to +125C Storage Temperature Range ........... -65Cto +150C Lead Temperature (soldering, 10 sec) Note 1: Vout may be shorted to AGND, Vpp, or Vss if the power dissipation of the package is not exceeded. Stresses bayond those under Absolute Maximum Ratings may cause permanent damage [0 the device. These are sirass ratings only, and functional operation of the devica at these or any other conditions beyand thase indicated in the absolute maximum rating conditions for axiended periods may affact device reliabitity. ELECTRICAL CHARACTERISTICS +300C operational sections of the specification is not implted. Exposure to Dual Supply (Vop = +11.4V to +15.75V, Vag = -11.4V to -15,75V, VREF = +10V, AGND = DGND =0V, AL = 2kQ, Cr = 100pF, all grades, TA = TMIN to Taax, unless otherwise noted.) (Note 2) Ratio Matching PARAMETER SYMBOL | CONDITIONS MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits MAX501/5024 4/2 Ta =t25C MAX501/502B 13/4 Relative Accuracy INL LSB TA = Twin to Tuan MAXSO1/5024, 3/4 MAX501/502B +1 Differential Nonlinearity ONL +i LSB Ta = +28C +1 Zero-Gode Offset Error Ta = TMIN 10 Tuax | MAX501/502_C/E +2 mv MAX501/502_M +3 Offset Temperature Coefficient ae +5 weo RFB, Vout connected +3 Gain Error Be oF Re connected te Vout, +44 LSE RA, Vout connected, VREF = 2.5V +6 Galn Temperature Coefficient atone +1 ppm? Reference Input Resistance RFB 4 12 16 kf} Application Resistor RA to RB to RC match 05 | % MA AXLAAVoltage-Outpul, 12-Bit Multiplying DACs ELECTRICAL CHARACTERISTICS (continued) Dual Supply (Vpp = +11.4 to +15.75Y, Vas = -11.4V to -15.75V, VREF = +10, AGND = DGND = OV, RL = 2kQ, C_ = 100pF, all grades, TA = TMIN to Tmax, unless otherwise noted.) (Nota 2} PARAMETER | SYMBOL CONDITIONS MIN TYP MAX | UNITS DIGITAL INPUTS Input Current VIN = OV and V Tastee = A ut Gurren = ni B IN IN oD Ta = TMIN to Tax +10 # Input Low Valtage VIL 0.8 v Input High Voltage VIH 24 Vv Input Capacitance CIN 7 pF POWER SUPPLIES Supply Vollage Voo 11.40 15.75 Vv ppiyue Vss -11.40 -15.75 I V unicaded 10 Supply Current pp OT mA iss VouT unloaded 4 VREF = -10V Vop = 18V + 5% AGain/AVpo +002 VREF = -8.9V hod Vpp = 12V + 5% Power-Supply Rejection PSR %/% VREF = 10V ; Ves =-16V+5% AGain/AVss, +0.62 VREF = 8.9V q Ves =-12V + 5% DYNAMIC PERFORMANCE (Note 3) Output-Voltage Settling Time ts To +0,01% of full scale 5 HB Slew Rate SR 5 Vis BAC Giltch impulse Major carry transition 450 nv-s Multiplying Feedthrough Error VREF = +10 at 10kHz, DAC = all Os 5 mVp_p Unity-Gain Small-Signal Bandwidth 3 MHz Full-Power Bandwidth 250 kHz Total Harmonic Distortion THD VREF = 6Vems at 1kHz aw dB OUTPUT CHARACTERISTICS Open-Loop Gain Avo RFB not connected, Vout = +10V, RL = 2kQ st] dB Output Resistance Ro a2 a Short-Circuit Current Ta = +25C 20 mA O.1Hz te 10Hz, Ta = +25"C 2 Output Noise Voltage za EVRMS f = 1kHz, Ta = +25C 25 nv/Hz MAAXLAA 3 ZOSXVHNI/ LOSXVWMAX5S01/MAX502 Voltage-Output, 12-Bit Multiplying DACs TIMING CHARACTERISTICS (See Figures 1a, 1b) Duel Supply (Vop = +11.4V to +18.75V, Veg = -11.4V to -16.75, VREF = +10V, AGND = DGND = OV. RL = 2k, CL = 100pF, all grades, Ta = Twin to Taax, unless otherwise noted.) (Note 2) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS MAX501 Chip Select to Write-Setup Time tos 6 ns Write Pulse Width twa Tat tere 6 ns Ta = Twin to Tax 70 | MAX501_C/E 50 Data-Setup Time tos MAXSO1_M 0 ns Data-Hold Time tou 10 Q ns LDAG Pulse Width TLDAC 70 ns GER Pulse Width tcLa 70 ns SET Pulse Width tSET 200 ng MAX502 Chip Select to Write-Setup Time tes 4 ng Ta = +26C 40 Write Pulse Width twr Ta = Twin to Tuax MAX502_C/E 50 ng MAX502_M 60 MAX502_C/E 50 Data-Setup Time tos MAXS02_M rm ns Data-Hold Time tpH 16 o ns Note 2: Vout must be lass than Vpp - 2.5V and greater than Vsg + 2.5V to ensure correct operation. Performance at supplies other than Vpo = +15V anc Vsg = -15V is guaranteed by PSRR tests. Leave unused feedback resistors floating. Nota 3: Dynamic Performance and Output Characteristics are included far design guidance and are not subject to test. MAXLAAVoltage-Output, 12-Bit Multiplying DACs FREQUENCY RESPONSE, GAIN = -] +180 z PHASE +90 i 18 _ GAIN us oe z -180 & & Vop = +15 V5, = -15V VREF = 20p-p DAG GODE: 11... 117 100 1k 1k 100 iM 10M FREQUENCY (Hz) NOISE SPECTRAL DENSITY = Von = +15 > Vs5 = -15 = VREF = (Vv z= OAC CODE: 11... 111 a GAIN = -1 = a 2 wo a wi 2 2 = 10 100 ik 10k 100k FREQUENCY (Hz) MULTIPLYING FEEDTHROUGH ERROR GND GND MA AXILAMA VREF SWDN Vout (FEEDTHROUGH) 5mV/DIV Typical Operating Characteristics OUTPUT VOUAGE SWING vs. RESISTIVE LOAD Voo = +15 24 Vss = =15V VREF = 30Vp_p @ 1kHz # 16 = te 4 4 1 10 100 tk 10k LOAD RESISTANCE (9) THD vs. FREQUENCY T Vpp = +15V Yigg = -15V -25 LVREF = 6Vams. DAC CODE: 11... 111 GAIN = -1 -50 2 - al -100 100 ik 10k 100k FREQUENCY (Hz) MULTIPLYING FEEOTHROUGH ERROR vs. FREQUENCY 200 r Vop = +15 = Vsg = -15V | 160 [- VREF = 20Vp-p = DAG CODE: 00. . . 000 | = GAIN =4 % 120 5 oa : | = 89 a i 40 > a =| 100 tk 10k Wk 1M FREQUENCY (Hz} ZOSXVN/ LOSXVWMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs tog Ppt tes CSLSB OR CSMSB [at twr } iv WR h A tos a ton DATA DATA VALID {Lowe LDAG Figure ta. MAX501 Timing Diagram -< twR r WR h j tps pe to DATA DATA VALID Figure 1b. MAX502 Timing Diagram NOTES: 1. All input signal rise and fall times measured from 10% to 90% of +5V, ty = te = 20ns. 2. Timing measurement reference level is Vout Vin FA AXLAAVoltage-Output, 12-Bit Multiplying DACs Pin Descriptions MAX501 MAX502 PIN NAME FUNCTION PIN NAME FUNCTION 1 Vout Voltage Output 1 Vout Voltage Output 2 LDAG Asynchronous Load DAC Input is 2-11 |} D11-D2 Data Bits 2 to 11 (MSB) ___ active low 12 |DGND | Digital Ground 3__ {SET Sets DAC registor to all 1 13,14 |D1,00 __| Data Bits 0 to 1 (LSB) CLA Sets DAC register to all Gs 16 |WR Write Input |s active low 58 | D7-D4 Data Bits 7 to 4 16 cS Chip-Select Input is active low 908/011 | Data Bit Sor 11 7 | VREF Reference Input to DAG 10 D2/D10 Data Bit 2 or 10 18 AGND Analog Ground "poe [Data Bit or 19 [Vss -12V to -15 Supply Voltage Input 2 DGND Digital Ground 20 Vpo +12 to +15V Supply Voltage Input 13 [| D0/D8__| Data Bito or 8 {LSB} 21 [RA Scaling Resistor: RA = 4RFB 14 CSLSB LSB Chip-Select Input is active low 22 RB Scaling Resistor. RB = 2AFB 6 WR Writa Input is active low 23 RG Scaling Resistor. RC = 2RFB 16 CSM&SB MSB Chip-Select Input is active low 24 RFB Feedback Resistor 7 VREF Reference Input to DAC 8 AGND Analog Ground 19 Vss -12V to -18 Supply Voltage Input 20 Voo +12V to +15V Supply Voltage Input 21 RA Scaling Resistor: RA = 4RFB 22 RB Scaling Resistor: RB = 2AFB 23 RC Scaling Resistor: AC = 2RFB 24 AFB Feedback Rasistor MAXILAA 7 ZOSXVHN/LOSXVNMAX501/MAX502 Voltage-Output, 12-Bit Multiplying DACs Deialled Description Digital Cireult Figures 2a and 2b are simplified circuit diagrams of the MAX501 and MAX502 input control logic. For the MAX501, a low on CSLSB and WR with CSMSB high joads the least significant bit (LSB) byte into the input register. The LSB byte is then latched into the input register on the rising edge of either a WR or a CSLSB. Similarly, a low on CSMSB and WA with CSLSB high Table 1. MAX501 Truth Table loads the most significant bit (MSB} nibble into the input register. The MS6 nibble is then latched into the input ragister on the rising edge of either a WR or a CSMSB pulse. With all 12 bits loaded, a low on LDAC transfers the data to the DAC register. For the MAX502, a low on CS and WR transfers the data on the input registers to the DAC latch. Both parts digital inputs are TTL and CMOS compatible, providing sasy microprocessor (uP} interfacing. Tables 1 and 2 ara MAX501 and MAX502 truth tables. WR | CSMSB8 | CSLSB | LDAC CLR SET OPERATION x Xx x x x a DAC Ragister overridden by 1's Input Register unaffected x x x x 6 1 DAC Register overriddan by 0's Input Register unaffected 0 0 1 1 1 1 Load MSB nibble into Input Register 0 1 0 1 1 1 Load LSB byte into Input Register x x xX a 1 1 Transter Input Register to DAC Register 1 Xx x 1 1 1 No Operation o 1 1 1 1 1 No Operation a a 1 1 1 1 Latching MSB nibble into Input Register R o 1 1 1 1 _| Lathing MSB nibble into Input Register 0 1 R 1 1 1 Latching LSB byte into Input Register A 1 6 1 1 1 Latching LSB byte inte Input Ragister H = High State, L = Low State, R = Rising Edge, X = Don't Care Table 2. MAX502 Truth Table wa ts OPERATION H x No Operation x H No Operation L L Input Register is Transparent L R Input Register is Latched R L Input Register is Latched H = High State, L = Low State, RA = Rising Edge, X = Don't Care MAAXLMAVoitage-Output, 12-Bit Multiplying DACs CSMSB 4-BIT REGISTER WA a wears ae, 8-BIT REGISTER CSLSB LAC LDAG _ SET SET CLR CLR Figure 2a. MAX501 Input Controf Logic Digitai-to-Analog Converter The MAX501/MAX502 have a 12-bit, binary-weighted, current-output DAG with standard R-2R ladder (Figure a, INPUT REL AER 3). Binarily weighted currents are switched between A LATGH = AGNO and the inverting input of the internal output amplifier. The output amplifier, typically connected to the feedback resistor RFB, converts the output current WR _> to a voltage. With RFB connected to Vout. oS Vout =-D * VREF, where D is the fractional expression of the digital input code divided by full scale. D can vary from 0 to 4095/4096 in unipolar mode. Figure 2b, MAX502 Input Control Logic VREF R a R RA RB RC AFB , 2R 2A aR 2R SR aR 22R S2R A i | t J 7 f | 4 L 4 b - Vout l | + . | oft 00 {MSB) (LSB) AGND Figure 3. MAX501T/MAX502 Simoiified DAC and Amplifier Circuit MAAXIAA q ZOSXVW/LOSXVNMAXS501/MAX502 Voltage-Ouipul, 12-Bit Multiplying DACs Output-Buffer Amplifier The output amplifier is an internally compensated, non- inverting, gain-scalable amplifier that can develop +10V across a 2kQ load. Maximum settling time is less than Sus (to within 0.01% FSR}. Input offset voltage is laser trimmed at the wafer level. Slew rate is typically 7V/us. The gain-setting resistors (RA, RB, and RC) connect to the amplifier inverting terminal. Float unused gain-set- ting resistors. Unipolar Configuration Figure 4, a typical configuration for the MAX501/MAX502, provides for unipolar-bipolar operation or two-quadrant multiplication when Vin is an AC signal. R1 adjusts gain and R3 adjusts zero offset. For fixed-reference applica- tions, trim the reference voltage and omit R1 and R2. If R1 and R2 are included, you must take into account their gain-temperature coefficient. The typical gain-tempera- ture coefficient of the MAX5G2 is 1pprn*C, which corres- ponds to a gain shift of 1/2LSB over a +100C temperature range. Table 3 is the code table for unipolar- binary operation. Va = Von ORG ss 100k Rt Rd anon $10k 7 20) 23] 19 VREF Von RO Ves Bipolar Operation Figure 5 shows a 4-quadrant, bipolar operation. Gain error may be adjusted by changing the R1 and R2 ratio. These resistors should ba ratio- matched to 0.01% to stay within gain-error specifications and to sliminate trimming. The offset value is defined by matching ihe RB and RC internal resistors. Table 4 Is the code table for bipolar-binary operation. Yoo ss = 7} 22] 20) 19 VREF RB Yoo Vss VIA AL SV 1 Vout MAXSG1 _ DGND AGND RC Figure 5. Bipolar Operation (4-Quadrant Multiplication) Table 4. MAX501/MAX502 Bipolar-Binary Code Table Vv MAK 3" DIGITAL INPUT ANALOG OUTPUT MAXSO1/MAX502 304 4 2047 DGND AGND RFA 1000 1111 4111 1111 (VIN) Saag 1 = = 1000 0000 0001 (VIN) Span Figure 4. Unipolar-Binary Operation 1000 00(s00 ov (2-Quadrant Muitiplication) 1 0111 1114 W111 CVn) = Table 3. MAX501/MAX502 Unipolar-Binary Code Table 2046 2043 DIGITAL INPUT ANALOG OUTPUT 0000 = 0000s: 0000 (VIN) Span * VIN- 4095 Wt o4111 W111 {-VIN) 1006 2048 1 10000000 0000 (-Vin) 4096 72 VN 1 0000 0000 0001 (VIN) S06 0000 0000 co0c ov 10 MA AXLIMVoltage-Output, 12-Bit Multiplying DACs Applications information MAX502 Microprocessor Interfacing Noise 16-Bit Microprocessor Systems AC or transient voltages between AGND and DGND can Figures 7-9 show the MAX502 interfaced with the cause nolse injection into the analog output. Tie the MC68000, the 8086, and the TMS32010, The MAX502 MAX502 AGND tc DGND to ensure both pins are at the appears as a memory-mapped peripheral to the pro- same potential. If these ground pins connect to separate cessors. In each case, a write instruction loads the backplanes, use two back-to-back diodes to tie the pins MAX562 with the appropriate data. The particular together. Also, decouple Voo and Vss to AGND, as instructions used are as follows: uP-based systems generally have noisy grounds that 88000: couple into the power supplies. ines , Moye Digital Giltches = TMS32010: OUT Any digital word written into the DAC causes a giltch impuise. This impulse couples across the stray capaci- tance of the GAC switches to the output bus. A glitch AI-A23 impulse on this bus is converted to a voltage by RFB and 3 | the output amplifier. The output voltage glitch energy is M6000 -the product of its duration and its average magnitude _ ADDRESS [18 (the net area under the curve), and is expressed in AS pecope [1 5 (n)(s}. The energy is measured with VREF connected a MAXI to analog ground and the DAC register alternately DTAGK MAXS502 loaded with all Os and all 1s. RAW yJ>1 4 WR Digital Feedthrough ves 4 ' vere . DO-D15 G0-D11 Most of the MAX501/MAX502's digital inputs are directly -> 4 connected to the wP bus. These inputs are constantly 2 changing, even when the DAC is not selected. High- frequency logic activity on the data bus can feed Figure 7, MAX502 to MC6800 Interface through the DAC package capacitance as noise on the DAC output. Figure 6 shows an interface that minimizes digital feedthrough. All data inputs are latched from the busy by CS. Aiternatively, using peripheral interface devices reduces digital feedthrough. 16-BIT aeH{ caqen | J agoness fa cs DECODE exerte AMAIAAL/A H " \ ADDRESS AO-AIS .DORESS 2 MAXS02 _ 151 mMAXLmM Wa wR MAXS02 14 uP bt os AD0-ADIS D0-011 16 2 WA a Ta i Figure 8. MAX502 to 8086 Interface DO-D15 16-BIT boot LATCH 4 Figure 6. MAX502 Interface Circuit Latches Minimize Digital Feedthrough MAAXLAA 11 COSXVM/LOSXVNMAX501/MAX502 Voltege-Output, 12-Bit Multiplying DACs AQ-A11 j MIAXI/Vi TMS32010 ADORESS [16] DECODE f-] oS MAX4502 wa 13 WA DO-D15 >} DO-D11 2 Pin Configurations (continued) Figure 9. MAX502 to TMS32010 Interface MAXS50O1 Microprocessor interfacing 8-8 Microprocessor Sysiama Figure 10 shows an interface circuit for the MAX501 to the 8085A 8-bit uP The software routine to load date to the device is given in Table 3. Note that transferring 12 data bits requiras two write operations. The first of these loads the 4 MSBs into the 7475 latch. The second write operation loads the 8 LSBs plus the 4 MSBs (which are held by the latch) into the DAC. TOP VIEW Vour 11] (24) AFB TDAC [2] [za] AC Ser [a] 22] RB cLACa] AAAxLM GG AA o7[S) 40 MAX5O1 =) Von D [5 | 119} Wss oT 18} AGND ba a] [47] VREF pyvot (a | 16] CSM5B 02/010 Ge! 45] WR p1/09 [4] [74] CSLSB DGND Fiz] 73] DO/D8 DIPYSO __ Ordering information (continued) PART TEMPRANGE = shi yae s80) AB-AIS Re MAXSO2ZAGNG 0 to+70C 24 Narrow Plastic OIP 1/2 MAXS02BCNG O0Gto+70C 24 Nerrow Plastic DIP = 4/4 Oo MAXSOPACWG 0 to +70G 24 Wide SO 2 ALE tor Aros 6 TSMS6 MAXSOZBGWG OCIa+70C 24 Wide SO avd 80854/8088 [ ) Loac MAXSO2BC/D O Gto+70C Dice af4 Zs MAK MAXSO2AENG -40C to +85C 24 Narrow Plastic DIP = 1/2 WR El wR MaxSoF MAXSO2BENG 40C to +85C 24 Narrow Plastic DIP 3/4 {3 MAXSO2AEWG -40C to 485C 24 Wide SO W2 ADG-AD? DorD8-07 MAXSO2BEWG 40C to +85C 24 Wide SO af 4 MAXSOZAMAG -85C 10 125C 24NarrowCERDIP 1/2 L MAXSO2BMAG -56G to +125C 24NarowCERDIE 3/4 Figure 10. MAX507 to 8085A/8088 Interface * Gontect factory for dica specifications. Contact factory for availability end processing to MIL-STD-383. Maxim cannot assume reaponsibiity for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licensas ara implied. Maxim reserves the right to change the circuitry and specifications without noice at any ime. 12 1996 Maxim Integrated Products Printed USA Maxim integrated Products, 120 San Gabriel Dive, Sunnyvale, CA 94086 (408) 737-7600 MM is a registered trademark of Maxim Integratad Products.