TCD2561D
2003-05-06
1
TOSHIBA CCD Linear Image Sensor CCD (charge coupled device)
TCD2561D
The TCD2561D is a high sensitive and low dark current 5340
elements × 4 line CCD color image sensor which includes CCD
drive circuit, clamp circuit.
The sensor is designed for scanner. The device contains a row of
5340 elements × 4 line photodiodes which provide a 24 lines/mm
across a A4 size paper. The device is operated by 5 V pulse and
12 V power supply.
Features
x Number of image sensing elements: 5340 elements × 4 line
x Image sensing element size: 7 Pm × 7 Pm on 7 Pm centers
x Photo sensing region: High sensitive PN photodiode
x Distanced between photodiode array: Color (28 Pm, 4 lines), B/W-color (56 Pm, 8 lines)
x Clock: 2 phase (5 V)
x Power supply: 12 V power supply voltage
x Internal circuit: Clamp circuit
x Package: 22 Pin CERDIP package
x Color filter: Red, green, blue
Maximum Ratings (Note1)
Characteristic Symbol Rating Unit
Clock pulse voltage VI V
Shift pulse voltage VSH V
Reset pulse voltage VRS V
Clamp pulse voltage VCP V
Changeover switch voltage VSW
0.3~8.0
V
Power supply voltage VOD 0.3~15 V
Operating temperature Topr 0~60 °C
Storage temperature Tstg 25~85 °C
Note 1: All voltage are with respect to SS terminals (ground).
Weight: 5.2 g (typ.)
OS2
22
OS1
OD
SS
1SW
I2A3
21
20
19
18
17
16
OS3 1
2
3
4
5
6
7
SS
RS
CP
2SW
I1A3
SS NC
I2A1
I1A1
SH0
15
14
13
12
8
9
10
11
I2A2
I1A2
SH3
SH2 SH1
1 Red 5340
1
1
5340
5340
Green
Blue
1 5340 Black & White
Pin Connections (top view)
TCD2561D
2003-05-06
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Circuit Diagram
Pin Names
OS3 Signal Output 3 (red) OS2 Signal Output 2 (green)
SS Ground OS1 Signal Output 1 (blue)
RS Reset Gate OD Power
CP Clamp Gate SS Ground
2SW Changeover Switch 2 (color and B/W) 1SW Changeover Switch 1 (color and B/W)
I1A3 Clock 3 (phase 1) I2A3 Clock 3 (phase 2)
SS Ground NC Non Connection
I2A2 Clock 2 (phase 2) I2A1 Clock 1 (phase 2)
I1A2 Clock 2 (phase 1) I1A1 Clock 1 (phase 1)
SH3 Shift Gate 3 SH0 Shift Gate 0
SH2 Shift Gate 2 SH1 Shift Gate 1
3
CCD ANALOG SHIFT REGISTER (EVEN)
SHIFT GATE SH0
D26
SHIFT GATE SH0
CCD ANALOG SHIFT REGISTER (ODD)
Clamp
Clamp
Clamp
Clamp
Clamp
4
18 19 20
9 8
15
13
OS2
OS1
OD SS 1SW I2A3
SS
RS
CP
I1A3
I2A1
SH0
I2A2 I1A2
7
6 17
1
22
21
OS3
SW1
SW1
SW2
SW2
D27
D28
D125
D126
D127
S1
S2
S5340
D128
㧰148
D149
S5339
S5338
PHOTO
DIODE
(Black & White)
D26
D27
D28
D125
D126
D127
S1
S2
S5340
D128
㧰148
D149
S5339
S5338
PHOTO
DIODE
(blue)
SHIFT GATE SH1
CCD ANALOG SHIFT REGISTER
D26
SHIFT GATE SH2
CCD ANALOG SHIFT REGISTER
D27
D28
D125
D126
D127
S1
S2
S5340
D128
㧰148
D149
S5339
S5338
PHOTO
DIODE
(green)
D26
D27
D28
D125
D126
D127
S1
S2
S5340
D128
㧰148
D149
S5339
S5338
PHOTO
DIODE
(red)
SHIFT GATE SH3
CCD ANALOG SHIFT REGISTER
5
2SW
12 SH1
14 I1A1
11 SH2
10 SH3
TCD2561D
2003-05-06
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Optical/Electrical Characteristics
(Ta
25°C, VOD
12 V, VI
II
I
VRS
VSH
VCP
5 V (pulse), fI
II
I
1.0 MHz, fRS
1.0 MHz,
LOAD RESISTANCE
100 k:
::
:, tINT (INTEGRATION TIME)
10 ms,
LIGHT SOURCE
A LIGHT SOURCE
CM500S FILTER (t
1.0 mm))
Characteristics Symbol Min Typ. Max Unit Note
RB/W 16.8 21.0 25.2
RR 6.3 9.0 11.7
RG 7.3 10.5 13.7
Sensitivity
RB 3.8 5.5 7.2
V/(lx㨯s) (Note 2)
PRNU (1) 10 20 % (Note 3)
Photo response non uniformity
PRNU (3) 3 12 mV (Note 4)
Image lag IL 1 % (Note 5)
Saturation output voltage (B/W) VSAT (B/W) 3.2 3.5 V (Note 6)
Saturation output voltage (color) VSAT (color) 3.2 3.5 V (Note 6)
Saturation exposure SE 0.1 lx㨯s (Note 7)
Dark signal voltage VDRK 0.4 2.0 mV (Note 8)
Dark signal non uniformity DSNU 7 12 mV (Note 8)
DC power dissipation PD 480 690 mW
Total transfer efficiency TTE 92 %
Output impedance ZO 0.3 1.0 k:
DC signal output voltage VOS 5.0 6.0 7.0 V (Note 9)
Random noise NDV 1.0 mV (Note 10)
Reset noise VRSN 0.5 1.0 V (Note 9)
Note 2: Sensitivity is defined for each color of signal outputs average when the photosensitive surface is applied
with the light of uniform illumination and uniform color temperature.
Note 3: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive
surface is applied with the light of uniform illumination and uniform color temperature.
'X
PRNU (1) X u 100 (%)
When X is average of total signal output and 'X is the maximum deviation from X . The amount of
incident light is shown below.
1 1 1
Red 2 SE, Green 2 SE, Blue 4 SE
Note 4: PRNU (3) is defined as maximum voltage with next pixel, where measured 5% of SE (typ.)
TCD2561D
2003-05-06
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Note 5: Image Lag is defined as follows.
Note 6: VSAT is defined as minimum saturation output of all effective pixels.
Note 7: Definition of SE:
Note 8: VDRK is defined as average dark signal voltage of all effective pixels. DSNU is defined as different voltage
between VDRK and VMDK when VMDK is maximum dark signal voltage.
Note 9: DC signal Output Voltage and Reset Noise is defined as follows, but Reset Noise is a fixed pattern noise.
SH
OS
LED
OFF ON
Signal
(500 mV)
Image Lag
VSAT
SE RB/W (lx㨯s)
VMDK
VDRK
DSNU
SS
VOS
VRSN
OS
TCD2561D
2003-05-06
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Note 10: Random noise is defined as the standard deviation (sigma) of the output level difference between two
adjacent effective pixels under no illumination (i.e. dark conditions) calculated by the following procedure.
(1) Two adjacent pixels (pixel n and n 1) in one reading are fixed as measurement points.
(2) Each of the output level at video output periods averaged over 200 ns period to get V (n) and V (n 1).
(3) V (n 1) is subtracted from V (n) to get 'V.
'V V (n) V (n 1)
(4) The standard deviation of 'V is calculated after procedure (2) and (3) are repeated 30 times (30
readings)
¦
' ' 30
1
Vi
30
1
Vi ¦
''
V __
30
1i
2
)VV(
30
1i㧙
(5) Procedure (2), (3) and (4) are repeated 10 times to get sigma value.
(6) 10 sigma values are averaged.
¦
V V
10
1j j
10
1
(7) V value calculated using the above procedure is observed 2 times larger than that measured
relative to the ground level. So we specify random noise as follows.
V
V2
1
ND
Output waveform (effective pixels under dark condition)
video output video output
200 ns
200 ns
pixel (n)
pixel (n 1)
'V
TCD2561D
2003-05-06
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Operating Condition
Characteristics Symbol Min Typ. Max Unit Note
“H” Level 4.5 5.0 5.5
Clock pulse voltage
“L” Level
VIA
0 0.5
V
“H” Level 4.5 5.0 5.5
Shift pulse voltage
“L” Level
VSH
0 0.5
V
“H” Level 4.5 5.0 5.5
Reset pulse voltage
“L” Level VRS
0 0.5
V
“H” Level 4.5 5.0 5.5
Clamp pulse voltage
“L” Level VCP
0 0.5
V
“H” Level 4.5 5.0 5.5
Switch pulse voltage
“L” Level VSW
0 0.5
V
Power supply voltage VOD 11.4 12.0 13.0 V
Clock Characteristics (Ta
25°C)
Characteristics Symbol Min Typ. Max Unit
Clock pulse frequency fI 0.3 1.0 16 MHz
Reset pulse frequency fRS 0.3 1.0 10 MHz
Clamp pulse frequency fCP 0.3 1.0 10 MHz
Clock1 capacitance (Note 11) CI1 160 240 pF
Clock2 capacitance (Note 11) CI2 130 195 pF
Shift gate capacitance CSH 30 60 pF
Reset gate capacitance CRS 10 40 pF
Clamp gate capacitance CCP 10 40 pF
Switch gate capacitance CSW 10 40 pF
Note 11: VOD 12 V
TCD2561D
2003-05-06
7
Timing Chart 1: Bit Clamp Mode (Color mode)
SH1, 2, 3
1 LINE READOUT PERIOD (5490 elements)
DUMMY OUTPUTS
(26 elements)
LIGHT SHIELD OUTPUTS
(96 elements) (6 elements) DUMMY OUTPUTS (3 elements)
TEST OUTPUTS (1 elements)
DUMMY
OUTPUTS
(12 elements)
DUMMY OUTPUTS (128 elements) SIGNAL OUTPUTS (5340 elements)
OS1, 2, 3 (color)
(6 elements)
DUMMY OUTPUTS (22 elements)
D132
D133
D145
D146
D134
D130
S2618
S2617
S2616
D147
D148
S1
D125
D124
D123
D122
D121
D60
D26
D12
D13
D1
D0
D127
D126
D149
D25
D61
D62
D63
D64
S2606
S2607
S2608
S2609
S2610
D128
D129
S5340
D131
tINT (integration time)
I1A
I2A
RS
CP
SH0 (“H”)
TCD2561D
2003-05-06
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Timing Chart 2: Line Clamp Mode (Color mode)
SH1, 2, 3
1 LINE READOUT PERIOD (5490 elements)
DUMMY OUTPUTS
(26 elements)
LIGHT SHIELD OUTPUTS
(96 elements) (6 elements) DUMMY OUTPUTS (3 elements)
TEST OUTPUTS (1 elements)
DUMMY
OUTPUTS
(12 elements)
DUMMY OUTPUTS (128 elements) SIGNAL OUTPUTS (5340 elements)
OS1, 2, 3 (color)
(6 elements)
DUMMY OUTPUTS (22 elements)
D132
D133
D145
D146
D134
D130
S2618
S2617
S2616
D147
D148
S1
D125
D124
D123
D122
D121
D60
D26
D12
D13
D1
D0
D127
D126
D149
D25
D61
D62
D63
D64
S2606
S2607
S2608
S2609
S2610
D128
D129
S5340
D131
tINT (integration time)
I1A
I2A
RS
CP SH
CP “H”
SH0 (“H”)
TCD2561D
2003-05-06
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Timing Chart 3: Bit Clamp Mode (B/W mode)
SH0
1 LINE READOUT PERIOD (2745 elements)
DUMMY OUTPUTS
(13 elements)
LIGHT SHIELD OUTPUTS
(48 elements) (3 elements) DUMMY OUTPUT (1 element)
TEST OUTPUT (1 element)
DUMMY OUTPUTS (6 elements)
DUMMY OUTPUTS (64 elements)
(3 elements)
DUMMY OUTPUTS (11 elements)
OS1 (B/W)
SIGNAL OUTPUTS (2670 elements)
D133
D147
D135
D131
D129
S5340
D149
S2
D125
D123
D121
D27
D25
D3
D1
D127
D51
D53
S116
S118
S120
S122
S124
S126
S128
S130
tINT (integration time)
I1A
I2A
RS
CP
OS2 (B/W)
D132
D146
D134
D130
D128
S5339
D148
S1
D124
D122
D120
D26
D24
D2
D0
D126
D50
D52
S115
S117
S119
S121
S123
S125
S127
S129
SH1, 2, 3 (“H”)
TCD2561D
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Timing Chart 4: Line Clamp Mode (B/W mode)
SH0
1 LINE READOUT PERIOD (2745 elements)
DUMMY OUTPUTS
(13 elements)
LIGHT SHIELD OUTPUTS
(48 elements) (3 elements) DUMMY OUTPUT (1 element)
TEST OUTPUT (1 element)
DUMMY OUTPUTS (6 elements)
DUMMY OUTPUTS (64 elements)
(3 elements)
DUMMY OUTPUTS (11 elements)
OS1 (B/W)
SIGNAL OUTPUTS (2670 elements)
D133
D147
D135
D131
D129
S5340
D149
S2
D125
D123
D121
D27
D25
D3
D1
D127
D51
D53
S116
S118
S120
S122
S124
S126
S128
S130
tINT (integration time)
I1A
I2A
RS
OS2 (B/W)
D132
D146
D134
D130
D128
S5339
D148
S1
D124
D122
D120
D26
D24
D2
D0
D126
D50
D52
S115
S117
S119
S121
S123
S125
S127
S129
CP SH
CP “H”
SH1, 2, 3 (“H”)
TCD2561D
2003-05-06
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Timing Requirements
I1
I2
GND
3.5 V (max)
1.5 V (min)
t1
t2 t3 t4
t5
t6
t7
RS
CP
SH
I1A
CP SH
(line clamp mode)
t8
B/W o Color mode: 1SW (“L” o “H”)
Color o B/W mode: 2SW (“L” o “H”)
B/W o Color mode: 2SW (“H” o “L”)
Color o B/W mode: 1SW (“H” o “L”)
Video signal
Peak
t21
t19
t18
t17
10%
t16
t15 t14
t13
t9 t10
t11 t12
I2
I1
90%
90%
10% to the peak
10% to the peak
10%
OS
(line clamp mode)
OS
(bit clamp mode)
RS
CP
t20
10%
TCD2561D
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Timing Requirements (cont.)
Characteristics Symbol Min
Typ.
(Note 12) Max Unit
t1 120 1000
Pulse timing of SH and I1
t5 800 1000
ns
SH pulse rise time, fall time t2, t4 0 50 ns
SH pulse width t3 3000 5000 ns
Pulse timing of SH and CP t6 200 500 ns
Pulse timing of SH and CP
(line clamp mode) t7 10 100 ns
Pulse timing of SH and SW t8 100 500 t3 100ns
I1, I2 pulse rise time, fall time t9, t10 0 50 ns
RS pulse rise time, fall time t11, t12 0 20 ns
RS pulse width t13 10 (20) 80 ns
Pulse timing of RS and CP t14 0 40 ns
Pulse timing of I1A, I2A and CP t15 0 20 ns
CP pulse rise time, fall time t16, t17 0 20 ns
CP pulse width (Note 13) t18 30 (3000) 80 (5000) ns
Reference level settle time
(bit clamp mode) t19 20 40 (Note 16) ns
Video data delay time (Note 14) t20 20 40 (Note 15) ns
Reference level settle time
(line clamp mode) t21 30 50 (Note 16) ns
Note 12: Typ. is the case of fRS 1.0 MHz.
Note 13: Line clamp Mode inside ( ).
Note 14: Load Resistance is 100 k:.
Note 15: Typical settle time to about 1% of final value.
Note 16: Typical settle time to about 1% of the peak.
Clamp Mode
Clamp Means CP Input Pulse
Bit Clamp CP Pulse
Line Clamp “H” or SH
Changeover Switch Mode
Output Type 1SW Input Pulse 2SW Input Pulse SH Input Pulse
Color “H” “L”
SH1, 2, 3 SH Pulse,
SH0 “H”
B/W “L” “H” SH0 SH Pulse,
SH1, 2, 3 “H”
TCD2561D
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Typical Spectral Response
Wavelength O
OO
O (nm)
Spectral response
400
0
0.2
0.4
1.0
450 500 550 600 650 700
0.6
0.8
Red
Ta 25°C
Green
Blue
TCD2561D
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Typical Drive Circuit
1SW
RS CP 2SW
OS2 OS1 OD SS I2A3
OS3 SS I1A3 SS
NC I2A1 I1A1 SH0
I2A2 I1A2 SH3 SH2
SH1
21 22 19 20 17 18 15 16 14 12 13
2 1 4 3 6 5 8 7 9 11 10
TCD2561D
IC1, 2, 3 : TC74AC04
IC4, 5 : TC74HC04
12 V
47 PF/25 V
1 PF/25 V
IC4
SH0
SH1
SH2
SH3
RS
CP
12 V
1 PF/25 V
47 PF/25 V
OS3
OS2
OS1
I2A3
I1A3
IC3
5 V 1 PF/25 V
47 PF/25 V
I2A1
I1A1
IC1
5 V 1 PF/25 V
47 PF/25 V
I2A2
I1A2
IC2
5 V 1 PF/25 V
47 PF/25 V
2SW
IC5
5 V 1 PF/25 V
47 PF/25 V
1SW
5 V 1 PF/25 V
47 PF/25 V
TCD2561D
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Caution
Window Glass
The dust and stain on the glass window of the package degrade optical performance of CCD sensor.
Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and
allow the glass to dry, by blowing with filtered dry N2. Care should be taken to avoid mechanical or
thermal shock because the glass window is easily to damage.
1. Electrostatic Breakdown
Store in shorting clip or in conductive foam to avoid electrostatic breakdown.
CCD Image Sensor is protected against static electricity, but interior puncture mode device due to static
electricity is sometimes detected. In handing the device, it is necessary to execute the following static
electricity preventive measures, in order to prevent the trouble rate increase of the manufacturing system
due to static electricity.
a. Prevent the generation of static electricity due to friction by making the work with bare hands or by
putting on cotton gloves and non-charging working clothes.
b. Discharge the static electricity by providing earth plate or earth wire on the floor, door or stand of the
work room.
c. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
It is not necessarily required to execute all precaution items for static electricity.
It is all right to mitigate the precautions by confirming that the trouble rate within the prescribed
range.
2. Incident Light
CCD sensor is sensitive to infrared light. Note that infrared light component degrades resolution and
PRNU of CCD sensor.
3. Lead Frame Forming
Since this package is not strong against mechanical stress, you should not reform the lead frame.
We recommend to use a IC-inserter when you assemble to PCB.
4. Soldering
Soldering by the solder flow method cannot be guaranteed because this method may have deleterious
effects on prevention of window glass soiling and heat resistance.
Using a soldering iron, complete soldering within ten seconds for lead temperatures of up to 260°C, or
within three seconds for lead temperatures of up to 350°C.
TCD2561D
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Package Dimensions
Weight: 5.2 g (typ.)
Unit: mm
WDIP22-G-400-2.54D (G)
Note 1: TOP OF CHIP TO BOTTOM OF PACKAGE.
Note 2: GLASS THICKNESS (n 1.5)
Note 3: No.1 SENSOR ELEMENT (S1) TO EDGE OF No.1 PIN.
52.6 r 0.5
Lead frame thickness
(Note 3)
(Note 1)
(Note 2)
TCD2561D
2003-05-06
17
x TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
x The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
x The products described in this document are subject to the foreign exchange and foreign trade laws.
x The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
x The information contained herein is subject to change without notice.
000707EBA
RESTRICTIONS ON PRODUCT USE
