1OCTOBER 2008
DSC-6117/14
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
3.3 VOLT HIGH-DENSITY SUPERSYNC II™
36-BIT FIFO
65,536 x 36
131,072 x 36
IDT72V36100
IDT72V36110
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
••
••
•Choose among the following memory organizations:
IDT72V36100 ⎯⎯
⎯⎯
⎯65,536 x 36
IDT72V36110 ⎯⎯
⎯⎯
⎯131,072 x 36
••
••
•Higher density, 2Meg and 4Meg SuperSync II FIFOs
••
••
•Up to 166 MHz Operation of the Clocks
••
••
•User selectable Asynchronous read and/or write ports (PBGA Only)
••
••
•User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
••
••
•Big-Endian/Little-Endian user selectable byte representation
••
••
•5V input tolerant
••
••
•Fixed, low first word latency
••
••
•Zero latency retransmit
••
••
•Auto power down minimizes standby power consumption
••
••
•Master Reset clears entire FIFO
••
••
•Partial Reset clears data, but retains programmable settings
••
••
•Empty, Full and Half-Full flags signal FIFO status
••
••
•Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
••
••
•Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
••
••
•Program programmable flags by either serial or parallel means
••
••
•Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
••
••
•Output enable puts data outputs into high impedance state
••
••
•Easily expandable in depth and width
••
••
•JTAG port, provided for Boundary Scan function (PBGA Only)
••
••
•Independent Read and Write Clocks (permit reading and writing
simultaneously)
••
••
•Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
••
••
•Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690) family
••
••
•High-performance submicron CMOS technology
••
••
•Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
••
••
•Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
65,536 x 36
131,072 x 36
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN WCLK/WR
D
0
-D
n
(x36, x18 or x9) LD
MRS
REN
RCLK/RD
OE Q
0
-Q
n
(x36, x18 or x9)
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
6117 drw01
BUS
CONFIGURATION
BM
CONTROL
LOGIC
BE
OW
IP
PFM
FSEL0
FSEL1
IW
RM
ASYR
ASYW
JTAG CONTROL
(BOUNDARY
SCAN)
TCK
TMS
TDO
TDI
TRST
*
*
*
*
*
*
*
*
*
*
*Available on the PBGA package only.
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
PIN CONFIGURATIONS
TQFP (PK128-1, order code: PF)
TOP VIEW
DESCRIPTION:
The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls and a
flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key
user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
NOTE:
1. DNC = Do Not Connect.
VCC
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
IW
D35
D34
D33
D32
D31
VCC
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
D21
D20
D19
D18
GND
D17
D16
D15
VCC
D13
D12
GND
D11 65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
101
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
Q15
Q14
Q13
Q12
GND
Q11
Q10
INDEX
WEN
SEN
DNC(1)
D14
VCC
VCC
VCC
VCC
VCC
VCC
6117 drw02
DNC(1)
RT
REN
RCLK
PAE
PFM
EF/OR
RM
GND
VCC
BM
IP
BE
FS1
GND
HF
FS0
OW
GND
PAF
VCC
FF/IR
FWFT/SI
LD
MRS
PRS
WCLK
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
D10
D9
D8
D7
D6
GND
D5
D4
D2
D1
D0
GND
Q0
Q1
Q2
Q3
Q4
Q5
GND
Q6
Q7
Q9
104
103
Q8
VCC
VCC
D3
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
PIN CONFIGURATIONS (CONTINUED)
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
ASYW WEN WCLK PAF FF/IR HF BM EF RCLK REN OE Q35
SEN IW PRS LD MRS FS0 FS1 ASYR IP PFM RT Q34
D35 D34 D33 FWFT/SI OW VCC VCC BE PAE RM Q32 Q3
3
D32 D31 D30 VCC VCC GND GND VCC VCC Q29 Q30 Q31
D29
D26
D27 VCC Q26 Q27 Q28
D28
D25 D24 Q23 Q24 Q25
D21 D22 D23 Q22 Q21 Q20
D18 D19 D20 VCC Q19 Q18 Q17
D15 D16 D17 VCC Q16 Q15 Q14
D12 D13 D14 D3 D0 VCC VCC TDO Q2 Q13 Q12 Q11
D10 D6 D4 D1 TMS TCK Q0 Q3 Q5 Q10 Q9
D8 D7 D5 D2 TRST TDI Q1 Q4 Q6 Q7 Q8
A1 BALL PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
12 3 4 5 6 7 8 9 101112
6117 drw02b
GND GND GND GND
GND GND GND GND
VCC
GND GND GND GND
VCC GND GND VCC VCC
GND GND GND GND
D11
D9
VCC
VCC
VCC
VCC
VCC
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
DESCRIPTION (CONTINUED)
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
DESCRIPTION (CONTINUED)
Figure 1. Single Device Configuration Signal Flow Diagram
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable Almost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
BUS-
MATCHING
(BM)
(x36, x18 or x9) DATA OUT (Q
0 - Qn)(x36, x18 or x9) DATA IN (D0 - Dn)
MASTER RESET (MRS)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
WRITE CLOCK (WCLK/WR*)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72V36100
72V36110
PARTIAL RESET (PRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
6117 drw03
HALF-FULL FLAG (HF)
SERIAL ENABLE(SEN)
INPUT WIDTH (IW) OUTPUT WIDTH (OW)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
BM IW OW Write Port Width Read Port Width
L L L x36 x36
H L L x36 x18
H L H x36 x9
H H L x18 x36
H H H x9 x36
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer
to Figure 13 and 14 for Zero Latency Retransmit Timing.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effect during parallel programming of the offset registers. It does not effect the data
written to and read from the FIFO.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V36100/72V36110 are fabricated using IDT’s high speed
submicron CMOS technology.
NOTE:
1. Pin status during Master Reset.
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
PIN DESCRIPTION (TQFP AND PBGA PACKAGES)
Symbol Name I/O Description
BM(1) Bus-Matching I BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
BE(1) Big-Endian/ I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will
Little-Endian select Little-Endian format.
D0–D35 Data Inputs I Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
EF/OR Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
Output Ready In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the
Input Ready FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO
memory.
FSEL0(1) Flag Select Bit 0 I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable
flags PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1 I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable
flags PAE and PAF. There are up to eight possible settings available.
FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions
Through/Serial In as a serial input for loading offset registers.
HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full.
IP(1) Interspersed Parity I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not
effect the data written to and read from the FIFO.
IW(1) Input Width I This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
LD Load I This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines
one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
OE Output Enable I OE controls the output impedance of Qn.
OW(1) Output Width I This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency
timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PFM(1) Programmable I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode will select Synchronous Programmable flag timing mode.
PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all
retained.
Q0–Q35 Data Outputs O Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state. Outputs are not 5V tolerant regardless of the state of OE.
RCLK/ Read Clock/ I If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
RD Read Strobe reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operation of the RCLK/RD input is only available in the PBGA package.
REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers.
RM(1) Retransmit Timing I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode normal latency mode.
RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
NOTE:
1. Inputs should not change state after Master Reset.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 43-47 and Figures 31-33.
PIN DESCRIPTION (PBGA PACKAGE ONLY)
Symbol Name I/O Description
ASYR(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW(1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port will select Asynchronous operation.
TCK(2) JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2) JTAG Test Data I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Input serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2) JTAG Test Data O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Output serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(2) JTAG Mode I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2) JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon
power-up. If the JTAG function is not used then this signal should to be tied to GND.
PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES)
SEN Serial Enable I SEN enables serial loading of programmable flag offsets.
WCLK/ Write Clock/ I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
WR Write Strobe writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO
on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation of
the WCLK/WR input is only available in the PBGA package.
WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers.
VCC +3.3V Supply I These are VCC supply inputs and must be connected to the 3.3V supply rail.
Symbol Name I/O Description
NOTE:
1. Inputs should not change state after Master Reset.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com’l & Ind’l Unit
VTERM(2) Terminal Voltage –0.5 to +4.5 V
with respect to GND
TSTG Storage –55 to +125 °C
Temperature
IOUT DC Output Current –50 to +50 mA
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminal only.
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Max. Unit
CIN(2) Input VIN = 0V 10 pF
Capacitance
COUT(1,2) Output VOUT = 0V 10 pF
Capacitance
Symbol Parameter Min. Typ. Max. Unit
VCC(1) Supply Voltage Com’l/Ind’l 3.15 3.3 3.45 V
GND Supply Voltage Com’l/Ind’l 0 0 0 V
VIH(2) Input High Voltage Com’l/Ind’l 2.0 — 5.5 V
VIL(3) Input Low Voltage Com’l/Ind’l — — 0.8 V
TAOperating Temperature 0 — 70 °C
Commercial
TAOperating Temperature -40 — 85 °C
Industrial
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2 . Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
IDT72V36100L
IDT72V36110L
Commercial and Industrial(1)
tCLK = 6, 7-5, 10, 15 ns
Symbol Parameter Min. Max. Unit
ILI(2) Input Leakage Current –1 1 µA
ILO(3) Output Leakage Current –10 10 µA
VOH Output Logic “1” Voltage, IOH = –2 mA 2 .4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA — 0. 4 V
ICC1(4,5,6) Active Power Supply Current — 40 mA
ICC2(4,7) Standby Current — 15 mA
NOTES:
1. Industrial temperature range product for the 7-5ns and 15ns speed grade are available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 4.2 + 1.4*fS + 0.002*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
RECOMMENDED DC OPERATING
CONDITIONS
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 7-5ns and 15ns are available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7-5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.
Commercial Com’l & Ind’l(2) Commercial Com’l & Ind’l(2)
PBGA & TQFP PBGA & TQFP TQFP Only TQFP Only
IDT72V36100L6 IDT72V36100L7-5 IDT72V36100L10 IDT72V36100L15
IDT72V36110L6 IDT72V36110L7-5 IDT72V36110L10 IDT72V36110L15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fSClock Cycle Frequency — 166 — 133.3 — 100 — 66.7 MHz
tAData Access Time(5) 141
(5) 51
(5) 6.5 1(5) 10 ns
tCLK Clock Cycle Time 6 — 7.5 — 10 — 15 — ns
tCLKH Clock High Time 2 .7 — 3. 5 — 4 .5 — 6 — n s
tCLKL Clock Low Time 2 .7 — 3. 5 — 4. 5 — 6 — ns
tDS Data Setup Time 2 — 2.5 — 3.5 — 4 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tENS Enable Setup Time 2 — 2.5 — 3.5 — 4 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tLDS Load Setup Time 3 — 3.5 — 3.5 — 4 — ns
tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tRS Reset Pulse Width(3) 10 — 10 — 10 — 15 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tRSR Reset Recovery Time 10 — 10 — 1 0 — 15 — ns
tRSF Reset to Flag and Output Time — 15 — 15 — 15 — 15 ns
tRTS Retransmit Setup Time 3 — 3.5 — 3.5 — 4 — ns
tOLZ Output Enable to Output in Low Z(4) 0—0—0 —0—ns
tOE Output Enable to Output Valid(5) 141
(5) 61
(5) 61
(5) 8ns
tOHZ Output Enable to Output in High Z(4,5) 141
(5) 61
(5) 61
(5) 8ns
tWFF Write Clock to FF or IR —4—5—6.5—10ns
tREF Read Clock to EF or OR —4—5—6.5—10ns
tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 10 — 12.5 — 16 — 20 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 4 — 5 — 6.5 — 10 ns
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 10 — 12.5 — 16 — 20 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 4 — 5 — 6.5 — 10 ns
tHF Clock to HF — 10 — 12.5 — 16 — 20 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 4—5—7 —9—ns
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 5—7—10—14—ns
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
AC ELECTRICAL CHARACTERISTICS(1) — ASYNCHRONOUS TIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial Com’l & Ind’l
IDT72V36100L6 IDT72V36100L7-5
IDT72V36110L6 IDT72V36110L7-5
Symbol Parameter Min. Max. Min. Max. Unit
fA(4) Cycle Frequency (Asynchronous mode) — 1 00 — 8 3 MHz
tAA(4) Data Access Time 0.6 8 0.6 10 ns
tCYC(4) Cycle Time 10 — 12 — ns
tCYH(4) Cycle HIGH Time 4.5 — 5 — ns
tCYL(4) Cycle LOW Time 4 .5 — 5 — n s
tRPE(4) Read Pulse after EF HIGH 8 — 10 — n s
tFFA(4) Clock to Asynchronous FF —8—10ns
tEFA(4) Clock to Asynchronous EF —8—10ns
tPAFA(4) Clock to Asynchronous Programmable Almost-Full Flag — 8 — 1 0 ns
tPAEA(4) Clock to Asynchronous Programmable Almost-Empty Flag — 8 — 10 ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Parameters apply to the PBGA package only.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
6117 drw04
330Ω
30pF*
510Ω
3.3V
D.U.T.
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns(1)
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load for tCLK = 10ns, 15 ns See Figure 2a
Output Load for tCLK = 6ns, 7.5ns See Figure 2b & 2c
AC TEST CONDITIONS
Figure 2b. AC Test Load
Figure 2c. Lumped Capacitive Load, Typical Derating
AC TEST LOADS - 6ns, 7.5ns Speed Grade
Figure 2a. Output Load
* Includes jig and scope capacitances.
AC TEST LOADS - 10ns, 15ns Speed Grades
NOTE:
1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns.
6117 drw04a
50Ω
1.5V
I/O Z0 = 50Ω
6117 drw04b
6
5
4
3
2
1
20 30 50 80 100 200
Ca
p
acitance
(p
F
)
tCD
(Typical, ns)
VIH
OE
VIL
t
OE &
t
OLZ
V
CC
2
V
CC
2
100mV
100mV
t
OHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
VOL
VOH
V
CC
2
V
CC
2
6117 drw04c
Output
Enable
Output
Disable
OUTPUT ENABLE & DISABLE TIMING
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
to the FIFO. D = 65,536 writes for the IDT72V36100 and 131,072 writes for
the IDT72V36110, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7,8,11 and 13.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 32,770th
word for the IDT72V36100 and 65,538th word for the IDT72V36110, respec-
tively was written into the FIFO. Continuing to write data into the FIFO will cause
the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (65,537-m) writes for the IDT72V36100 and (131,073-m) writes for the
IDT72V36110, where m is the full offset value. The default setting for these
values are stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 65,537 writes for the IDT72V36100 and 131,073
writes for the IDT72V36110, respectively. Note that the additional word in FWFT
mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10, 12,
and 14.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V36100/72V36110 support two different timing modes of
operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by the
state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 32,769th word for the IDT72V36100 and 65,537th word for the IDT72V36110,
respectively was written into the FIFO. Continuing to write data into the FIFO
will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no
reads are performed, the PAF will go LOW after (65,536-m) writes for the
IDT72V36100 and (131,072-m) writes for the IDT72V36110. The offset “m”
is the full offset value. The default setting for these values are stated in the footnote
of Table 2. This parameter is also user programmable. See section on
Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time after
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
The IDT72V36100/72V36110 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous
PAF timing and Figure 18 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
19 for asynchronous PAF timing and Figure 20 for asynchronous PAE timing.
IDT72V36100, 72V36110
LD FSEL1 FSEL0 Offsets n,m
L H L 16,383
L L H 8,191
L H H 4,095
H H L 2,047
H L L 1,023
HLH511
HHH255
LLL127
LD FSEL1 FSEL0 Program Mode
H X X Serial(3)
L X X Parallel(4)
TABLE 2 — DEF AULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2 . m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72V36100/
72V36110 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
00
1 to n(1) 1 to n (1)
(n+1) to 32,768 (n+1) to 65,536
32,769 to (65,536-(m+1)) 65,537 to (131,072-(m+1))
(65,536-m) to 65,535 (131,072-m) to 131,071
65,536 131,072
IDT72V36100 IDT72V36110 FF PAF HF PAE EF
HH
HL L
HH
HL H
HH
HHH
HHLH H
HLLH H
LL
LH H
Number of
Words in
FIFO
6117 drw05
00
1 to n+1 1 to n+1
(n+2) to 32,769 (n+2) to 65,537
32,770 to (65,537-(m+1)) 65,538 to (131,073-(m+1))
(65,537-m) to 65,536 (131,073-m) to 131,072
65,537 131,073
IDT72V36100 IDT72V36110 IR PAF HF PAE OR
LH
HL H
LH
HL L
LH
HHL
LHLHL
LLLHL
HL LHL
Number of
Words in
FIFO
NOTE:
1. See table 2 for values for n, m.
NOTE:
1. See table 2 for values for n, m.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 3. Programmable Flag Offset Programming Sequence
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK RCLK
X
X
XX
X
X
XX
LD
0
0
X
1
1
1
0
WEN
0
1
1
0
X
1
1
REN
1
0
1
X
0
1
1X
SEN
1
1
1
X
X
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
IDT72V36100
IDT72V36110
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
Ending with Full Offset (MSB)
32 bits for the 72V36100
34 bits for the 72V36110
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
6117 drw06
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
D/Q17 D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
Data Inputs/Outputs
# of Bits Used
1234
56789101112131415
16
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
2nd Parallel Offset Write/Read Cycle
12345678
10
11
1213
1415 9
FULL OFFSET (LSB) REGISTER (PAF)12345678910
1112
13
1415
16 1
2345678
1011121314
15 9
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q8
D/Q8
16
16
D/Q17
D/Q16
IDT72V36100 ⎯ x18 Bus Width
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
6117 drw07
D/Q17 D/Q0
D/Q8
EMPTY OFFSET REGISTER (PAE)
# of Bits Used
234
5
67
910111213
14
15
16
1st Parallel Offset Write/Read Cycle
23456781213
1415
1617 11
Interspersed
Parity
17 10 1
1
8
D/Q35 D/Q19
9
D/Q17 D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
# of Bits Used
234
5
67
910111213
14
15
16
2nd Parallel Offset Write/Read Cycle
23456781213
1415
1617 11
Interspersed
Parity
17 10 1
1
8
9
IDT72V36100/IDT72V36110 ⎯ x36 Bus Width
Non-Interspersed
Parity
Non-Interspersed
Parity
D/Q35 D/Q19
D/Q17 D/Q0D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
Data Inputs/Outputs
# of Bits Used
1234
56789101112131415
EMPTY OFFSET (MSB) REGISTER (PAE)
Data Inputs/Outputs
17
16
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
Data Inputs/Outputs
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
1234
5678
10
11
1213
1415 9
FULL OFFSET (LSB) REGISTER (PAF)12345678910
1112
13
1415
16 1
2345678
1011121314
15 9
FULL OFFSET (MSB) REGISTER (PAF)17
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q0
D/Q0
D/Q8
D/Q8
16
16
17
17
D/Q17 D/Q16
D/Q17
D/Q16
D/Q17 D/Q16
IDT72V36110 ⎯ x18 Bus Width
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
D/Q8 D/Q0
EMPTY OFFSET REGISTER (PAE)
1234567
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8 D/Q0
EMPTY OFFSET REGISTER (PAE)
9101112
13
14
15
16
D/Q8 D/Q0
FULL OFFSET REGISTER (PAF)
12
34
5
678
D/Q8 D/Q0
EMPTY OFFSET REGISTER (PAE)
17
5th Parallel Offset Write/Read Cycle
D/Q8 D/Q0
FULL OFFSET REGISTER (PAF)
9
101112
13
14
15
16
6th Parallel Offset Write/Read Cycle
D/Q8 D/Q0
17
FULL OFFSET REGISTER (PAF)
IDT72V36110 ⎯
x9 Bus Width
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
6117 drw07a
D/Q8 D/Q0
EMPTY OFFSET REGISTER (PAE)
1234567
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
D/Q8 D/Q0
EMPTY OFFSET REGISTER (PAE)
9101112
13
14
15
16
D/Q8 D/Q0
FULL OFFSET REGISTER (PAF)
12
34
5
678
4th Parallel Offset Write/Read Cycle
D/Q8 D/Q0
FULL OFFSET REGISTER (PAF)
9
101112
13
14
15
16
IDT72V36100 ⎯
x9 Bus Width
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written,
one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 32 bits for the IDT72V36100 and 34 bits for
the IDT72V36110. See Figure 15, Serial Loading of Programmable Flag
Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI input
and then, by bringing LD and SEN HIGH, data can be written to FIFO memory
via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN
restored to a LOW, the next offset bit in sequence is written to the registers via
SI. If an interruption of serial programming is desired, it is sufficient either to set
LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD
and SEN are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceeds as follows: LD and WEN must be set LOW. For x36 bit input bus width,
data on the inputs Dn are written into the Empty Offset Register on the first LOW-
to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of
WCLK, data are written into the Full Offset Register. The third transition of WCLK
writes, once again, to the Empty Offset Register. For x18 bit input bus width,
data on the inputs Dn are written into the Empty Offset Register LSB on the first
LOW-to-HIGH transition of WCLK. Upon the 2nd LOW-to-HIGH transition of
WCLK data are written into the Empty Offset Register MSB. The third transition
of WCLK writes to the Full Offset Register LSB, the fourth transition of WCLK then
writes to the Full Offset Register MSB. The fifth transition of WCLK writes once
again to the Empty Offset Register LSB. A total of four writes to the offset registers
is required to load values using a x18 input bus width. For an input bus width
of x9 bits, a total of six write cycles to the offset registers is required to load values.
See Figure 3, Programmable Flag Offset Programming Sequence. See
Figure 16, Parallel Loading of Programmable Flag Registers, for the timing
diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing LD HIGH, write operations can be redirected to
the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offset
register in sequence is written to. As an alternative to holding WEN LOW and
toggling LD, parallel programming can also be interrupted by setting LD LOW
and toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when LD is set LOW and REN is set LOW. For x36 output bus width, data
are read via Qn from the Empty Offset Register on the first LOW-to-HIGH
transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are
read from the Full Offset Register. The third transition of RCLK reads, once
again, from the Empty Offset Register. For x18 output bus width, a total of four
read cycles are required to obtain the values of the offset registers. Starting with
the Empty Offset Register LSB and finishing with the Full Offset Register MSB.
For x9 output bus width, a total of six read cycles must be performed on the offset
registers. See Figure 3, Programmable Flag Offset Programming Sequence.
See Figure 17, Parallel Read of Programmable Flag Registers, for the timing
diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW. At least two words,
but no more than D - 2 words should have been written into the FIFO, and read
from the FIFO, between Reset (Master or Partial) and the time of Retransmit
setup. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,
the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK
that RT is setup will update HF. PAF is synchronized to WCLK, thus the second
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT
is setup will update PAF. RT is synchronized to RCLK.
The Retransmit function has the option of two modes of operation, either
“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Data inputs for 36-bit wide data (D0 - D35), data inputs for 18-bit wide data
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
CONTROLS:
MASTER RESET ( MRS )
A Master Reset is accomplished whenever the MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined
during the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET ( PRS )
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
ASYNCHRONOUS WRITE (ASYW)
The write port can be configured for either Synchronous or Asynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchronous
operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write
port in Asynchronous mode).
When the write port is configured for Asynchronous operation the full flag
(FF) operates in an asynchronous manner, that is, the full flag will be updated
based in both a write operation and read operation. Note, if Asynchronous mode
is selected, FWFT is not permissable. Refer to Figures 23, 24, 27 and 28 for
relevant timing and operational waveforms.
ASYNCHRONOUS READ (ASYR)
The read port can be configured for either Synchronous or Asynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
Asynchronous operation of the read port will be selected. During Asynchronous
operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operation of the read port).
The OE input provides three-state control of the Qn output bus, in an
asynchronous manner.
When the read port is configured for Asynchronous operation the device
must be operating on IDT standard mode, FWFT mode is not permissible if the
read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to figures 25, 26, 27 and 28 for relevant timing and
operational waveforms.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of the memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
In Retransmit operation, zero latency mode can be selected using the
Retransmit Mode (RM) pin during a Master Reset. This can be applied to both
IDT Standard mode and FWFT mode.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Qn after three RCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
If Synchronous operation of the write port has been selected via ASYW, this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
If Asynchronous operation has been selected this input is WR (write strobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE ( WEN )
When the WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
If Asynchronous operation of the write port has been selected, then WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
If Synchronous operation of the read port has been selected via ASYR, this
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE
and HF flags will not be updated. (Note that RCLK is only capable of updating
the HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the REN input must be
tied LOW. The OE input is used to provide Asynchronous control of the three-
state Qn outputs.
READ ENABLE ( REN )
When Read Enable is LOW, data is loaded from the RAM array into the output
register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the last
word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting
further read operations. REN is ignored when the FIFO is empty. Once a write
is performed, EF will go HIGH allowing a read to occur. The EF flag is updated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write. REN does not need to be asserted LOW. In order to access
all other words, a read must be executed using REN. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read
operations. REN is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then REN
must be held active, (tied LOW).
SERIAL ENABLE ( SEN )
The SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset. SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Qn) goes
into a high impedance state.
LOAD ( LD )
This is a dual purpose pin. During Master Reset, the state of the LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
After Master Reset, the LD pin is used to activate the programming process
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values.
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
BUS-MATCHING (BM, IW, OW)
The pins BM, IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 4 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Programmable
flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,
LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.
A HIGH will select Interspersed Parity mode. The IP bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effect during parallel programming of the offset registers. It does not effect the data
written to and read from the FIFO.
OUTPUTS:
FULL FLAG ( FF/IR )
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110). See
Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevant timing information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO (D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110).
See Figure 9, Write Timing (FWFT Mode), for the relevant timing information.
The IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
EMPTY FLAG ( EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts
the last word from the FIFO memory to the outputs. OR goes HIGH only with
a true read (RCLK with REN = LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until OR goes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (65,536-m) writes for the IDT72V36100
and (131,072-m) writes for the IDT72V36110. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAF will go LOW after (65,537-m) writes for the
IDT72V36100 and (131,073-m) writes for the IDT72V36110, where m is the
full offset value. The default setting for this value is stated in Table 2.
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
If asynchronous PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
HALF-FULL FLAG ( HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536 for the
IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
IDT72V36100 and 131,073 for the IDT72V36110.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
DATA OUTPUTS (Q0-Qn)
(Q0-Q35) are data outputs for 36-bit wide data, (Q0 - Q17) are data outputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
D35-D27 D26-D18 D17-D9 D8-D0
A
A
A
D
A
C
B
B
B
C
B
D
C
C
C
A
D
D
D
B
(a) x36 INPUT to x36 OUTPUT
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Write to FIFO
Read from FIFO
1st: Read from FIFO
BE BM IW OW
BYTE ORDER ON INPUT PORT:
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
1st: Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
2nd: Read from FIFO
D
C
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
1st: Read from FIFO
A
B
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
6117 drw08
BYTE ORDER ON OUTPUT PORT:
L H L L
H H L L
L H L H
H H L H
X L L L
BE BM IW OW
BE BM IW OW
BE BM IW OW
BE BM IW OW
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Figure 4. Bus-Matching Byte Arrangement
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
A
A
D
A
C
B
B
C
B
D
CD
D35-D27 D26-D18 D17-D9 D8-D0
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Read from FIFO
1st: Write to FIFO
BYTE ORDER ON INPUT PORT:
2nd: Write to FIFO
3rd: Write to FIFO
4th: Write to FIFO
D35-D27 D26-D18 D17-D9 D8-D0
1st: Write to FIFO
2nd: Write to FIFO
6117 drw09
BYTE ORDER ON OUTPUT PORT:
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
CDAB
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Read from FIFO
BE BM IW OW
H H H L
BYTE ORDER ON INPUT PORT:
ABCD
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
Read from FIFO
BE BM IW OW
L H H H
BYTE ORDER ON OUTPUT PORT:
DCBA
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Read from FIFO
BE BM IW OW
H H H H
BE BM IW OW
L H H L
D35-D27 D26-D18 D17-D9 D8-D0
D35-D27 D26-D18 D17-D9 D8-D0
D35-D27 D26-D18 D17-D9 D8-D0
D35-D27 D26-D18 D17-D9 D8-D0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Q35-Q27 Q26-Q18 Q17-Q9 Q8-Q0
Figure 4. Bus-Matching Byte Arrangement (Continued)
26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 5. Master Reset Timing
tRS
MRS
tRSR
REN
tRSS
FWFT/SI
6117 drw10
tRSR
tRSR
WEN
FSEL0,
FSEL1
RT
SEN
tRSF
tRSF
OE = HIGH
OE = LOW
PAE
PAF, HF
Q0 - Qn
tRSF
EF/OR
FF/IR
tRSF
tRSF If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
tRSS
tRSS
tRSS
BM,
OW, IW
BE
RM
PFM
IP
tRSS
LD
tRSR
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
tRSS
ASYW,
ASYR
tRSS
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 6. Partial Reset Timing
tRS
PRS
tRSR
REN
tRSS
6117 drw11
tRSR
WEN
RT
SEN
tRSF
tRSF
OE = HIGH
OE = LOW
PAE
PAF, HF
Q0 - Qn
tRSF
EF/OR
FF/IR
tRSF
tRSF If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
tRSS
tRSS
tRSS
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
RCLK
REN
6117 drw13
EF
t
CLK
t
CLKH
t
CLKL
t
ENH
t
REF
t
A
t
OLZ
t
OE
Q0 - Qn
OE
WCLK
(1)
t
SKEW1
WEN
D0 - Dn
t
ENS
t
ENS
t
ENH
t
DS
t
DH
D
0
12
t
OLZ
NO OPERATION
LAST WORD D
0
D
1
D
1
t
ENS
t
ENH
t
DS
t
DH
t
OHZ
LAST WORD
t
REF
t
ENH
t
ENS
t
A
t
A
t
REF
t
ENS
t
ENH
D
0
- D
n
WEN
RCLK
REN
t
ENH
t
ENH
Q
0
- Q
nDATA READ NEXT DATA READDATA IN OUTPUT REGISTER
t
SKEW1
(1)
6117 drw12
WCLK
NO WRITE
1212
t
DS
NO WRITE
t
WFF
t
WFF
t
WFF
t
A
t
ENS
t
ENS
t
SKEW1
(1)
t
DS
t
A
D
X
t
DH
t
CLK
t
CLKH
t
CLKL
D
X
+1
t
WFF
t
DH
FF
29
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 9. Write Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
- D
17
RCLK
t
DH
t
DS
t
SKEW1
(1)
REN
Q
0
- Q
17
PAF
HF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
HF
t
PAFS
t
WFF
W
[D-m+2]
W
1
t
ENH
6117 drw14
DATA IN OUTPUT REGISTER
(2)
W
3
123
1
D-1
2+1][
W
D-1
+2][
W2
D-1
+3][
W2
12
t
ENS
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 10. Read Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
WCLK 12
WEN
D0 - D17
RCLK
t
ENS
REN
Q0 - Q17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
t
OHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
OE
t
A
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
OE
t
SKEW2
W
D
6117 drw15
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
t
HF
t
REF
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1) (2)
t
ENS
D-1 + 1
][
W
2D-1 + 2
][
W
2
1
31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4 . No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
t
REF
t
RTS
t
ENH
6117 drw16
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q0 - Qn
t
SKEW2
12
1
W
1
t
PAFS
t
HF
t
PAES
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
t
RTS
t
ENS
t
ENH
(3)
t
A
t
A
(3)
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
t
REF
t
RTS
t
ENH
6117 drw17
t
ENS
W
x
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
t
PAFS
t
HF
t
PAES
t
REF
W
x+1
2
W
2
t
ENH
t
RTS
WEN
t
ENS
W
1
t
ENS
(4)
34
t
ENH
W
3
t
A
t
A
t
A
W
4
t
A
(4) (4)
33
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4 . No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
t
RTS
t
ENH
6117 drw18
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
W
3(3)
t
PAFS
t
HF
t
PAES
W
x+1
2
W
4
WEN
t
ENS
t
ENH
t
A
t
A
3
t
A
t
A
W
2(3)
W
1(3)
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1 . X = 15 for the IDT72V36100 and X = 16 for the IDT72V36110.
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
SEN
SI
6117 drw20
t
ENH
t
ENS
t
LDS
LD
t
DS
BIT 0
EMPTY OFFSET
BIT X BIT 0
FULL OFFSET
(1)
t
ENH
BIT X (1)
t
LDH
t
DH
t
LDH
tRTS
tENH
6117 drw19
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0
- Q
n
tSKEW2
12
1
tPAFS
tHF
tPAES
Wx+1
2
W3
WEN
tENS
W2(4)
45
tENH
W4
tA
tA
tA
W5
tA
(4) (4)
3
tA
W1
35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
WCLK
WEN
PAF
RCLK
(3)
t
PAFS
REN
6117 drw 23
D - (m+1) words in FIFO
(2)
D - m words in FIFO
(2)
1212
D-(m+1) words
in FIFO
(2)
t
PAFS
t
ENH
t
ENS
t
SKEW2
t
ENH
t
ENS
t
CLKL
t
CLKL
RCLK
LD
REN
Q
0
- Q
n
tLDH
tLDS
tENS
DATA IN OUTPUT REGISTER PAE OFFSET PAF OFFSET
tENH tENH
tLDH
6117 drw 22
t
CLK
tAtA
tCLKH tCLKL
WCLK
LD
WEN
D0 - Dn
6117 drw 21
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4.
tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode:
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAF
t
ENS
t
PAFA
D - (m + 1) words
in FIFO
RCLK
t
PAFA
REN
6117 drw25
D - m words
in FIFO
D - (m + 1) words in FIFO
WCLK
tENH
tCLKH tCLKL
WEN
PAE
RCLK
tENS
n words in FIFO
(2),
n+1 words in FIFO
(3)
tPAES
tSKEW2 tPAES
12 12
(4)
REN
6117 drw 24
tENS tENH
n+1 words in FIFO
(2),
n+2 words in FIFO
(3)
n words in FIFO
(2),
n+1 words in FIFO
(3)
37
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
t
HF
RCLK
t
HF
REN
6117 drw27
t
CLKL
t
CLKH
D/2 words in FIFO
(1)
,
[ + 1] words in FIFO
(2)
D-1
2
D/2 + 1 words in FIFO
(1)
,
[ + 2] words in FIFO
(2)
D/2 words in FIFO
(1)
,
[ + 1] words in FIFO
(2)
D-1
2D-1
2
WCLK
tCLKH tCLKL
tENS tENH
WEN
PAE
tENS
tPAEA n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
RCLK
tPAEA
REN
6117 drw26
n words in FIFO(2),
n + 1 words in FIFO(3)
38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
NOTE:
1. OE = LOW and WEN = LOW.
NOTE:
1. OE = LOW and WEN = LOW.
RCLK
REN
6117 drw28
FF
Qn W
0
t
A
W
1
t
ENH
t
ENS
t
FFA
t
FFA
t
FFA
WR t
CYH
Dn
t
DS
W
D
t
DH
W
D+1
t
CYC
RCLK
REN
6117 drw29
Qn Last Word
t
A
W
0
t
ENH
t
ENS
t
SKEW
WR
Dn W
0
t
DH
12
t
A
W
1
t
REF
t
REF
EF
t
CYL
t
DS
t
CYH
W
1
t
DH
t
DS
t
CYC
39
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
WCLK
WEN
6117 drw30
Qn
t
SKEW
RD
Dn D
F
12
t
WFF
t
WFF
FF
t
CYL
t
CYH
Last Word
No Write
D
F+1
t
AA
W
X
t
AA
W
X+1
t
CYC
WCLK
WEN
6117 drw31
Qn Last Word in Output Register W
0
RD
Dn
t
EFA
EF
t
CYH
t
ENS
t
ENH
W
0
t
DS
t
DH
t
EFA
t
AA
t
RPE
40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
6117 drw32
Qn Last Word in O/P Register
tAA
W0
tCYH
WR
Dn W0
tDH
tAA
W1
tEFA
tEFA
EF
tCYL
W1
tDH
tDS
RD
tCYC
tRPE
6117 drw33
t
CYH
WR
Dn W
y
t
DH
t
FFA
FF
t
CYL
t
DS
W
y+1
t
DH
t
DS
RD
W
x
t
AA
W
x+1
W
x+2
Qn
t
FFA
t
CYC
t
CYH
t
CYL
t
CYC
t
AA
41
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
Figure 29. Block Diagram of 65,536 x 72 and 131,072 x 72 Width Expansion
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
Figure 29 demonstrates a width expansion using two IDT72V36100/
72V36110 devices. D0 - D35 from each device form a 72-bit wide input bus and
Q0-Q35 from each device form a 72-bit wide output bus. Any word width can
be attained by adding additional IDT72V36100/72V36110 devices.
WRITE CLOCK (WCLK)
m + n m n
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
nm + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72V36100
72V36110
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
6117 drw34
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
IDT
72V36100
72V36110
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 30. Block Diagram of 131,072 x 36 and 262,144 x 36 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V36100 can easily be adapted to applications requiring depths
greater than 65,536 and 131,072 for the IDT72V36110, with an 36-bit bus width.
In FWFT mode, the FIFOs can be connected in series (the data outputs of one
FIFO connected to the data inputs of the next) with no external logic necessary.
The resulting configuration provides a total depth equivalent to the sum of the
depths associated with each single FIFO. Figure 30 shows a depth expansion
using two IDT72V36100/72V36110 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK period.
Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK READ CLOCK
RCLK
REN
OE OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
IDT
72V36100
72V36110
TRANSFER CLOCK
6117 drw35
n
n n
FWFT/SI FWFT/SI
FWFT/SI
IDT
72V36100
72V36110
43
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 31. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pf loading on external output signals.
t
DS
t
DH
TDO
TDO
TDI/
TMS
TCK
TRST
(1)
t
DO
6117 drw36
t
JRSR
t
JRST
t
TCK
t
JTCKR
t
JTCKH
t
JTCKL
t
JTCKF
IDT72V36100
IDT72V36110
Parameter Symbol Test Conditions Min. Max. Units
Data Output tDO(1) -20ns
Data Output Hold tDOH(1) 0-ns
Data Input tDS trise=3ns 10 - ns
tDH tfall=3ns 10 -
NOTE:
1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
Parameter Symbol Test
Conditions Min. Max. Units
JTAG Clock Input Period tTCK - 100 - ns
JTAG Clock HIGH tJTCKH -40-ns
JTAG Clock Low tJTCKL -40-ns
JTAG Clock Rise Time tJTCKR --5
(1) ns
JTAG Clock Fall Time tJTCKF --5
(1) ns
JTAG Reset tJRST -50-ns
JTAG Reset Recovery tJRSR -50-ns
JTAG AC ELECTRICAL
CHARACTERISTICS
(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)
NOTE:
1. Guaranteed by design.
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V36100/72V36110
incorporates the necessary tap controller and modified pad cells to implement
the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of four basic elements:
•Test Access Port (TAP)
•TAP controller
•Instruction Register (IR)
•Data Register Port (DR)
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 32. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
T
A
P
TAP
Cont-
roller
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
clkDR, ShiftDR
UpdateDR
TDO
TDI
TMS
TCLK
TRST
clklR, ShiftlR
UpdatelR
Instruction Register
Instruction Decode
Control Signals
6117 drw37
45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
Figure 33. TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
1
0
0
Select-
DR-Scan
Select-
IR-Scan
111
Capture-IR
0
Capture-DR
0
0
Exit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
10
1
1
1
6117 drw38
0
Shift-DR
0
0
0
Shift-IR
0
0
Pause-IR
0
1
Input = TMS
0
0
1
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram.
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the Queue and must be reset after power up of the device. See TRST
description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling
the normal operation of the IC. The TAP controller state machine is designed
in such a way that, no matter what the initial state of the controller is, the Test-
Logic-Reset state can be entered by holding TMS at high and pulsing TCK five
times. This is the reason why the Test Reset (TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the Pause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
NOTE:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
For the IDT72V36100/72V36110, the Part Number field contains the
following values:
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
•Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e.IR3, IR2, IR1, IR0) to decode 16
different possible instructions. Instructions are decoded as follows.
Hex Instruction Function
Value
0x00 EXTEST Select Boundary Scan Register
0x02 IDCODE Select Chip Identification data register
0x01 SAMPLE/PRELOAD Select Boundary Scan Register
0x03 HIGH-IMPEDANCE JTAG
0x0F BYPASS Select Bypass Register
Table 6. JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST pin or by otherwise moving to the
Test-Logic-Reset state.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
Device Part# Field
IDT72V36100 04DE
IDT72V36110 04DF
IDT72V36100/72V36110 JTAG Device Identification Register
31(MSB) 28 27 12 11 1 0(LSB)
V ersion (4 bits) Part Number (16-bit) Manufacturer ID (1 1-bit)
0X0 0X33 1
47
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
OCTOBER 22, 2008
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
48
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
Thin Plastic Quad Flatpack (TQFP, PK128-1)
Plastic Ball Grid Array (PBGA, BB144-1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
65,536 x 36 ⎯ 3.3V SuperSync II™ FIFO
131,072 x 36 ⎯ 3.3V SuperSync II™ FIFO
6117 drw39
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Commercial Only, PBGA & TQFP
Com‘l & Ind’l, PBGA & TQFP
Commercial, TQFP Only
Com'l & Ind'l, TQFP Only
6
7-5
10
15
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I
(1)
72V36100
72V36110
PF
BB
L
X
Green
G
(2)
NOTES:
1. Industrial temperature range product for 7-5ns and 15ns are available as standard device. All other speed grades are available by special order.
2. Green parts are available. For specific speeds and packages contact you sales office.
DATASHEET DOCUMENT HISTORY
05/25/2000 pgs. 1, 6, 7, 8, 34, and 35.
07/28/2000 pgs. 13, 14, and 34.
12/14/2000 pgs. 6, 7, and 8.
03/27/2001 pg. 7.
04/06/2001 pgs. 4, 5, and 18.
12/14/2001 pgs. 1-36.
12/16/2002 pgs. 1-11, 20, 21, 26, and 38-47.
02/11/2003 pgs. 7, and 45.
06/26/2003 pgs. 1, 3, 9, 10, and 47.
07/15/2003 pgs. 3, 20, and 38-40.
07/21/2003 pgs. 7, 43, and 45-47.
09/29/2003 pg. 8.
11/02/2005 pgs. 1, 8-10, and 48.
04/06/2006 pg. 4.
10/22/2008 pg. 48.
