1
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc. DSC-3251/6
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4µ µ
µ µ
µ W typ. static)
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT163601A
3.3V CMOS 18-BIT
UNIVERSAL BUS
TRANSCEIVER WITH
3-STATE OUTPUTS
DESCRIPTION:
The FCT163601/A 18-bit registered transceiver is built using advanced
dual metal CMOS technology. These 18-bit universal bus transceivers
combine D-type latches and D-type flip-flops to allow data flow in transpar-
ent, latched and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-
bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB.
Output enable OEAB is active low. When OEAB is low, the outputs are active.
When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA
and CLKENBA.
The FCT163601 has series current limiting resistors. These offer low
ground bounce, minimal undershoot, and controlled output fall times-
reducing the need for external series terminating resistors.
LEAB
CLKAB
LEBA
CLKBA
CLKENAB
OEAB
A1
TO 17 OTHER CHANNELS
OEBA
CE
1D
C1
CLK
CE
1D
C1
CLK
CLKENBA
1
56
55
2
28
30
29
27
354 B1
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to 7 V
VTERM(4) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +60 mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
COUT Output Capacitance VOUT = 0V 3.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
PIN CONFIGURATION
TSSOP
TOP VIEW
CLKENAB
B2
B3
GND
B4
B5
VCC
B6
B7
B1
B8
B9
B10
B11
GND
B12
B13
VCC
B14
GND
CLKAB
B16
B15
B17
GND
B18
CLKBA
CLKENBA
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
GND
A10
A11
VCC
A12
A18
A14
A13
A16
GND
A17
LEBA
A15
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
3225
26
27
28
PIN DESCRIPTION
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
Ax A-to-B Data Inputs or B-to-A 3-State Outputs
Bx B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB A to B Clock Enable Input (Active LOW)
CLKENBA B to A Clock Enable Input (Active LOW)
FUNCTION TABLE(1,4)
Inputs Outputs
CLKENAB OEAB LEAB CLKAB A B
X HXXXZ
XLHXLL
XLHXHH
HLLXXB
0(2)
LLL↑LL
LLL↑HH
L LLLXB
0(2)
LLLHXB
0(3)
NOTES:
1 . A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA
and CLKENBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4 . H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
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IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2 — 5.5 V
Input HIGH Level (I/O pins) 2 — VCC+0.5
VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level –0.5 — 0.8 V
IIH Input HIGH Current (Input pins) VCC = Max. VI = 5.5V — — ±1
Input HIGH Current (I/O pins) VI = VCC ——±1µA
IIL Input LOW Current (Input pins) VI = GND — — ±1
Input LOW Current (I/O pins) VI = GND — — ±1
IOZH High Impedance Output Current VCC = Max. VO = VCC ——±1µA
IOZL (3-State Output pins) VO = GND — — ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IODH Output HIGH Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 –60 –110 mA
IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 90 200 mA
VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA V CC-0.2 — —
VIN = VIH or VIL IOH = –3mA 2.4 3 — V
VCC = 3V IOH = –8mA 2.4(5) 3—
VIN = VIH or VIL
VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2
VIN = VIH or VIL IOL = 16mA — 0.2 0.4
IOL = 24mA — 0.3 0.55 V
VCC = 3V IOL = 24mA — 0.3 0.5
VIN = VIH or VIL
IOS Short Circuit Current(4) VCC = Max., VO = GND(3) –60 –135 –240 mA
VHInput Hysteresis — — 150 — mV
ICCL Quiescent Power Supply Current VCC = Max. — 0.1 10 µA
ICCH VIN = GND or VCC
ICCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC–0.6V at rated current.
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply VCC = Max. — 2 30 µA
Current TTL Inputs HIGH VIN = VCC –0.6V(3)
ICCD Dynamic Power Supply Current(4) VCC = Max. VIN = VCC — 60 100 µA/
Outputs Open VIN = GND M H z
OEAB = VCC, OEBA = GND
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max., Outputs Open VIN = VCC — 0.6 1 mA
fCP = 10MHz (CLKBA) VIN = GND
50% Duty Cycle
OEAB = VCC, OEBA = GND
LEBA = GND VIN = VCC –0.6V — 0.6 1
CLKENBA = GND VIN = GND
fi = 5MHz
One Bit Toggling
VCC = Max., Outputs Open VIN = VCC —35
(5)
fCP = 10MHz (CLKBA) VIN = GND
50% Duty Cycle
OEAB = VCC, OEBA = GND
LEBA = GND VIN = VCC –0.6V — 3 5.3(5)
CLKENBA = GND VIN = GND
fi = 2.5MHz
Eighteen Bits Toggling
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
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IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
Symbol Parameter Condition(1) Min.(2) Max. Unit
fMAX CLKAB or CLKBA frequency(3) CL = 50pF — 150 ns
tPLH Propagation Delay RL = 500Ω1.5 5.5 ns
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay 1.5 6.2 ns
tPHL LEBA to Ax, LEAB to Bx
tPLH Propagation Delay 1.5 6.3 ns
tPHL CLKBA to Ax, CLKAB to Bx
tPZH Output Enable Time 1.5 6.5 ns
tPZL OEBA to Ax, OEAB to Bx
tPHZ Output Disable Time 1.5 5.2 ns
tPLZ OEBA to Ax, OEAB to Bx
tSU Set-up Time HIGH or LOW 3 — n s
Ax to CLKAB, Bx to CLKBA
tHHold Time HIGH or LOW 0 — ns
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time HIGH or LOW Clock LOW 2 . 5 — ns
Ax to LEAB, Bx to LEBA Clock HIGH 2 —
tSU Set-up Time, CLKEN to CLK 2 .5 — ns
tHHold Time HIGH or LOW 1 — ns
Ax to LEAB, Bx to LEBA
tHHold Time, CLKEN to CLK 0 — ns
tWLEAB or LEBA Pulse Width HIGH 2.5 — ns
tWCLKAB or CLKBA Pulse Width HIGH or LOW 3 — ns
tSK(o) Output Skew(4) — 0.5 ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500Ω
500Ω
Open
GND
6v
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU tH
tREM
tSU tH
PRESET
CLEAR
CLO C K ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
SWITCH
GND
VOL
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test Switch
Open Drain
Disable Low 6V
Enable Low
Disable High GND
Enable High
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
4/22/2002 Removed blank speed grade
5/21/2002 Removed TVSOP package
DATA SHEET DOCUMENT HISTORY
XX
Temp. Range XXXX
Device Type X
Package
PA Thin Shrink Small Outline P a ckage
− 40°C to +85°C
74
IDT FCT XXX
Family
163 Double- Densit y 3.3Vol t
601A Non-Inverting 18-Bit Registered Transceiver
