AT25P1024C1-10CI-1.8 - Atmel

Features

•Serial Peripheral Interfa ce (SPI) Compatible

•Supports SPI Modes 0 (0,0) and 3 (1,1)

•2.1 MHz Clock Rate

•128-byte Page Mode Only for Write Operations

•Low-voltage and Standard-voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 3.6V)

•Block Write Protection

–Protect 1/4, 1/2, or Entire Array

•Write Protect (WP) Pin and Write Disable Instructions for

Both Hardware and Software Data Protection

•Self-Timed Write Cycle (5 ms Typical)

•High Reliability

–Endurance: 100,000 Write Cycles

–Data Retention: >40 Years

–ESD Prote ction: >3000 V

•20-lead JEDEC SOIC and 8-pad Leadless Array Package

Description

The AT25 P1024 pr ovides 1, 048,576 bi ts of seri al electric ally era sable prog ramma ble

read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device

is op timi zed for u se in m any ind ustri al and comm erc ial a ppli catio ns w he re lo w pow er

and low vol tage ope ratio n are ess ential. T he AT25P 1024 is availab le in spac e sav ing

20-lead JEDEC SOIC and 8-pad LAP packages.

Rev. 1082D–10/99

SPI Serial

EEPROMs

1M (131,072 x 8)

AT25P1024

Preliminary

Pin Configurations

Pin Name Function

CS Chip Select

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

GND Ground

VCC Power Supply

WP Write Protect

HOLD Suspends Serial Input

NC No Connect

(continued)

20-lead SOIC

GND

VCC

HOLD

SCK

8-pad Leadless Array

Bottom View

VCC

HOLD

SCK

GND

AT25P1024

The AT25P1024 is enabled through the Chip Select pin

(CS) and accessed via a 3-wire interface consisting of

Serial Data Input (SI), Serial Data Output (SO), and Serial

Clock (S CK). All pr ogramming cy cles are co mpletely s elf-

timed, and no separate ERASE cycle is required before

WRITE.

BLOCK WRITE protection is enabled by programming the

status register with top ¼, top ½ or entire array of write pro-

tection. Separate program enable and program disable

instructions are provided for additional data protection.

Hardware data protection is provided via the WP pin to pro-

tect against inadv ertent write attempts to the status regis-

ter. The HOLD pin may be used to suspend any serial

communication without resetting the serial sequence.

Block Diag ram

Absolute Maxim u m Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses be yond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age t o the device. Th is is a s tress ratin g only and

functio nal oper a tion of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device rel iability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximu m Op er ati ng Voltage ...... ...... ..... ....................... .. 6.25V

DC Output Current...................... ...... ..... ...... ................. 5.0 mA

131,072 x 8

AT25P1024

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. VIL and VIH max are reference only and are not tested.

Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Symbol Test Conditions Max Units Conditions

COUT Output Capacit anc e (S O) 8 pF V OUT = 0V

CIN Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV

IN = 0V

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,

TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.8 3.6 V

VCC2 Supply Voltage 2.7 5.5 V

VCC3 Supply Voltage 4.5 5.5 V

ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open Read 2.0 5.0 mA

ICC2 Supply Current VCC = 5.0V at 2 MHz, SO = Open Write 4.0 7.0 mA

ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 3.0 µA

ISB2 Standby Current VCC = 2.7V, CS = VCC 0.2 3.0 µA

ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 7.0 µA

IIL Input Leakage VIN = 0V to VCC -3.0 3.0 µA

IOL Output Lea ka ge VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 µA

VIL(1) Input Low Voltage -0.6 VCC x 0.3 V

VIH(1) Input High Voltage VCC x 0.7 VCC + 0.5 V

VOL1 Output Lo w Voltage 4.5V ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V

VOH1 Outp ut High Voltage IOH = -1.6 mA VCC - 0.8 V

VOL2 Output Lo w Voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V

VOH2 Outp ut High Voltage IOH = -100 µA VCC - 0.2 V

AT25P1024

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

fSCK SCK Clock Frequency 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

2.1

1.0

0.5 MHz

tRI Input Rise Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

2µs

tFI Input Fall Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

2µs

tWH SCK High Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

200

400

800 ns

tWL SCK Low Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

200

400

800 ns

tCS CS High Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

250

500

1000 ns

tCSS CS Setup Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

100

250

1000 ns

tCSH CS Hold Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

150

250

1000 ns

tSU Data In Setup Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

100 ns

tH Data In Hold Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

100 ns

tHD Hold Setup Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

100

400 ns

tCD Hold Hold Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

200

300

400 ns

tVOutput Valid 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

200

400

800 ns

tHO Output Hold Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

0ns

AT25P1024

Note: 1. This parameter is characterized and is not 100% tested.

tLZ Hold to Output Low Z 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

100

200

300 ns

tHZ Hold to Output High Z 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

100

200

300 ns

tDIS Output Disable Time 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

200

250

1000 ns

tWC Write Cycle Tim e 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6

10 ms

Endurance(1) 5.0V, 25°C, Page Mode 4.5 - 5.5

2.7 - 5.5

1.8 - 3.6 100K Write Cycles

AC Characteristics (Continued)

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

AT25P1024

Serial Interface Description

MASTER: The device that generates the serial clock.

SLAVE: B e ca us e t he Se r ia l Cloc k pi n ( SCK ) is al w ays an

input, the AT25P1024 always operates as a slave.

TRANSMITTER/RECEIVER: The AT25P1024 has

separate pins designated for data transmission (SO) and

reception (SI) .

MSB: The Most Significant Bit (MSB) is the first bit

transmitted and received.

SERIAL OP-CO DE: After the device is selected with CS

going low, the fi rst byte w ill be rece ived. Thi s byte contai ns

the op-code that defines the operations to be performed.

INVALID OP-CODE: If an invali d op-cod e is r eceive d, no

data will b e shift ed into t he AT25P 1024, an d the ser ial o ut-

put pin ( SO) wi ll rema in in a high imped ance s tate un til th e

falling edge of CS is detected again. This will reinitialize the

serial communication.

CHIP SELECT: The AT25P1024 is selected when the CS

pin is lo w. Wh en th e dev i ce is not s ele ct ed, data will not b e

accepted via the SI pin, and the serial output pin (SO) will

remain in a high impedance state.

HOLD: The HOLD pin is u sed in conj unctio n wit h the CS

pin to select the AT25P1024. When the device is selected

and a serial sequence is underway, HOLD can be used to

pause the serial communication with the master device

without re settin g the seria l sequ ence. To pa use, the HOLD

pin must be brought low while the SCK pin is low. To

resume serial communication, the HOLD pin is brought

high while the SCK pin is low (SCK may still toggle during

HOLD). Inputs to the SI pin will be ignored while the SO pin

is in the high impedance state.

WRITE PROTECT: The write protect pin (WP) will allow

normal read/write operations wh en held high. When the

WP pin i s brough t low an d WPE N bit is “1”, all wri te opera-

tions to the status register are inhibited. WP going low

while CS is st ill low will interr upt a write to the statu s regis-

ter. If the internal write cycle has already been initiated, WP

going low will have no effect on any write operation to the

status register. The WP pin function is blocked when the

WPEN bi t in the statu s re gister is “0”. This will allow the

user to install th e AT25 P1024 in a s ystem wi th the WP pin

tied to ground and still be able to write to the status regis-

ter. All WP pin functions are enabled when the WPEN bit is

set to “1”.

SPI Serial Interface

MASTER:

MICROCONTROLLER SLAVE:

AT25P1024

DATA OUT (MOSI)

DATA IN (MISO)

SERIAL CLOCK (SPI CK)

SS0

SS1

SS2

SS3

SCK

AT25P1024

Functional Description

The AT25P1024 is designed to interface directly with the

synchronous serial peripheral interface (SPI) of the 6800

type series of microcontrollers.

The AT25P1024 utilizes an 8-bit instruction register. The

list of instructions and their operation codes are contained

in Table 1. All instructions, addresses, and data are trans-

ferred with the MS B first and st art with a high- to-low trans i-

tion.

WRITE ENABLE (WREN): The dev ice w ill power u p in th e

write disable state when VCC is applied. All programming

instr ucti ons m ust t herefo re be p rec eded by a W rite Enab le

instruction.

WRITE DISABLE (WRDI): To protect the device against

inadver ten t writ es, the Wr it e Dis abl e i nst ru ction disabl es all

programmi ng modes . The WRDI ins tructio n is ind ependen t

of the status of the WP pin .

READ STATUS REGISTER (RDSR): The Read Status

The REA DY/BUSY and Write Enable status of the devi ce

can be determined by the RDSR instruction. Similarly, the

Block Writ e Pr otec tion bits i ndicate th e exten t o f prote ctio n

employed. These bits are set by using the WRSR i nstruc-

tion.

WRITE STATUS REGISTER (WRSR): The WRSR instruc-

tion allows the user to select one of four levels of protec-

tion. The AT2 5P1024 is divi ded into four array se gments.

Top quarter (1/4), top half ( 1/2), or all of the memory seg-

ments can be protected. Any of the data within any

select ed segment will the refore be READ only . Th e block

write protection le vels and correspond ing status register

control bits are shown in Table 4.

The three bits, BP0, BP1, and WPEN are nonvolatile cells

that have the s ame properti es and function s as the regular

memory cells (e.g. WREN, tWC, RDSR).

The WRSR instruction also allows the user to enable or

disable the write protect (WP) pin through the use of the

Write Protect Enable (WPEN) bit. Hardware write protec-

tion is enabl e d w h en th e W P pin is low and the WPEN bit is

“1”. Hardware write protection is disabl ed when either the

WP pin is high or the WPEN bit is “0.” When the device is

hardware write protected, writes to the Status Register,

includi ng the Bl ock Protec t bits and the WPEN bi t, and the

block- protec ted sec tions in the memory a rra y are dis able d.

Writes are only allowed to sections of the memory which

are not block-protected.

Table 1. Instruction Set for the AT25P1024

Instruction

Name Instruction

Format Operation

WREN 0000 X110 Set Write Enable Latch

WRDI 0000 X100 Reset Wr ite Enable Latch

RDSR 0000 X101 Read Status Register

WRSR 0000 X001 Wr ite Status Register

READ 0000 X011 Read Data from Memory Array

WRITE 0000 X010 Wr ite Data to Memory Array

Table 2. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Table 3. Read Status Register Bit Definition

Bit Definition

Bit 0 (RDY)Bit 0 = 0 (RDY) indicates the device is READY.

Bit 0 = 1 indicates the write cycle is in progress.

Bit 1 (WEN) Bit 1 = 0 i ndicates the de vice is not WRITE ENABLED .

Bit 1 = 1 indicates the device is WRITE ENABLED.

Bit 2 (BP0) See Table 4.

Bit 3 (BP1) See Table 4.

Bits 4-6 are 0s when device is not in an internal write cycle.

Bit 7 (WPEN) See T able 5.

Bits 0-7 are 1s during an internal write cycle.

Table 4. Block Write Protect Bits

Level

Status Register Bits Array Addresses Protected

BP1 BP0 AT25P1024

0 0 0 None

1(1/4) 0 1 01800 - 01FFFF

2(1/2) 1 0 010000 - 01FFFF

3(All) 1 1 0000 - 01FFFF

AT25P1024

NOTE: When the WPEN bit is hardware write protected, it

cannot be changed back to “0”, as long as the WP pin is

held low.

READ SEQUENCE (READ): Reading the AT25P1024

via the SO (Serial Output) pin requires the following

sequence. After the CS line is pulled low to select a device,

the READ op-code is transmitted via the SI line followed by

the byte ad dress to be read (Refer to Table 6). U pon com-

pletion, any data on the SI lin e will be ignored. The data

(D7-D0) at the specified address is then shifted out onto

the SO line. If only one byte is to be read, the CS line

should be driv en high afte r the da ta come s out. T he REA D

sequence can be continued since the byte address is auto-

matically in cremented a nd data will continue to be shifted

out. When the highest address is reached, the address

counter will roll over to the lowest address allowing the

entire memory to be read in one continuous READ cycle.

WRITE SEQUENCE (WRITE): In order to program the

AT25P10 24, two separate instruc tions must be executed.

First, the device must be write enabled via the Write

Enable ( WREN) Ins truc tio n. T hen a Write (W RITE ) In stru c-

tion may be executed. Also, the address of the memory

location(s) to be programmed must be out side the pro-

tected address field l ocation selected by the Block Write

Protectio n Level. During an internal write c ycle, all com-

mands will be ignored except the RDSR instruction.

A Write Instr uction r equires the foll owing s equence. After

the CS line is pulled lo w to sel ect the dev ice, the W RITE

op-code i s transmitted via the SI line followed by the by te

addres s and the data (D7 -D0) to be program med (Refer to

Table 6 ). Progr am mi ng will s tart after the CS p in is broug ht

high. (The LOW to High transition of the CS pin mu st oc cur

during t he SCK lo w time imm ediately after clocking i n the

D0 (LSB) data bit.

The READY /BUSY statu s of the device can be deter mined

by initiating a READ STATUS REGISTER (RDSR) Instruc-

tion. If Bit 0 = 1, the WRITE cyc le is stil l in progr es s. If Bit 0

= 0, the WRITE cycle has ended. Only the READ STATUS

gramming cycle.

The A T2 5P1024 is c apable of a 128-byte PA GE WRITE

operati on ONLY. Content of the p age in the array will not

be gu aranteed if l ess than 12 8 bytes of data is rec eived

(byte op erati on i s not s upp or ted ). Afte r e ach by te o f dat a is

received, the seve n low order address bits are internally

incremented by one; the high order bits of the address will

remain constant. If more than 128 bytes of data are trans-

mitted, the address c ou nter wi ll roll ov er an d the previ ous ly

written data will be overwritten. The AT25P1024 is auto-

matically returned to the write disable state at the comple-

tion of a WRITE cycle.

NOTE: If the device is not Write enabled (WREN), the

device wil l i gno re the Wr it e in st ru cti on and wil l r etu rn to th e

standby state, when CS is brought high. A new CS fa lling

edge is required to re-initiate the serial communication.

Table 5. WPEN Operation

WPEN WP WEN Protected

Blocks Unprotected

Blocks Status

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

Table 6. Addr ess Key

Address AT25P1024

ANA16 - A0

Don’t Care Bi ts A23 - A17

AT25P1024

Timing Diagrams (for SPI Mode 0 (0, 0))

Synchronous Data Timing

WREN Timing

WRDI Timing

SO V

HI-Z HI-Z

VALID IN

SI V

DIS

SCK V

CSH

CS V

CSS

AT25P1024

RDSR Timing

WRSR Timing

READ Timing

SCK 01234567891011121314

SI INSTRUCTION

SO 76543210

DATA OUT

MSB

HIGH IMPEDANCE

SCK

HIGH IMPEDANCE

INSTRUCTION

3-BYTE ADDRESS

01234

8 9 10 11 28

23 22 21 3

... 21

321

29 30 31 32 33 34 35 36 37 38

AT25P1024

WRITE Timing

HOLD Timing

SCK

3-BYTE ADDRESS 1st BYTE DATA-IN 128th BYTE DATA-IN

INSTRUCTION

HIGH IMPEDANCE

0123456789101128

232221 3 10 654321072

29 30 31 32 33 34

1051

1052

1054

1053

1055

SCK

HOLD

AT25P1024

Ordering Informat ion

tWC (max)

(ms) ICC (max)

(µA) ISB (max)

(µA) fMAX

(kHz) Ordering Code Package Operation Range

5 7000 7.0 2100 AT25P1024C1-10CC

AT25P1024W1-10SC 8C1

20S Commercial

(0°C to 70°C)

7000 7.0 2100 AT25P1024C1-10CI

AT25P1024W1-10SI 8C1

20S Industrial

(-40°C to 85°C)

10 2000 3.0 1400 AT25P1024C1-10CC-2.7

AT25P1024W1-10SC-2.7 8C1

20S Commercial

(0°C to 70°C)

2000 3.0 1000 AT25P1024C1-10CI-2.7

AT25P1024W1-10SI-2.7 8C1

20S Industrial

(-40°C to 85°C)

10 1000 3.0 500 AT25P1024C1-10CC-1.8

AT25P1024W1-10SC-1.8 8C1

20S Commercial

(0°C to 70°C)

1000 3.0 500 AT25P1024C1-10CI-1.8

AT25P1024W1-10SI-1.8 8C1

20S Industrial

(-40°C to 85°C)

Package Type

8C1 8-pad, 0.300" Wide, Leadless Array Package (LAP)

20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

Options

Blank Standard Device (4.5V to 5.5V)

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 3.6V)

AT25P1024

Packaging Information

*Controlling dimension: millimeters

5.10 (0.201)

4.90 (0.193)

8.10 (0.319)

7.90 (0.311) 0.38 (0.015)

0.30 (0.012)

1.14 (0.045)

0.94 (0.037)

4.76 (0.187)

4.66 (0.183)

0.34 (0.013)

0.24 (0.009)

0.95 (0.037)

0.85 (0.033)

0.92 (0.036)

0.82 (0.032)

1.22 (0.048)

1.12 (0.044) 1

TOP VIEW SIDE

VIEW

BOTTOM VIEW

1.32 (0.052)

1.22 (0.048)

0.299 (7.60)

0.291 (7.39)

0.020 (0.508)

0.013 (0.330)

0.420 (10.7)

0.393 (9.98)

PIN 1

.050 (1.27) BSC

0.513 (13.0)

0.497 (12.6)

0.012 (0.305)

0.003 (0.076)

0.105 (2.67)

0.092 (2.34)

8REF

0.035 (0.889)

0.015 (0.381)

0.013 (0.330)

0.009 (0.229)

8C1, 8-pad, 0.300" Wide,

Leadless Array Package (LAP)

Dimensions in Millimeters and (Inches)*

20S, 20-lead, 0.300" Wide,

Plastic Gull Wing Small Outline (JEDEC SOIC)

Dimensions in Inches and (Millimeters)

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Ter ms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the inform ation contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

Mar ks b eari ng ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

Ter ms and product names in this document may be trademarks of others.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441- 0311

FAX (408) 487-2600

Europe

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721 -9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24 -8 Shinka wa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Indu strie lle

13106 Rousset Cedex

France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

1082D–10/99/xM