18
Synchronous SRAM
SAMSUNG SEMICONDUCTOR, INC. AUGUST 2007BR-07-ALL-001
DDR
II
CIO/SIO (18Mbit) SRAM
P art Access Time Cycle Time I/O
Number Organization Vdd (V) tCD (ns) (MHz) Voltage (V) Package Status Comments
K7I161882B 1Mx18 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-2B
K7I161884B 1Mx18 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-4B
K7J161882B 1Mx18 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA SIO-2B
K7J163682B 512Kx36 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA SIO-2B
K7I163682B 512Kx36 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-2B
K7I163684B 512Kx36 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-4B
NOTES: 2B = Burst of 2 4B = Burst of 4 SIO = Separate I/O CIO = Common I/O
DDR
II
CIO/SIO (36Mbit) SRAM
P art Access Time Cycle Time I/O Production
Number Organization Vdd (V) tCD (ns) (MHz) Voltage (V) Package Status Comments
K7I321882C 2Mx18 1.8 0.45 333,300,250 1.5,1.8 165FBGA CIO-2B
K7I321884C 2Mx18 1.8 0.45 333,300,250 1.5,1.8 165FBGA CIO-4B
K7J321882C 2Mx18 1.8 0.45 333,300,250 1.5,1.8 165FBGA SIO-2B
K7I323682C 1Mx36 1.8 0.45 333,300,250 1.5,1.8 165FBGA CIO-2B
K7I323684C 1Mx36 1.8 0.45 333,300,250 1.5,1.8 165FBGA CIO-4B
K7J323682C 1Mx36 1.8 0.45 333,300,250 1.5,1.8 165FBGA SIO-2B
NOTES: 2B = Burst of 2 4B = Burst of 4 SIO = Separate I/O CIO = Common I/O
C-die will support high-speed bins only 330, 300, 250MHz, which can cover slow-speed bins (200MHz, 167MHz) using stable DLL circuit.
DDR
II
+ CIO (18Mbit) SRAM
P art Access Time Cycle Time I/O
Number Organization Vdd (V) tCD (ns) (MHz) Voltage (V) Package Status Comments
K7K1618T2C 1Mx18 1.8 0.45 450, 400, 333 1.5 165FBGA DDRII + CIO-2B
K7K1636T2C 512Kx36 1.8 0.45 450, 400, 333 1.5 165FBGA DDRII + CIO-2B
NOTE: Offer 2-clock latency now; we can also support 2.5-clock latency with 500MHz speed based on demand.
DDR
II
+ CIO (36Mbit) SRAM
P art Access Time Cycle Time I/O Production
Number Organization Vdd (V) tCD (ns) (MHz) Voltage (V) Package Status Comments
K7K3218T2C 2Mx18 1.8 0.45 450, 400, 333 1.5 165FBGA DDRII + CIO-2B
K7K3236T2C 1Mx36 1.8 0.45 450, 400, 333 1.5 165FBGA DDRII + CIO-2B
NOTE: Offer 2-clock latency now; we can also support 2.5-clock latency with 450MHz speed based on demand.
DDR
II
CIO/SIO (72Mbit) SRAM
P art Access Time Cycle Time I/O
Number Organization Vdd (V) tCD (ns) (MHz) Voltage (V) Package Status Comments
K7I641882M 4Mx18 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-2B
K7I641884M 4Mx18 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-4B
K7J641882M 4Mx18 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA SIO-2B
K7I643682M 2Mx36 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-2B
K7I643684M 2Mx36 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA CIO-4B
K7J643682M 2Mx36 1.8 0.45,0.45,0.45,0.50 300,250,200,167 1.5,1.8 165FBGA SIO-2B
NOTES: 2B = Burst of 2 4B = Burst of 4 SIO = Separate I/O CIO = Common I/O
MEMORY AND ST ORA GE