PREVIEW
PREVIEW
PREVIEW
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SLLS633A − O C TOBER 2004 − REVISED FEBRUARY 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DDual-Supply Operation . . . ±5 V to ±18 V
DLow Noise Voltage . . . 4.5 nV/√Hz
DLow Input Offset Voltage . . . 0.15 mV
DLow Total Harmonic Distortion . . . 0.002%
DHigh Slew Rate ...7 V/µs
DHigh-Gain Bandwidth Product . . . 16 MHz
DHigh Open-Loop AC Gain . . . 800 @ 20 kHz
DLarge Output-Voltage Swing . . . 14.1 V to
−14.6 V
DExcellent Gain and Phase Margins
description/ordering information
The MC33078 and MC33079 are bipolar
dual/quad operational amplifiers with
high-performance specifications for use in quality
audio and data-signal applications. These
devices operate over a wide range of single- and
dual-supply voltages and offer low noise,
high-gain bandwidth, and high slew rate.
Additional features include low total harmonic
distortion, excellent phase and gain margins,
large output voltage swing with no deadband
crossover distortion, and symmetrical sink/source
performance.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (P) Tube of 50 MC33078P MC33078P
SOIC (D)
Tube of 75 MC33078D
M33078
Dual SOIC (D) Reel of 2500 MC33078DR M33078
−40°C to 85°C
Dual
VSSOP/MSOP (DGK)
Reel of 2500 MC33078DGKR
−40
°
C to 85
°
C
VSSOP/MSOP (DGK)
Reel of 250 MC33078DGKT
PDIP (P) Tube of 50 MC33079P
Quad
SOIC (D)
Tube of 75 MC33079D
Quad
SOIC (D)
Reel of 2500 MC33079DR
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
1
2
3
4
8
7
6
5
OUT1
IN1−
IN1+
VCC−
VCC+
OUT2
IN2−
IN2+
MC33078 ...D (SOIC), DGK (MSOP), OR P (PDIP) PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VCC+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
VCC−
3IN+
3IN−
3OUT
MC33079 ...D (SOIC) OR P (PDIP) PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
VCC+
OUT2
IN2−
IN2+
MC33078 ...D (SOIC), DGK (MSOP), OR P (PDIP) PACKAGE
(TOP VIEW)
MC33079 ...D (SOIC) OR P (PDIP) PACKAGE
(TOP VIEW)
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SLLS633A − O C TOBER 2004 − REVISED FEBRUARY 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
symbol (each amplifier)
IN+
IN− OUT
+
−
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, VCC− (see Note 1) −18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, (VCC− to VCC+) 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, either input (see Notes 1 and 2) VCC− or VCC+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (see Note 3) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of output short circuit (see Note 4) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 5 and 6): D package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGK package 172°C/W. . . . . . . . . . . . . . . . . . . . . . . .
P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
2. The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
3. Excessive input current will flow if a dif ferential input voltage in excess of approximately 0.6 V is applied between the inputs, unless
some limiting resistance is used.
4. The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.
5. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN MAX UNIT
VCC−
Supply voltage
−5 −18
V
VCC+ Supply voltage 5 18 V
TAOperating free-air temperature range −40 85 °C
 
      
SLLS633A − O C TOBER 2004 − REVISED FEBRUARY 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC− = −15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO
VO = 0, RS = 10 Ω VCM = 0
TA = 25°C 0.15 2
mV
VIO Input offset voltage VO = 0, RS = 10 Ω, VCM = 0 TA = −40°C to 85°C 3 mV
αVIO Input offset voltage
temperature coefficient VO = 0, RS = 10 Ω, VCM = 0 TA = −40°C to 85°C 2 µV/°C
IIB
VO = 0,
VCM = 0
TA = 25°C 300 750
nA
IIB Input bias current VO = 0, VCM = 0 TA = −40°C to 85°C800 nA
IIO
VO = 0,
VCM = 0
TA = 25°C 25 150
nA
IIO Input offset current VO = 0, VCM = 0 TA = −40°C to 85°C175 nA
VICR Common-mode input voltage
range nVIO = 5 mV, VO = 0 ±13 ±14 V
AVD
RL ≥ 2 kΩ, VO = ±10 V
TA = 25°C 90 110
dB
AVD
voltage amplification RL ≥ 2 kΩ, VO = ±10 V TA = −40°C to 85°C 85 dB
RL = 600 Ω
VOM+ 10.7
RL = 600 ΩVOM− −11.9
VOM
VID = ±1 V
RL = 2k Ω
VOM+ 13.2 13.8
V
VOM
swing VID = ±1 V RL = 2k ΩVOM− −13.2 −13.7 V
RL = 10k Ω,
VOM+ 13.5 14.1
RL = 10k Ω,VOM− −14 −14.6
CMMR Common-mode rejection ratio VIN = ±13 V 80 100 dB
kSVR†Supply-voltage rejection ratio VCC+ = 5 V to 15 V, VCC− = −5 V to −15 V 80 105 dB
IOS
IVIDI = 1 V,
(Source current) 15 29
mA
IOS Output short-circuit current
IVIDI = 1 V,
Output to GND (Sink current) −20 −37 mA
ICC
VO = 0
TA = 25°C 2.05 2.5
mA
ICC Supply current (per channel) VO = 0 TA = −40°C to 85°C 2.75 mA
†Measured with VCC± differentially varied at the same time
operating characteristics, VCC− = −15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR Slew rate at unity gain AVD = 1, VIN = −10 V to 10 V, RL = 2 kΩ, CL = 100 pF 5 7 V/µs
GBW Gain bandwidth product f = 100 kHz 10 16 MHz
B1Unity gain frequency open loop 9 MHz
RL = 2 kΩ
CL = 0 pF −11
dB
Gain margin RL = 2 kΩCL = 100 pF −6 dB
φm
RL = 2 kΩ
CL = 0 pF 55
deg
φmPhase margin RL = 2 kΩCL = 100 pF 40 deg
Amp-to-amp isolation f = 20 Hz to 20 kHz −120 dB
Power bandwidth VO = 27 V(PP), RL = 2 kΩ,THD 1% 120 kHz
THD Total harmonic distortion VO = 3 Vrms, AVD = 1, RL = 2 kΩ, f = 20 Hz to 20 kHz 0.002 %
zoOpen-loop output impedance VO = 0, f = 9 MHz 37 Ω
rid Differential input resistance VCM = 0 175 kΩ
Cid Differential input capacitance VCM = 0 12 pF
VnEquivalent input noise voltage f = 1 kHz, RS = 100 Ω4.5 nV/√Hz
InEquivalent input noise current f = 1 kHz 0.5 pA/√Hz
 
      
SLLS633A − O C TOBER 2004 − REVISED FEBRUARY 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D.U.T.
Voltage Gain = 50,000
Scope
x 1
RIN = 1.0 MΩ
+
−
100 kΩ
10 Ω
0.1 µF
100 kΩ
0.1 µF
24.3 kΩ
4.7 µF
2.0 kΩ
2.2 µF
22 µF
110 kΩ
4.3 kΩ
1/2
MC33078
NOTE: All capacitors are non-polarized.
Figure 1. Voltage Noise Test Circuit (0.1 Hz to 10 Hzp−p)
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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