HARRIS SEMICOND SECTOR G? HARRIS CMOS NOR Gates High-Voltage Types (20-Volt Rating) Quad 2 Input ~ CD4001B Dual 4 Input CD40028 Triple 3 Input CD4025B @ CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct impiementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4001B, CO4002B, and CD40258 types are supplied in 14-lead hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix). STATIC ELECTRICAL CHARACTERISTICS Features: = Propagation delay time = 60 ns (typ.) at Ce. =50 pF, Vpp = 10 V Buffered inputs and outputs Standardized symmetrical output characteristics 100% tested for maximum quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25C Noise margin (over full package temperature range}: 1VatVpp=5V 2 Vat Vpp=10V 2.5 Vat Vpp = 15 V Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B" Series CMOS Devices CONDITIONS LIMITS AT INDICATED TEMPERATURES (C) CHARACTER- UNITS ISTIC vo. |vin [Vop 78 tv) iv) | (vj) | -55 | 40 +85 +125 | Min. | Typ. | Max. Quiescent Device | - 05 | 5 |o25}025| 75 | 75] - | 001 | o25 Current, - [oo] 10/05 | os | 15 1s | - | oot | o5 '0D Max _ fost ps f+ | a | 3 ]- [oo] i] = 0,20} 20] 5 5 | 150 | 150 | - oo2} 5 Output Low o4 [os | 5 | 064/06: | 042 | 036/051] 1 (Sink) Current 0.5 |010] 10] 16 | 1.5 it 09 | 1.3 2.6 - Fou Min. 15 [015| 15| 421 4 | 28 |] 24/34] 68 | - Output High 46 [o5| 5 |-06al-0.61/-042]-o36/-o51| -1 | | mA (Sourcel 25 |o5|5 | -2 {-18|-13 |-1.15|-16] -32] - Current, 95 |010| 10|-16/-15 |-11 |-091-13| -26] - 1H Min 135 [015] 15 |-42] -4 | -28 |-24|-34] -68 | Output Voltage - 05 5 0.05 - 0 0.05 Lew Level. ~ [oto[ 10 0.05 = 0 | 0.05 VOL Max fois] 15 0.05 = 0 foo) | Output Voitage. - 05 5 495 4.95 5 - High Level, - 0.10] 10 9.95 9.95 | 10 - VOH Min 10.15] 15 14,95 14.95 | 15 = Input Low 0.5,4.5 - 5 1.5 =- - 15 Vottage, 1.9 _ 10 3 3 vit Max fy5195] [18 [= Ty] Input High 0.5 - 5 35 3.5 - - Voltage. t = 10 7 7 ~ VIH Min 15 | 45 nN uf "hee quent 0,18] 18 | 04 10.1 | "1 | a} fsto-5] ton] pA W4E D 4302271 0037322 3 MMHAS 7 Tet B-Z | CD4001B, CD4002B, CD4025B Types a ss le fo [2 Le fe |e Vss4 UskiF 92C8-24762. cD4001B FUNCTIONAL DIAGRAM da L . Yoo J2At84C40) 2 say x o iM o4 6 o r neS] ee gg44 KeEsFeGon 18 ne e2cs-24756 cD4002B FUNCTIONAL DIAGRAM z Yss s Js hase cp40288 92cs~ 24760 FUNCTIONAL DIAGRAM COMMERCIAL CMOS HIGH VOLTAGE ICsHARRIS SEMICOND SECTOR YUE D MM 4302273 0037323 5 MBHAS CD40018, CD4002B, CD4025B Types ; ; RECOMMENDED OPERATING CONDITIONS AMB:ZENT TEMPERATURE {Ta} For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: i LIMITS $ CHARACTERISTIC UNITS at MIN, MAX. g Supply-Voltage Range (For Ta = Full Package 3 3 18 Vv 5 Temperature Range) MAXIMUM RATINGS, Absolute-Maximum Values: DCG SUPPLY-VOLTAGE RANGE, (Vpp) INPUT VOLTAGE (Vy) Voltages raferancad to Vgg Terminal) ...... 00... ccc eee e ence cence erect neces en teeeeuen -0.5V to +20V stca-zesce (INPUT VOLTAGE RANGE, ALLINPUTS ... . 70.5V to Von +0.5V - DC INPUT CURRENT, ANY ONE INPUT +10MA Fig.1 Typical voltage transfer characteristics. POWER DISSIPATION PER PACKAGE (Pp): For Ty = -85C 10 $1009 oo cece ence nec ee ee eee eeeeeeeeeeeneseaesensersgees scomw For Ta = $1009C to +1250C. o.oo eee ec ee see eeeeeeenes Darate Linearity at 12mW/2G to 200mW DEVICE DISSIPATION PEA OUTPUT TRANSISTOR FOR Ta = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .... s0omw OPERATING-TEMPERATURE RANGE (Ta) STORAGE TEMPERATURE RANGE Tstg) LEAD TEMPERATURE (DURING SOLDERING): At distance 1/16 + 1/32 inch (1.59 + 0,79mm) from case for 10s Max ...... 0... cece eee ee ee eaee +265C POWER DISSIPATION PER GATE (Pg t= pw DYNAMIC ELECTRICAL CHARACTERISTICS AtT, = 28C, Input t,, ty= 20ns, C, = SO pF, Ry = 200k2 bo IRPUT FREQUENCY: (fy}~ Ae ercd-2a903 TEST CONDITIONS wuts a2 Tyoicat dissipation vt CHARACTERISTIC UNITS Fig.2 - Typical power dissipation vs. frequency. v OD | tvp. MAX. VOLTS Propagation Delay Time, 5 125 250 IPHL. tPLH 10 60 120 ns 15 45 90 5 100 200 Transition Time, 10 50 100 ns TTHL. 'TLH 15 40 80 Input Capacitance, Cyy Any Input 5 7.5 pF ORAIN=TQ-SQURCE VOLTAGE [ps}V seestarany Fig.3 -- Typical output low (sink) current characteristics. DRAIN-TO-OURCE VOLTAGE [YosI- s2e3-2enem Fig, 4 - Minimum output low (sink) current characteristics. 3-4HARRIS SEMICOND SECTOR - 4Y4E D MM 4302271 0037324 7 MMHAS CD4001B, CD4002B, CD4025B Types T- J ) / | 18,6, 13} 3 110,440 219,512) ORAIN~T0-SQURCE VOLTAGE lYpg}V HH 4 LOGIC OLAGRAK 3 aa | a wt . p8 pret (10,411) ] Yoo re t a ik on asa] al | A A byes ALL INPUTS ARE PROTECTED 8Y CMOS PROTECTION NETWORK 1OF 4GATES g2ts- 2037988 (NUMBERS IM FARENTHESES 9268-2080) ARE TERMINAL NUMBERS . , , FOR oTnER cates) Fig. 8- Typical autput high {source} current characteristics. Fig.5 Schematic and logic diagrams for CD40018. Yo DAAIN-TO-SOURCE VOLTAGE (osI 14 2t12) 3a) Ie fe pep i ; al Ay 1n3) LOGIC O1AGRAM 3 i= yi | (88 eu ne Fs w at > [ i 39 fe wl . sz ytan Ayo | & 3 o_ a> wt = fle! 2] ss re { g 4 | | ve R= oo i; s2ea-cesnet 6 ; woe "| --_ Fig. 9 - Minimum output high (source) ies | current characteristics. 91 My | 7 a i rs 4 *ALL INFUTS ARE PROTECTED BY J CMOS NETWORK wyatt aera b vote NUMBERS FOR SECOND GATE} ss Fig. @~ Schematic and logic diagrams for CD4002B. TRANSITION TIME (THE et TLHIRS 30,0 p Dp i | nd qd . 412,12) hoy 3 20 100 LOAD CAPACITANCE (cL) 4 4 318,13), SaPA (euler S2eS~ 24322 Ae Logic OLAGRAM Fig. 10- Typical transition time vs. load k , sf (sto) capacitance, ae | bh Hy a wl 24 J] TEMPERATURE (1g) 25C a ||! * Hy | Nv, oT ae 0 (2,12) wt ay ] | j= . st HY | ee (a3) fa a Is VS * ALL INPUTS ARE PROTECTED QY CMOS PROTECTION 10F 3GATES (NUMBERS IN NETWORK PARENTHESES ARE TERMINAL 7 NUMBERS FOR OTHER GATES) VSS. s2cs-2av0s LOAD icu oF - 2, 9208+ 248e Fig. 7 - Schematic and logic diagrams for CD4025B. Fig. 11 - Typical propagation delay time vs, load capacitance. 3-5HARRIS SEMICOND SECTOR CD4001B, CD4002B, CD4025B Types Ty 2-2] INPUTS: us | NOTE MEASURE INPUTS SEQUENTIALLY, TO GOTH Von AND Vgs- CONNECT ALL UNUSED INPUTS TO EITHER Yoo OF ss Yoo vss tttt Yss y2c3-27402 Fig. 13 Input leakage current test circuit. WHE D MM 4302271 00373e5 4 BAHAS t IaPUTS: ouTPUTS 4 Loe Vin | Lon woe a Le Yee ~ be = a bom = NOTE: Yss TEST ANY COMBINATION OF INPUTS 92C$-27441R1 Fig. 14 Input-voltage test circuit. TERMINAL ASSIGNMENTS (TOP VIEW) sas Yoo a4 vara CFO "GH co eye eo JtA+BECHO Yoo t INPUTS ates. ar amsaitit Gp) Vs Fig.18 Quiescent-device current test circuit, 92C5- 244468) 92cs-2aas7ar 9268-24468RI NCaNO CONNECTION NC =NO COKNECTION NG +HO CONNECTION. CD40018 CD4002B CD4025B8 Chip Dimensions and Pad Layouts 0 10 20 30 40 50 60 68 52-60 30 (1.320-1.524) 20 a lo-| o- By be 4-10 (0.102-0.254) 65-73 i 1651 -1-8547 92CS-35054 co40018 60-} io = 20 40 80 68 50-' 52-60 0.320-1.524) 30 20 7, oO. cp4002B . 4-10 (0.102-0.254} 68-73 1651-1884, s2cs-2aso8 = | *76.102-0 254) 66-74 r (1.676-1.879) t cp4025B 92CS-35060 3-6