1
DS31407
3-Input, 4-Output, Single DPLL Timing IC
with Sub-ps Output Jitter
General D es cription
The DS31407 is a flexible, high-performance timing IC
for diverse frequency conversion and frequency
synthesis applications. On each of i ts three input clocks
and four output clocks, the device can accept or
generate nearly any frequency between 2kHz and
750MHz.
The input clocks are divided down, fractionally scaled as
needed, and continuously monitored for activity and
frequency accuracy. The best input clock is selected,
manually or automatically, as the reference clock for the
rest of the device. A flexible, high-performance digital
PLL locks to the selected reference and provides
programmable bandwidth, very high resolution holdover
capability, and truly hitless switching between input
clocks. The digital PLL is followed by a clock synthesis
subsystem that has two fully programmable digital
frequency synthesis blocks, a high-speed low-jitter
APLL, and four output clocks, each with its own 32-bit
divider and phase adjustment. The APLL provides
fractional scaling and output jitter less than 1ps RMS.
For telecom systems, the DS31407 has all required
features and functions to serve as a central timing
function or as a line card timing IC. With a suitable
oscillator the DS31407 meets the requirements of
Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813,
and G.8262.
Applications
Frequency Conversion Applications in a Wide Variety of
Equipment Types
Telecom Line Cards or Timing Cards with Any Mix of
SONET/SDH, Synchronous Ethernet and/or OTN
Ports in WAN Equipment Including MSPPs, Ethernet
Switches, Routers, DSLAMs, and Base Stations
Order ing Information
PART TEMP RANGE PIN-PACKAGE
DS31407GN+
-40
°
C to +85
°
C
256 CSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
Features
♦ Three Input Clock s
♦ Differential or CMOS/TTL Format
♦ Any Frequency from 2kHz to 750MHz
♦ Fractional Scaling for 64B/66B and FEC
Scaling (e.g., 64/66, 237/ 2 55, 238/2 55) or Any
Other Downscaling Requirement
♦ Continuous Input Clock Quality Monitoring
♦ Automatic or Manual Clock Selection
♦ Three 2/4/8kHz Frame Sync Inputs
♦ High-Performance DPLL
♦ Hitless Re ference Switching on Loss of Input
♦ Automatic or Manual Phase Build-Out
♦ Holdover on Loss of All Inputs
♦ Programmable Bandwidth, 0.5 mHz to 400Hz
♦ Two Digital Frequency Synthesizers
♦ Produce Any 2kHz Multiple Up to 77.76MHz
♦ Per-DFS Clock Pha se Adjust
♦ High-Perf orma nce Ou tpu t APLL
♦ Output Freque nci es to 750MHz
♦ High Resolution Fractional Scaling for FEC
and 64B/66B (e.g., 255/237, 255/238, 66/64)
or Any Other Scaling Requirement
♦ Less than 1ps RMS Output Jitter
♦ Four Out put Clocks in Two Groups
♦ Nearly Any Frequency from < 1Hz to 750MHz
♦ Each Group Slaves to a DFS Clock, an APLL
Clock, or Any Input Clock (Divided and Scaled)
♦ Each Has a Differential Output (1 CML, 1 LVDS/
LVPECL) and Separate CMOS/TTL Output
♦ 32-Bit Frequency Divider Per Output
♦ Two Sync Pulse Outputs: 8kHz and 2kHz
♦ General Features
♦ Suitable Line Card IC or Timing Card I C for
Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
♦ Accepts and Produces Nearly Any Frequency Up
to 750MHz Including 1Hz, 2k Hz, 8kH z, NxDS1,
NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M,
156.25M, and Nx19.44M Up to 622.08M
♦ Internal Compensation for Local Oscillator
Frequency Error
♦ SPI™ Processor Interface
♦ 1.8V Operation with 3.3V I/O (5V Tolerant)
Short Form Data Sheet
April 2012
DS31407
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Short Form Data Sheet
Applicat ion Exampl e
system timing
from master and slave
timing cards
IC1
DS31407
IC2
Each input can be any frequency
from 2kHz to 725MHz
Output clocks can be nearly any frequency from <1Hz to 725MHz.
Each output clock can be sourced from a DFS block, an APLL or
from an input clock (divided and scaled).
Each output clock has its own 32-bit divider.
Output Cocks
outputs from APLL: <1ps rms jitter,
outputs from DFS: ~40ps rms jitter
clock monitoring and selection,
hitless switching, holdover, frequency
conversion, fractional scaling,
jitter attenuation
OC1
OC4
OC1POS/NEG
OC4POS/NEG
Block Diagr am
DPLL
Filtering, Holdover,
Hitless Switching, PBO,
Frequency Conversion,
Manual Phase Adjust
Master Clock
APLL
FSYNC
MFSYNC
Microprocessor Port
(SPI Serial)
and HW Control and Status Pins
Local Oscillator
TCXO or OCXO
RST
CS
CPHA
SCLK
SDI
SDO
INTREQ
SRCSW
MCLKOSC
JTAG
SYNC1
TEST
GPIO[4:1]
SRFAIL
LOCK
SYNC3
IC1 POS/NEG
IC2 POS/NEG
SYNC2
OC1POS/NEG
OC4
CPOL
JTRST
JTMS
JTCLK
JTDI
JTDO
Divider 4
OC1
MFSYNC
DS31407
lowest jitter path
PLL Bypass
OC4POS/NEG
IC3 POS/NEG
OSCFREQ[2:0]
Divider 1
Divider Muxes Dif Mux
Input Clock
Block
Frequency Scaler,
Activity Monitor,
Freq. Monitor,
Optional Inversion
(per input clock)
Clock
Selector
3
status
DFS 1 APLL1
DFS 4
DFS Muxes
DS31407
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Short Form Data Sheet
Detail ed Features
Input Clock Feat ures
• Three input clocks, differential or CMOS/TTL signal format
• Input clocks can be any frequency from 2kHz up to 750MHz
• Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3
• Per-input fractional scaling (i.e. multiplying by N÷D where N is a 16-bit integer and D is a 32-bit int eger and
N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255)
• Special mode allows locking to 1Hz input clocks
• All inputs constantly monitored by programmable activity monitors and frequency monitors
• Fast activity monitor can disqualify the selected reference after a few missing clock cycles
• Frequency measurement and frequency monitor thresholds with 0.2ppm resolution
• Three optional 2/4/8kHz frame-s ync inputs
DPLL Features
• Very high-resol uti on DPL L ar chitec ture
• Sophisticated state machine automatically transitions between free-run, locked, and holdover states
• Revertive or nonrevertive reference selection algorithm
• Programmable bandwidth from 0.5mHz to 400Hz
• Separately configurable acquisition bandwidth and locked bandwidth
• Programmable damping factor: 1.2, 2.5, 5, 10, or 20
• Multiple phase detectors: phase/frequency and multicycle
• Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
• Multicycl e phase detec t ion and loc k ing (up to ±8191UI) improves jitter tolerance and lock time
• Phase build-out in response to reference switching for true hitless switching
• Less than 1 ns output clock phase transient during phase build-out
• Output phase adjustment up to ±2 00ns in 6ps steps wi th respec t to selec ted in put r ef erenc e
• High-resolution frequency and phase measurement
• Holdover frequency averaging over 1-seco nd, 5.8-minute, and 93.2-minute int erva l s
• Fast detection of input clock failure and transition to holdover mode
• Low-jitter frame sy nc (8kHz) and multiframe sync (2kHz) aligned with output clocks
Digital Fr equency Sy nt hes izer Featur es
• Two independently programmable DFS engines
• Each DFS can synthesize any 2 kHz multiple up to 77.76MHz
• Per-DFS phase adjust (1/256UI steps)
• Approximately 40ps RMS output jitter
Output APLL Features
• Simultaneously produce four different output frequencies from the same reference clock
• Standard telecom output freque ncies incl ude 622 .08 MH z, 155.52M H z, and 19.44MHz for SONET/SDH
and 156.25MHz, 125MHz, and 25M Hz for Synchronous Ethernet
• Very high-resolution fractional scaling (i.e., nonint e ger mult iplic a t io n )
• Less than 1ps RMS output jitter
DS31407
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Short Form Data Sheet
Output Clock Features
• Four output clock signals in two groups
• Output clock group OC1 has a very high-sp eed dif f erentia l output (current-mode logic, ≤ 750MHz) and a
separate CMOS/TTL output (≤ 125MHz)
• Output clock group OC4 has a high-speed differential output (LVDS/LVPECL, ≤ 312.5MHz) and a separate
CMOS/TTL ouptut (≤ 125MHz)
• Each output can be any frequency from < 1Hz to max frequency stated above
• Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, microprocessor clock
frequencies, and much more
• Internal clock muxing allows each output group to slave to its associated DFS block, an APLL output, or
any input clock (after being divided and scaled)
• Outputs sourced directly from the APLL have less than 1ps RMS output jitter
• Outputs sourced directly from DFS blocks have approximately 40ps RMS output jitter
• Optional 32-bit f requenc y divider per out put
• 8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can
be disciplined by a 2kHz or 8kHz frame sync input
• Per-output delay adjustment
• Per-output enable/disable
• All outputs disabled during reset
General Feat ures
• SPI serial microprocessor interface
• Four general-purpose I/O pins
• Register set can be write protected
• Operates from a 12.8MH z, 25.6 MH z, 10.24MHz, 20.48MHz, 10MHz, 20MHz, 19.44MHz, or 38.8 8MH z
local oscillator
• On-chip watchdog circuit for the local oscillator
• Internal compensation for local oscillator frequency error
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo
CA 92656 USA
Within the USA: +1 (949) 380
-6100
Sales: +1 (949) 380
-6136
Fax
: +1 (949) 215-4996
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ystems. Microsemi is headquartered in Aliso Viejo, Calif.
.
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