LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input Check for Samples: LMK00105 FEATURES TARGET APPLICATIONS * * * 1 2 * * * * * * * 5 LVCMOS Outputs, DC to 200 MHz Universal Input - LVPECL - LVDS - HCSL - SSTL - LVCMOS / LVTTL Crystal Oscillator Interface - Crystal Input Frequency: 10 to 40 MHz Output Skew: 6 ps Additive Phase Jitter - 30 fs at 156.25 MHz (12 kHz to 20 MHz) Low Propagation Delay Operates with 3.3 or 2.5 V Core Supply Voltage Adjustable Output Power Supply - 1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank 24 pin WQFN package (4.0 x 4.0 x 0.8 mm) * * * * * * * LO Reference Distribution for RRU Applications SONET, Ethernet, Fibre Channel Line Cards Optical Transport Networks GPON OLT/ONU Server and Storage Area Networking Medical Imaging Portable Test and Measurement High-end A/V DESCRIPTION The LMK00105 is a high performance, low noise LVCMOS fanout buffer which can distribute 5 ultralow jitter clocks from a differential, single ended, or crystal input. The LMK00105 supports synchronous output enable for glitch free operation. The ultra lowskew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00105 can be easily configured through pin programming. FUNCTIONAL BLOCK DIAGRAM Bank A CLKout0 CLKout1 Crystal 5 LVCMOS Outputs Universal Input (Differential/ Single Ended) Bank B CLKout2 CLKout3 CLKout4 SEL OE SYNC 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012-2013, Texas Instruments Incorporated LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com Connection Diagram 24 23 22 21 20 19 OE Vdd SEL CLKin CLKin* GND 24-Pin WQFN Package 1 2 3 4 5 6 DAP 18 17 16 15 14 13 Vddo CLKout4 GND CLKout3 Vddo CLKout2 GND Vdd OSCin OSCout GND GND 7 8 9 10 11 12 GND Vddo CLKout0 GND CLKout1 Vddo PIN DESCRIPTIONS (1) 2 Pin # Pin Name Type DAP DAP - 2, 6 Vddo Power Power Supply for Bank A (CLKout0 and CLKout 1) CLKout pins. LVCMOS Output 3 CLKout0 Output 1,4,7,11, 12, 16,19 GND GND Description The DAP should be grounded Ground 5 CLKout1 Output LVCMOS Output 8,23 Vdd Power Supply for operating core and input buffer 9 OSCin Input Input for Crystal 10 OSCout Output Output for Crystal 13 CLKout2 Output LVCMOS Output 14,18 Vddo Power Power Supply for Bank B (CLKout2 to CLKout 4) CLKout pins 15 CLKout3 Output LVCMOS Output 17 CLKout4 Output LVCMOS Output 20 CLKin* Input Complementary input pin 21 CLKin Input Input Pin 22 SEL Input Input Clock Selection. This pin has an internal pull-down resistor. (1) 24 OE Input Output Enable. This pin has an internal pull-down resistor. (1) CMOS control input with internal pull-down resistor. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (1) (2) Parameter Symbol Ratings Units Core Supply Voltage Vdd -0.3 to 3.6 V Output Supply Voltage Vddo -0.3 to 3.6 V Input Voltage VIN -0.3 to Vdd + 0.3 V Storage Temperature Range TSTG -65 to 150 C Lead Temperature (solder 4 s) TL +260 C Junction Temperature TJ +125 C "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV. Recommended Operating Conditions Parameter Symbol Min Typ Max Units Ambient Temperature TA -40 25 85 C Vdd 2.375 3.3 3.45 V Vddo 1.425 3.3 Vdd V Core Supply Voltage Output Supply Voltage (1) (1) Vddo should be less than or equal to Vdd (Vddo Vdd) Package Thermal Resistance 24-Lead WQFN Package Thermal resistance from junction to ambient on 4-layer Jedec board Thermal resistance from junction to case (1) (2) (1) (2) Symbols Ratings Units JA 50.6 C/W JC (DAP) 20.1 C/W Specification assumes 4 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias play a key role in improving the thermal performance of the WQFN. For best thermal dissipation it is recommended that the maximum number of vias be used on the board layout. Case is defined as the DAP (die attach pad). Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 3 LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com Electrical Characteristics (2.375 V Vdd 3.45 V, 1.425 Vddo Vdd, -40 C TA 85 C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, TA = 25 C, at the Recommended Operation Conditions at the time of product characterization and are not ensured). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units Total Device Characteristics Vdd Core Supply Voltage 2.375 2.5 or 3.3 3.45 V Vddo Output Supply Voltage 1.425 1.5,1.8, 2.5, or 3.3 Vdd V No CLKin 16 25 Vddo = 3.3 V, Ftest = 100 MHz 24 Vddo = 2.5 V, Ftest = 100 MHz 20 Vddo = 2.5 V, OE = High, Ftest = 100 MHz 5 Vddo= 3.3 V, OE = High, Ftest = 100 MHz 7 OE = Low 0.1 OE = High @ 100 MHz 48 OE = Low 16 IVdd IVddo[n] IVdd + IVddo Core Current Current for Each Output Total Device Current with Loads on all outputs mA mA mA Power Supply Ripple Rejection (PSRR) PSRR 100 kHz, 100 mVpp Ripple Injected on Vdd, Vddo = 2.5 V Ripple Induced Phase Spur Level Outputs Skew tPD tPD, PP fCLKout tRise VCLKoutLow Propagation Delay CLKin to CLKout Part-to-part Skew (2) (3) Output Frequency Rise/Fall Time 6 25 ps CL = 5 pF, RL = 50 Vdd = 3.3 V; Vddo = 3.3 V 0.85 1.4 2.2 ns CL = 5 pF, RL = 50 Vdd = 2.5 V; Vddo = 1.5 V 1.1 1.8 2.8 ns CL = 5 pF, RL = 50 Vdd = 3.3 V; Vddo = 3.3 V 0.35 ns CL = 5 pF, RL = 50 Vdd = 2.5 V; Vddo = 1.5 V 0.6 ns 200 MHz (4) DC Vdd = 3.3 V, Vddo = 1.8 V, CL = 10 pF 250 Vdd = 2.5 V, Vddo = 2.5 V, CL = 10 pF 275 Vdd = 3.3 V, Vddo = 3.3 V, CL = 10 pF 315 Output Low Voltage Output High Voltage RCLKout Output Resistance (1) (2) (3) (4) (2) RMS Additive Jitter dBc (1) Measured between outputs, referenced to CLKout0 (2) VCLKoutHigh tj 4 Output Skew -44 ps 0.1 V Vddo0.1 fCLKout = 156.25 MHz, CMOS input slew rate 2 V/ns CL = 5 pF, BW = 12 kHz to 20 MHz 50 ohm 30 fs AC Parameters for CMOS are dependent upon output capacitive loading Parameter is specified by design, not tested in production. Part-to-part skew is calculated as the difference between the fastest and slowest tPD across multiple devices. Specified by characterization. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 Electrical Characteristics (continued) (2.375 V Vdd 3.45 V, 1.425 Vddo Vdd, -40 C TA 85 C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, TA = 25 C, at the Recommended Operation Conditions at the time of product characterization and are not ensured). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 unless otherwise stated. Symbol Parameter Test Conditions VLow Input Low Voltage Min Typ Max Units Digital Inputs (OE, SEL0, SEL1) VHigh Input High Voltage IIH High Level Input Current IIL Low Level Input Current Vdd = 2.5 V 1.3 Vdd = 3.3 V 1.6 50 IIH High Level Input Current VCLKin = Vdd IIL Low Level Input Current VCLKin = 0 V VIH Input High Voltage VIL Input Low Voltage VI_SE VID Differential Input Voltage Swing 5 20 -20 uA uA GND (8) uA (5) (6) Vdd Differential Input Common Mode Input Voltage (7) Single-Ended Input Voltage Swing V -5 CLKin/CLKin* Input Clock Specifications, VCM 0.4 Vdd = 2.5 V V VID = 150 mV 0.5 Vdd1.2 VID = 350 mV 0.5 Vdd1.1 VID = 800 mV 0.5 Vdd0.9 CLKinX driven single-ended (AC or DC coupled), CLKinX* AC coupled to GND or externally biased within VCM range 0.3 2 Vpp CLKin driven differentially 0.15 1.5 V Single-Ended Input, OSCout floating DC 200 MHz Fundamental Mode Crystal ESR < 200 ( fXtal 30 MHz ) ESR < 120 ( fXtal > 30 MHz ) (9) (10) 10 40 MHz V OSCin/OSCout Pins fOSCin (5) (6) (7) (8) (9) (10) Input Frequency (9) fXTAL Crystal Frequency Input Range COSCin Shunt Capacitance VIH Input High Voltage 1 Single-Ended Input, OSCout floating pF 2.5 V See Differential Voltage Measurement Terminology for definition of VOD and VID. Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information. When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled. Parameter is specified by design, not tested in production. Specified by characterization. The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However, lower ESR values for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 5 LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified: Vdd = Vddo = 3.3 V, TA = 20 C, CL = 5 pF, CLKin driven differentially, input slew rate 2 V/ns. NOISE FLOOR (dBc/Hz) RMS JITTER (fs) RMS Jitter vs. CLKin Slew Rate @ 100 MHz 500 -40 C Fclk-100 MHz 25 C 450 Int. BW=1-20 MHz 85 C CLKin Source 400 350 300 250 200 150 100 Noise Floor vs. CLKin Slew Rate @ 100 MHz -140 -40 C Fclk=100 MHz 25 C Foffset=20 MHz 85 C -145 CLKin Source -150 -155 -160 -165 50 0 -170 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT SLEW RATE (V/ns) Figure 1. 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT SLEW RATE (V/ns) Figure 2. LVCMOS Phase Noise @ 100 MHz LVCMOS Output Swing vs. Frequency 3.5 Vddo=1.5 V Vddo=1.8 V Vddo=2.5 V Vddo=3.3 V OUTPUT SWING (V) 3.0 LVCMOS Output CLKin Source 2.5 Rterm=50 2.0 1.5 1.0 0.5 0.0 0 (1) Test conditions: LVCMOS Input, slew rate 2 V/ns, CL = 5 pF in parallel with 50 , BW = 1 MHz to 20 MHz Figure 3. 200 400 600 800 FREQUENCY (MHz) 1000 Figure 4. Iddo per Output vs Frequency CURRENT (mA) 15 Vddo = 1.5 V Vddo = 1.8 V Vddo = 2.5 V Vddo = 3.3 V Cload = 10 pF 10 5 0 0 6 50 100 150 200 FREQUENCY (MHz) Figure 5. Submit Documentation Feedback 250 Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 MEASUREMENT DEFINITIONS Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first section Figure 6 illustrates the two different definitions side-by-side for inputs and Figure 7 illustrates the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP). VID Definition VSS Definition for Input Non-Inverting Clock VIH VCM VSS VID VIL Inverting Clock VSS = 2* VID VID = | VIH VIL | GND Figure 6. Two Different Definitions for Differential Input Signals VOD Definition VSS Definition for Output Non-Inverting Clock VOH VOS VOL VSS VOD Inverting Clock VOD = | VOH - VOL | VSS = 2* VOD GND Figure 7. Two Different Definitions for Differential Output Signals Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 7 LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION The LMK00105 is a 5 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz. It features a 2:1 input multiplexer with a crystal oscillator input, single supply or dual supply (lower power) operation, and pin-programmable device configuration. The device is offered in a 24-pin WQFN package. Vdd and Vddo Power Supplies Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply (3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. Bank A (CLKout0 and CLKout1) and Bank B (CLKout2 to CLKout4) may also be operated at different Vddo voltages, provided neither Vddo voltage exceeds Vdd. NOTE Care should be taken to ensure the Vddo voltage does not exceed the Vdd voltage to prevent turning-on the internal ESD protection circuitry. DO NOT DISCONNECT OR GROUND ANY OF THE Vddo PINS as the Vddo pins are internally connected within an output bank. CLOCK INPUT The LMK00105 has one differential input, CLKin/CLKin* and OSCin, that can be driven in different manners that are described in the following sections. SELECTION OF CLOCK INPUT Clock input selection is controlled using the SEL pin as shown in Table 1. Refer to Driving the Clock Inputs for clock input requirements. When CLKin is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator will start-up and its clock will be distributed to all outputs. Refer to Crystal Interface for more information. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal. Table 1. Input Selection SEL Input 0 CLKin, CLKin* 1 OSCin (Crystal Mode) CLKin/CLKin* Pins The LMK00105 has a differential input (CKLin/CLKin*) which can be driven single-ended or differentially. It can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and single ended signals that meet the input requirements in Electrical Characteristics and (1). Refer to Driving the Clock Inputs for more details on driving the LMK00105 inputs. In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them, Table 2 following will be the state of the outputs. (1) 8 When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 Table 2. CLKin Input vs. Output States CLKin CLKin* Output State Open Open Logic Low Logic Low Logic Low Logic Low Logic High Logic Low Logic High Logic Low Logic High Logic Low OSCin/OSCout Pins The LMK00105 has a crystal oscillator which will be powered up when OSCin is selected. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal. Refer to Crystal Interface for more information. If Crystal mode is selected and the pins do not have an AC signal applied to them, Table 3 will be the state of the outputs. If Crystal mode is selected an open state is not allowed on OSCin, as the outputs may oscillate due to the crystal oscillator circuitry. Table 3. OSCin Input vs. Output States OSCin Output State Open Not Allowed Logic Low Logic High Logic High Logic Low CLOCK OUTPUTS The LMK00105 has 5 LVCMOS outputs. Output Enable Pin When the output enable pin is held High, the outputs are enabled. When it is held Low, the outputs are held in a Low state as shown in Table 4. Table 4. Output Enable Pin States OE Outputs Low Disabled (Hi-Z) High Enabled The OE pin is synchronized to the input clock to ensure that there are no runt pulses. When OE is changed from Low to High, the outputs will initially have an impedance of about 400 to ground until the second falling edge of the input clock and starting with the second falling edge of the input clock, the outputs will buffer the input. If the OE pin is taken from Low to High when there is no input clock present, the outputs will either go high or low and stay a that state; they will not oscillate. When the OE pin is taken from High to Low the outputs will be Low after the second falling edge of the clock input and then will go to a Disabled (Hi-Z) state starting after the next rising edge. Using Less than Five Outputs Although the LMK00105 has 5 outputs, not all applications will require all of these. In this case, the unused outputs should be left floating with a minimum copper length to minimize capacitance. In this way, this output will consume minimal output current because it has no load. NOTE For best soldering practices, the minimum trace length should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 9 LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com APPLICATION INFORMATION Driving the Clock Inputs The LMK00105 has a differential input (CLKin/CLKin*) that can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, and other differential and single ended signals that meet the input requirements specified in Electrical Characteristics. The device can accept a wide range of signals due to its wide input common mode voltage range (VCM) and input voltage swing (VID)/dynamic range. AC coupling may also be employed to shift the input signal to within the VCM range. To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have a high slew rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this reason, a differential input signal is recommended over single-ended because it typically provides higher slew rate and common-mode noise rejection. While it is recommended to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive it with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in the Electrical Characteristics. For large single-ended input signals, such as 3.3 V or 2.5 V LVCMOS, a 50 load resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line termination to minimize reflections. The CLKin input has an internal bias voltage of about 1.4 V, so the input can be AC coupled as shown in Figure 8. The output impedance of the LVCMOS driver plus Rs should be close to 50 to match the characteristic impedance of the transmission line and load termination. RS 0.1 PF 0.1 PF 50: Trace 50: CMOS Driver LMK Input 0.1 PF Figure 8. Preferred Configuration: Single-Ended LVCMOS Input, AC Coupling A single-ended clock may also be DC coupled to CLKin as shown in Figure 9. A 50- load resistor should be placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of the driver (VO,PP / 2) drives CLKin, CLKin* should be externally biased to the midpoint voltage of the attenuated input swing ((VO,PP / 2) x 0.5). The external bias voltage should be within the specified input common voltage (VCM) range. This can be achieved using external biasing resistors in the k range (RB1 and RB2) or another lownoise voltage reference. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest. CMOS Driver VO,PP Rs VO,PP/2 VCC 50: Trace VBB ~ (VO,PP/2) x 0.5 50: LMK Input RB1 VCC RB2 0.1 PF Figure 9. Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing 10 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 10. The input clock should be AC coupled to the OSCin pin, which has an internally generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, it is recommended to use either differential input (CLKin) since it offers higher operating frequency, better common mode, improved power supply noise rejection, and greater performance over supply voltage and temperature variations. 0.1 PF 50: Trace OSCin OSCout LMK00105 RS 0.1 PF 50: CMOS Driver Figure 10. Driving OSCin with a Single-Ended Crystal Interface C1 OSCin XTAL RLIM OSCout LMK00105 The LMK00105 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 11. C2 Figure 11. Crystal Interface The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY ~ 1 to 3 pF) can affect the discrete load capacitor values, C1 and C2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows: CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY (1) Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1only: CL = C12 / (2 * C1) + CIN + CSTRAY (2) Finally, solve for C1: C1 = (CL - CIN - CSTRAY) * 2 (3) Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 11 LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation. The power dissipated in the crystal, PXTAL, can be computed by: PXTAL = IRMS2 * RESR * (1 + C0 / CL)2 (4) Where: * IRMS is the RMS current through the crystal. * RESR is the maximum equivalent series resistance specified for the crystal. * CL is the load capacitance specified for the crystal. * C0 is the minimum shunt capacitance specified for the crystal. IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active. As shown in Figure 11, an external resistor, RLIM, can be used to limit the crystal drive level if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 k. 12 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 Power Supply Ripple Rejection In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00105, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc). For the LMK00105, power supply ripple rejection (PSRR), was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vddo supply. The PSRR test setup is shown in Figure 12. Ripple Source Vcco Clock Source Power Supplies Bias-Tee IN+ IC IN- Vcc OUT Limiting Amp DUT Board OUT Phase Noise Analyzer Scope Measure 100 mVPP ripple on Vcco at IC Measure single sideband phase spur power in dBc Figure 12. PSRR Test Setup A signal generator was used to inject a sinusoidal signal onto the Vddo supply of the DUT board, and the peak-topeak ripple amplitude was measured at the Vddo pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following power supply ripple conditions: * Ripple amplitude: 100 mVpp on Vddo = 2.5 V * Ripple frequency: 100 kHz Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [(2 * 10(PSRR/20)) / ( * fclk)] * 1012 (5) Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 13 LMK00105 SNAS579F - MARCH 2012 - REVISED MAY 2013 www.ti.com Power Supply Bypassing The Vdd and Vddo power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very close to each supply pin. Placing the bypass capacitors on the same layer as the LMK00105 improves input sensitivity and performance. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance. Thermal Management For reliability and performance reasons the die temperature should be limited to a maximum of 125C. That is, as an estimate, TA (ambient temperature) plus device power consumption times JA should not exceed 125C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 13. More information on soldering WQFN packages and gerber footprints can be obtained: www.ti.com/packaging. To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 13 should connect these top and bottom copper layers and to the ground layer. These vias act as "heat pipes" to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. 2.6 mm, min 0.2 mm, typ 1.0 mm, typ Figure 13. Recommended Land and Via Pattern 14 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 LMK00105 www.ti.com SNAS579F - MARCH 2012 - REVISED MAY 2013 REVISION HISTORY Changes from Revision E (February 2013) to Revision F Page * Added device name to title of document. ............................................................................................................................. 1 * Changed all LLP and QFN packages to WQFN throughout document. ............................................................................... 1 * Deleted optional from CLKin* pin description. And changed complimentary to complementary. ........................................ 2 * Added max limit to Output Skew parameter and added tablenote to parameter in Electrical Characteristics Table. .......... 4 * Changed typical value for both conditions of Propagation Delay in the Electrical Characteristics Table. ........................... 4 * Added Min/Max limits to both conditions of Propagation Delay parameter in Electrical Characteristics Table. .................. 4 * Changed unit value for the first condition of Part-to-part Skew from ps to ns in the Electrical Characteristics Table. ........ 4 * Changed both Max values of each Part-to-part Skew condition in Electrical Characteristics Table. ................................... 4 * Changed the Typ value of each Rise/Fall Time condition in the Electrical Characteristics Table. ...................................... 4 * Deleted VIL table note. .......................................................................................................................................................... 5 * Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table. ........................ 5 * Added CLKin* column to CLKin Input vs. Output States table. Also added fourth row starting with Logic Low under CLKin column. ....................................................................................................................................................................... 9 * Changed table title from CLKin input vs. Output States to OSCin Input vs. Output States ................................................. 9 * Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Removed extra references to other figures. Revised to better correspond with information in Electrical Characteristics Table. ............... 10 * Deleted Figure 10 (Near End termination) and Figure 11 (Far End termination) from Driving the Clock Inputs section ... 10 * Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section. ............ 10 * Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic. ............ 10 * Deleted sentence in reference to two deleted images. ...................................................................................................... 11 * Changed link from National packaging site to TI packaging site. ....................................................................................... 14 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMK00105 15 PACKAGE OPTION ADDENDUM www.ti.com 3-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMK00105SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00105 LMK00105SQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00105 LMK00105SQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00105 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMK00105SQ/NOPB WQFN RTW 24 LMK00105SQE/NOPB WQFN RTW LMK00105SQX/NOPB WQFN RTW SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK00105SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0 LMK00105SQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0 LMK00105SQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA RTW0024A SQA24A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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