SEL
OE
5 LVCMOS
Outputs
Crystal
Universal Input
(Differential/
Single Ended)
Bank A
Bank B
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
SYNC
LMK00105
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LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
Check for Samples: LMK00105
1FEATURES TARGET APPLICATIONS
2• 5 LVCMOS Outputs, DC to 200 MHz • LO Reference Distribution for RRU
Applications
• Universal Input • SONET, Ethernet, Fibre Channel Line Cards
– LVPECL • Optical Transport Networks
– LVDS • GPON OLT/ONU
– HCSL • Server and Storage Area Networking
– SSTL • Medical Imaging
– LVCMOS / LVTTL • Portable Test and Measurement
• Crystal Oscillator Interface • High-end A/V
– Crystal Input Frequency: 10 to 40 MHz
• Output Skew: 6 ps DESCRIPTION
• Additive Phase Jitter The LMK00105 is a high performance, low noise
– 30 fs at 156.25 MHz (12 kHz to 20 MHz) LVCMOS fanout buffer which can distribute 5 ultra-
low jitter clocks from a differential, single ended, or
• Low Propagation Delay crystal input. The LMK00105 supports synchronous
• Operates with 3.3 or 2.5 V Core Supply Voltage output enable for glitch free operation. The ultra low-
• Adjustable Output Power Supply skew, low-jitter, and high PSRR make this buffer
– 1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank ideally suited for various networking, telecom, server
and storage area networking, RRU LO reference
• 24 pin WQFN package (4.0 x 4.0 x 0.8 mm) distribution, medical and test equipment applications.
The core voltage can be set to 2.5 or 3.3 V, while the
output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V.
The LMK00105 can be easily configured through pin
programming.
FUNCTIONAL BLOCK DIAGRAM
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
CLKout0
CLKout1 CLKout2
CLKout3
CLKout4
Vddo
GND
Vddo
Vddo
GND
Vddo
GND
Vdd
CLKin
GND
OE
SEL
CLKin*
GND
OSCin
GND
GND
Vdd
OSCout
DAP
LMK00105
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Connection Diagram
24-Pin WQFN Package
PIN DESCRIPTIONS
Pin # Pin Name Type Description
DAP DAP - The DAP should be grounded
2, 6 Vddo Power Power Supply for Bank A (CLKout0 and CLKout 1) CLKout pins.
3 CLKout0 Output LVCMOS Output
1,4,7,11, GND GND Ground
12, 16,19
5 CLKout1 Output LVCMOS Output
8,23 Vdd Power Supply for operating core and input buffer
9 OSCin Input Input for Crystal
10 OSCout Output Output for Crystal
13 CLKout2 Output LVCMOS Output
14,18 Vddo Power Power Supply for Bank B (CLKout2 to CLKout 4) CLKout pins
15 CLKout3 Output LVCMOS Output
17 CLKout4 Output LVCMOS Output
20 CLKin* Input Complementary input pin
21 CLKin Input Input Pin
22 SEL Input Input Clock Selection. This pin has an internal pull-down resistor.(1)
24 OE Input Output Enable. This pin has an internal pull-down resistor.(1)
(1) CMOS control input with internal pull-down resistor.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Parameter Symbol Ratings Units
Core Supply Voltage Vdd -0.3 to 3.6 V
Output Supply Voltage Vddo -0.3 to 3.6 V
Input Voltage VIN -0.3 to Vdd + 0.3 V
Storage Temperature Range TSTG -65 to 150 °C
Lead Temperature (solder 4 s) TL+260 °C
Junction Temperature TJ+125 °C
(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD
protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Ambient Temperature TA-40 25 85 °C
Core Supply Voltage Vdd 2.375 3.3 3.45 V
Output Supply Voltage (1) Vddo 1.425 3.3 Vdd V
(1) Vddo should be less than or equal to Vdd (Vddo ≤Vdd)
Package Thermal Resistance
24-Lead WQFN Package Symbols Ratings Units
Thermal resistance from junction to ambient on 4-layer Jedec board (1) θJA 50.6 ° C/W
Thermal resistance from junction to case (2) θJC (DAP) 20.1 ° C/W
(1) Specification assumes 4 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias
play a key role in improving the thermal performance of the WQFN. For best thermal dissipation it is recommended that the maximum
number of vias be used on the board layout.
(2) Case is defined as the DAP (die attach pad).
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Electrical Characteristics
(2.375 V ≤Vdd ≤3.45 V, 1.425 ≤Vddo ≤Vdd, -40 °C ≤TA≤85 °C, Differential inputs. Typical values represent most likely
parametric norms at Vdd = Vddo = 3.3 V, TA= 25 °C, at the Recommended Operation Conditions at the time of product
characterization and are not ensured). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 Ωunless
otherwise stated.
Symbol Parameter Test Conditions Min Typ Max Units
Total Device Characteristics
2.5 or
Vdd Core Supply Voltage 2.375 3.45 V
3.3
1.5,1.8,
Vddo Output Supply Voltage 1.425 2.5, or Vdd V
3.3
No CLKin 16 25
IVdd Core Current Vddo = 3.3 V, Ftest = 100 MHz 24 mA
Vddo = 2.5 V, Ftest = 100 MHz 20
Vddo = 2.5 V, 5
OE = High, Ftest = 100 MHz
IVddo[n] Current for Each Output Vddo= 3.3 V, mA
7
OE = High, Ftest = 100 MHz
OE = Low 0.1
OE = High @ 100 MHz 48
Total Device Current with Loads on all
IVdd + IVddo mA
outputs OE = Low 16
Power Supply Ripple Rejection (PSRR)
100 kHz, 100 mVpp
Ripple Induced
PSRR Ripple Injected on -44 dBc
Phase Spur Level Vdd, Vddo = 2.5 V
Outputs (1)
Measured between outputs,
Skew Output Skew (2) 6 25 ps
referenced to CLKout0
CL= 5 pF, RL= 50 Ω0.85 1.4 2.2 ns
Vdd = 3.3 V; Vddo = 3.3 V
tPD Propagation Delay CLKin to CLKout (2) CL= 5 pF, RL= 50 Ω1.1 1.8 2.8 ns
Vdd = 2.5 V; Vddo = 1.5 V
CL= 5 pF, RL= 50 Ω0.35 ns
Vdd = 3.3 V; Vddo = 3.3 V
tPD, PP Part-to-part Skew (2) (3) CL= 5 pF, RL= 50 Ω0.6 ns
Vdd = 2.5 V; Vddo = 1.5 V
fCLKout Output Frequency (4) DC 200 MHz
Vdd = 3.3 V, Vddo = 1.8 V, CL= 10 pF 250
tRise Rise/Fall Time Vdd = 2.5 V, Vddo = 2.5 V, CL= 10 pF 275 ps
Vdd = 3.3 V, Vddo = 3.3 V, CL= 10 pF 315
VCLKoutLow Output Low Voltage 0.1 V
Vddo-
VCLKoutHigh Output High Voltage 0.1
RCLKout Output Resistance 50 ohm
fCLKout = 156.25 MHz,
tjRMS Additive Jitter CMOS input slew rate ≥2 V/ns 30 fs
CL= 5 pF, BW = 12 kHz to 20 MHz
(1) AC Parameters for CMOS are dependent upon output capacitive loading
(2) Parameter is specified by design, not tested in production.
(3) Part-to-part skew is calculated as the difference between the fastest and slowest tPD across multiple devices.
(4) Specified by characterization.
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Electrical Characteristics (continued)
(2.375 V ≤Vdd ≤3.45 V, 1.425 ≤Vddo ≤Vdd, -40 °C ≤TA≤85 °C, Differential inputs. Typical values represent most likely
parametric norms at Vdd = Vddo = 3.3 V, TA= 25 °C, at the Recommended Operation Conditions at the time of product
characterization and are not ensured). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 Ωunless
otherwise stated.
Symbol Parameter Test Conditions Min Typ Max Units
Digital Inputs (OE, SEL0, SEL1)
VLow Input Low Voltage Vdd = 2.5 V 0.4
Vdd = 2.5 V 1.3 V
VHigh Input High Voltage Vdd = 3.3 V 1.6
IIH High Level Input Current 50 uA
IIL Low Level Input Current -5 5
CLKin/CLKin* Input Clock Specifications, (5) (6)
IIH High Level Input Current VCLKin = Vdd 20 uA
IIL Low Level Input Current VCLKin = 0 V -20 uA
VIH Input High Voltage Vdd V
VIL Input Low Voltage GND Vdd-
VID = 150 mV 0.5 1.2
Differential Input Common Vdd-
VCM VID = 350 mV 0.5 V
Mode Input Voltage (7) 1.1
Vdd-
VID = 800 mV 0.5 0.9
CLKinX driven single-ended (AC or DC
VI_SE Single-Ended Input Voltage Swing (8) coupled), CLKinX* AC coupled to GND or 0.3 2 Vpp
externally biased within VCM range
VID Differential Input Voltage Swing CLKin driven differentially 0.15 1.5 V
OSCin/OSCout Pins
fOSCin Input Frequency (9) Single-Ended Input, OSCout floating DC 200 MHz
Fundamental Mode Crystal
fXTAL Crystal Frequency Input Range ESR < 200 Ω( fXtal ≤30 MHz ) 10 40 MHz
ESR < 120 Ω( fXtal > 30 MHz ) (9)(10)
COSCin Shunt Capacitance 1 pF
VIH Input High Voltage Single-Ended Input, OSCout floating 2.5 V
(5) See Differential Voltage Measurement Terminology for definition of VOD and VID.
(6) Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.
(7) When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled.
(8) Parameter is specified by design, not tested in production.
(9) Specified by characterization.
(10) The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However,
lower ESR values for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal.
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0 50 100 150 200 250
0
5
10
15
CURRENT (mA)
FREQUENCY (MHz)
Cload = 10 pF
Vddo = 1.5 V
Vddo = 1.8 V
Vddo = 2.5 V
Vddo = 3.3 V
0 200 400 600 800 1000
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT SWING (V)
FREQUENCY (MHz)
Rterm=50
Vddo=1.5 V
Vddo=1.8 V
Vddo=2.5 V
Vddo=3.3 V
LVCMOS Output
CLKin Source
0.5 1.0 1.5 2.0 2.5 3.0
0
50
100
150
200
250
300
350
400
450
500
RMS JITTER (fs)
DIFFERENTIAL INPUT SLEW RATE (V/ns)
Fclk-100 MHz
Int. BW=1-20 MHz
-40 C
25 C
85 C
CLKin Source
0.5 1.0 1.5 2.0 2.5 3.0
-170
-165
-160
-155
-150
-145
-140
NOISE FLOOR (dBc/Hz)
DIFFERENTIAL INPUT SLEW RATE (V/ns)
Fclk=100 MHz
Foffset=20 MHz
-40 C
25 C
85 C
CLKin Source
LMK00105
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Typical Performance Characteristics
Unless otherwise specified: Vdd = Vddo = 3.3 V, TA= 20 °C, CL= 5 pF, CLKin driven differentially, input slew rate ≥2 V/ns.
RMS Jitter vs. CLKin Slew Rate @ 100 MHz Noise Floor vs. CLKin Slew Rate @ 100 MHz
Figure 1. Figure 2.
LVCMOS Phase Noise @ 100 MHz LVCMOS Output Swing vs. Frequency
(1) Test conditions: LVCMOS Input, slew rate ≥2 V/ns, CL= 5 pF in
parallel with 50 Ω, BW = 1 MHz to 20 MHz
Figure 3. Figure 4.
Iddo per Output vs Frequency
Figure 5.
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VOH
VOL
GND
VOD = | VOH - VOL | VSS = 2·VOD
VOD Definition VSS Definition for Output
Non-Inverting Clock
Inverting Clock
VOD VSS
VOS
LMK00105
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MEASUREMENT DEFINITIONS
Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions causing confusion
when reading datasheets or communicating with other engineers. This section will address the measurement and
description of a differential signal so that the reader will be able to understand and discern between the two
different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the
inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if
an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal
with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated
parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its
differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can
be calculated as twice the value of VOD as described in the first section
Figure 6 illustrates the two different definitions side-by-side for inputs and Figure 7 illustrates the two different
definitions side-by-side for outputs. The VID and VOD definitions show VAand VBDC levels that the non-inverting
and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the
inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now
increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the
differential signal can be measured.
VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP).
Figure 6. Two Different Definitions for Differential Input Signals
Figure 7. Two Different Definitions for Differential Output Signals
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FUNCTIONAL DESCRIPTION
The LMK00105 is a 5 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz.
It features a 2:1 input multiplexer with a crystal oscillator input, single supply or dual supply (lower power)
operation, and pin-programmable device configuration. The device is offered in a 24-pin WQFN package.
Vdd and Vddo Power Supplies
Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply
(3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply
operation, dual supply operation enables lower power consumption and output-level compatibility.
Bank A (CLKout0 and CLKout1) and Bank B (CLKout2 to CLKout4) may also be operated at different Vddo
voltages, provided neither Vddo voltage exceeds Vdd.
NOTE
Care should be taken to ensure the Vddo voltage does not exceed the Vdd voltage to
prevent turning-on the internal ESD protection circuitry.
DO NOT DISCONNECT OR GROUND ANY OF THE Vddo PINS as the Vddo pins are
internally connected within an output bank.
CLOCK INPUT
The LMK00105 has one differential input, CLKin/CLKin* and OSCin, that can be driven in different manners that
are described in the following sections.
SELECTION OF CLOCK INPUT
Clock input selection is controlled using the SEL pin as shown in Table 1. Refer to Driving the Clock Inputs for
clock input requirements. When CLKin is selected, the crystal circuit is powered down. When OSCin is selected,
the crystal oscillator will start-up and its clock will be distributed to all outputs. Refer to Crystal Interface for more
information. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal.
Table 1. Input Selection
SEL Input
0 CLKin, CLKin*
1 OSCin (Crystal Mode)
CLKin/CLKin* Pins
The LMK00105 has a differential input (CKLin/CLKin*) which can be driven single-ended or differentially. It can
accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and single ended signals that meet the
input requirements in Electrical Characteristics and (1). Refer to Driving the Clock Inputs for more details on
driving the LMK00105 inputs.
In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them,
Table 2 following will be the state of the outputs.
(1) When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled.
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Table 2. CLKin Input vs. Output States
CLKin CLKin* Output State
Open Open Logic Low
Logic Low Logic Low Logic Low
Logic High Logic Low Logic High
Logic Low Logic High Logic Low
OSCin/OSCout Pins
The LMK00105 has a crystal oscillator which will be powered up when OSCin is selected. Alternatively, OSCin
may be driven by a single ended clock, up to 200 MHz, instead of a crystal. Refer to Crystal Interface for more
information. If Crystal mode is selected and the pins do not have an AC signal applied to them, Table 3 will be
the state of the outputs. If Crystal mode is selected an open state is not allowed on OSCin, as the outputs may
oscillate due to the crystal oscillator circuitry.
Table 3. OSCin Input vs. Output States
OSCin Output State
Open Not Allowed
Logic Low Logic High
Logic High Logic Low
CLOCK OUTPUTS
The LMK00105 has 5 LVCMOS outputs.
Output Enable Pin
When the output enable pin is held High, the outputs are enabled. When it is held Low, the outputs are held in a
Low state as shown in Table 4.
Table 4. Output Enable Pin States
OE Outputs
Low Disabled (Hi-Z)
High Enabled
The OE pin is synchronized to the input clock to ensure that there are no runt pulses. When OE is changed from
Low to High, the outputs will initially have an impedance of about 400 Ωto ground until the second falling edge of
the input clock and starting with the second falling edge of the input clock, the outputs will buffer the input. If the
OE pin is taken from Low to High when there is no input clock present, the outputs will either go high or low and
stay a that state; they will not oscillate. When the OE pin is taken from High to Low the outputs will be Low after
the second falling edge of the clock input and then will go to a Disabled (Hi-Z) state starting after the next rising
edge.
Using Less than Five Outputs
Although the LMK00105 has 5 outputs, not all applications will require all of these. In this case, the unused
outputs should be left floating with a minimum copper length to minimize capacitance. In this way, this output will
consume minimal output current because it has no load.
NOTE
For best soldering practices, the minimum trace length should extend to include the pin
solder mask. This way during reflow, the solder has the same copper area as connected
pins. This allows for good, uniform fillet solder joints helping to keep the IC level during
reflow.
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0.1 PF
50:Trace
CMOS
Driver
Rs
VCC RB1
RB2
VCC
LMK
Input
50:
VO,PP VO,PP/2
VBB ~ (VO,PP/2) x 0.5
0.1 PF
0.1 PF
50:Trace
50:
LMK
Input
0.1 PF
RS
CMOS
Driver
LMK00105
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APPLICATION INFORMATION
Driving the Clock Inputs
The LMK00105 has a differential input (CLKin/CLKin*) that can accept AC or DC coupled 3.3V/2.5V LVPECL,
LVDS, and other differential and single ended signals that meet the input requirements specified in Electrical
Characteristics. The device can accept a wide range of signals due to its wide input common mode voltage
range (VCM) and input voltage swing (VID)/dynamic range. AC coupling may also be employed to shift the input
signal to within the VCM range.
To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have a high slew
rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.
For this reason, a differential input signal is recommended over single-ended because it typically provides higher
slew rate and common-mode noise rejection.
While it is recommended to drive the CLKin/CLKin* pair with a differential signal input, it is possible to drive it
with a single-ended clock provided it conforms to the Single-Ended Input specifications for CLKin pins listed in
the Electrical Characteristics. For large single-ended input signals, such as 3.3 V or 2.5 V LVCMOS, a 50 Ωload
resistor should be placed near the input for signal attenuation to prevent input overdrive as well as for line
termination to minimize reflections. The CLKin input has an internal bias voltage of about 1.4 V, so the input can
be AC coupled as shown in Figure 8. The output impedance of the LVCMOS driver plus Rs should be close to
50 Ωto match the characteristic impedance of the transmission line and load termination.
Figure 8. Preferred Configuration: Single-Ended LVCMOS Input, AC Coupling
A single-ended clock may also be DC coupled to CLKin as shown in Figure 9. A 50-Ωload resistor should be
placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of
the driver (VO,PP / 2) drives CLKin, CLKin* should be externally biased to the midpoint voltage of the attenuated
input swing ((VO,PP / 2) × 0.5). The external bias voltage should be within the specified input common voltage
(VCM) range. This can be achieved using external biasing resistors in the kΩrange (RB1 and RB2) or another low-
noise voltage reference. This will ensure the input swing crosses the threshold voltage at a point where the input
slew rate is the highest.
Figure 9. Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing
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OSCin
OSCout
C1
C2
XTAL
RLIM
0.1 PF
50:Trace
50:
CMOS
Driver
0.1 PF
RS
LMK00105
OSCin
OSCout
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If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external
clock as shown in Figure 10. The input clock should be AC coupled to the OSCin pin, which has an internally
generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative
input to multiplex an external clock, it is recommended to use either differential input (CLKin) since it offers
higher operating frequency, better common mode, improved power supply noise rejection, and greater
performance over supply voltage and temperature variations.
Figure 10. Driving OSCin with a Single-Ended
Crystal Interface
The LMK00105 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The
crystal interface is shown in Figure 11.
Figure 11. Crystal Interface
The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CLis specified
for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY
~ 1 to 3 pF) can affect the discrete load capacitor values, C1and C2. For the parallel resonant circuit, the discrete
capacitor values can be calculated as follows:
CL= (C1* C2) / (C1+ C2) + CIN + CSTRAY (1)
Typically, C1= C2for optimum symmetry, so Equation 1 can be rewritten in terms of C1only:
CL= C12/ (2 * C1) + CIN + CSTRAY (2)
Finally, solve for C1:
C1= (CL- CIN - CSTRAY) * 2 (3)
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Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the
crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power
dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the
crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient
level necessary to start-up and maintain steady-state operation.
The power dissipated in the crystal, PXTAL, can be computed by:
PXTAL = IRMS2* RESR * (1 + C0/ CL)2(4)
Where:
• IRMS is the RMS current through the crystal.
• RESR is the maximum equivalent series resistance specified for the crystal.
• CLis the load capacitance specified for the crystal.
• C0is the minimum shunt capacitance specified for the crystal.
IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal
connected to OSCout with the oscillation circuit active.
As shown in Figure 11, an external resistor, RLIM, can be used to limit the crystal drive level if necessary. If the
power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted,
then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the
crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a
suggested value for RLIM is 1.5 kΩ.
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Ripple
Source Bias-Tee Power
Supplies
DUT Board
Limiting
Amp
Scope Phase Noise
Analyzer
IC
Measure 100 mVPP
ripple on Vcco at IC
OUT
OUT
Measure single
sideband phase spur
power in dBc
Clock
Source
IN+
IN-
Vcco Vcc
LMK00105
www.ti.com
SNAS579F –MARCH 2012–REVISED MAY 2013
Power Supply Ripple Rejection
In practical system applications, power supply noise (ripple) can be generated from switching power supplies,
digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to
understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is
applied to the power supply of a clock distribution device, such as LMK00105, it can produce narrow-band phase
modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise
spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in
dBc).
For the LMK00105, power supply ripple rejection (PSRR), was measured as the single-sideband phase spur
level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vddo supply. The PSRR
test setup is shown in Figure 12.
Figure 12. PSRR Test Setup
A signal generator was used to inject a sinusoidal signal onto the Vddo supply of the DUT board, and the peak-to-
peak ripple amplitude was measured at the Vddo pins of the device. A limiting amplifier was used to remove
amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise
analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following
power supply ripple conditions:
• Ripple amplitude: 100 mVpp on Vddo = 2.5 V
• Ripple frequency: 100 kHz
Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ)
can be calculated using the measured single-sideband phase spur level (PSRR) as follows:
DJ (ps pk-pk) = [(2 * 10(PSRR/20)) / (π* fclk)] * 1012 (5)
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMK00105
0.2 mm, typ
1.0 mm,
typ
2.6 mm, min
LMK00105
SNAS579F –MARCH 2012–REVISED MAY 2013
www.ti.com
Power Supply Bypassing
The Vdd and Vddo power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very
close to each supply pin. Placing the bypass capacitors on the same layer as the LMK00105 improves input
sensitivity and performance. All bypass and decoupling capacitors should have short connections to the supply
and ground plane through a short trace or via to minimize series inductance.
Thermal Management
For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is, as
an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125°C.
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent
electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
A recommended land and via pattern is shown in Figure 13. More information on soldering WQFN packages and
gerber footprints can be obtained: www.ti.com/packaging.
To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground
plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite
side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but
should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in
Figure 13 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively
dissipated.
Figure 13. Recommended Land and Via Pattern
14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMK00105
LMK00105
www.ti.com
SNAS579F –MARCH 2012–REVISED MAY 2013
REVISION HISTORY
Changes from Revision E (February 2013) to Revision F Page
• Added device name to title of document. ............................................................................................................................. 1
• Changed all LLP and QFN packages to WQFN throughout document. ............................................................................... 1
• Deleted optional from CLKin* pin description. And changed complimentary to complementary. ........................................ 2
• Added max limit to Output Skew parameter and added tablenote to parameter in Electrical Characteristics Table. .......... 4
• Changed typical value for both conditions of Propagation Delay in the Electrical Characteristics Table. ........................... 4
• Added Min/Max limits to both conditions of Propagation Delay parameter in Electrical Characteristics Table. .................. 4
• Changed unit value for the first condition of Part-to-part Skew from ps to ns in the Electrical Characteristics Table. ........ 4
• Changed both Max values of each Part-to-part Skew condition in Electrical Characteristics Table. ................................... 4
• Changed the Typ value of each Rise/Fall Time condition in the Electrical Characteristics Table. ...................................... 4
• Deleted VIL table note. .......................................................................................................................................................... 5
• Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table. ........................ 5
• Added CLKin* column to CLKin Input vs. Output States table. Also added fourth row starting with Logic Low under
CLKin column. ....................................................................................................................................................................... 9
• Changed table title from CLKin input vs. Output States to OSCin Input vs. Output States ................................................. 9
• Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Removed extra
references to other figures. Revised to better correspond with information in Electrical Characteristics Table. ............... 10
• Deleted Figure 10 (Near End termination) and Figure 11 (Far End termination) from Driving the Clock Inputs section ... 10
• Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section. ............ 10
• Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic. ............ 10
• Deleted sentence in reference to two deleted images. ...................................................................................................... 11
• Changed link from National packaging site to TI packaging site. ....................................................................................... 14
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMK00105
PACKAGE OPTION ADDENDUM
www.ti.com 3-May-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMK00105SQ/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00105
LMK00105SQE/NOPB ACTIVE WQFN RTW 24 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00105
LMK00105SQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMK00105SQ/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LMK00105SQE/NOPB WQFN RTW 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LMK00105SQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMK00105SQ/NOPB WQFN RTW 24 1000 210.0 185.0 35.0
LMK00105SQE/NOPB WQFN RTW 24 250 210.0 185.0 35.0
LMK00105SQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-May-2013
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
www.ti.com
SQA24A (Rev B)
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