THC63LVD827-Z_Rev.1.00_E THC63LVD827-Z LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER General Description Features The THC63LVD827-Z transmitter is designed to support pixel data transmission between Host and Flat Panel Display and Dual Link transmission between Host and Flat Panel Display up to 1080p/1920x1200 resolutions. The THC63LVD827-Z converts 27bits (RGB 8 bits + Hsync, Vsync, DE) of CMOS/TTL data into LVDS (Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. For dual LVDS out, LVDS clock frequency of 87MHz, 51bits of RGB data are transmitted at an effective rate of 609Mbps per LVDS channel. For single LVDS out, LVDS clock frequency of 174MHz, 27bits of RGB data are transmitted at an effective rate of 1218Mbps per LVDS channel. 21bits (RGB 6 bits + Hsync, Vsync, DE) mode is also selectable for 6bit color transmission with lower power. * Low power 1.8V CMOS design * 7mm x 7mm/72pin/0.65mm pitch/TFBGA package applicable to non-HDI PCB. * Wide dot clock range, 10-174MHz, suited for TV Signal: up to 1080p(74.25MHz dual) PC Signal: up to 1920x1200(77MHz dual) * Supports 1.8V single power supply * 1.8V/2.5V/3.3V TTL/CMOS inputs are supported by setting IOVCC=1.8V/2.5V/3.3V * LVDS swing reducible by RS-pin to reduce both EMI and power consumption * PLL requires No external components * Flexible Input / Output mode 1. Single in / Dual LVDS out 2. Single in / Single LVDS out 3. Double edge Single in / Dual LVDS out * 2 LVDS data mapping to simplify PCB layout * Power down mode * Input clock triggering edge selectable by R/F pin * 6bit / 8bit modes selectable by 6B/8B pin Block Diagram R17~R10 G17~G10 B17~B10 CLKIN Figure 1. Block Diagram Copyright(c)2018 THine Electronics, Inc. 1 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Pin Diagram (top view) Figure 2. Pin Diagram Copyright(c)2018 THine Electronics, Inc. 2 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Pin Description Pin Name TA1+,TA1TB1+,TB1TC1+,TC1TD1+, TD1TCLK1+, TCLK1TA2+,TA2TB2+,TB2TC2+,TC2TD2+, TD2TCLK2+, TCLK2- Table 1. Pin Description Type DE VSYNC HSYNC CLKIN Pin # A1,B1 A2,B2 A3,B3 A5,B5 A4,B4 A6,B6 A7,B7 A8,B8 C9,C8 A9,B9 G1,G2,F1,F2 E1,E2,D1,D2 J4,H4,J3,H3 J2,H2,J1,H1 J8,H8,J7,H7 J6,H6,J5,H5 G9 H9 J9 F9 R/F G8 IN RS F8 IN R17~R10 G17~G10 B17~B10 Description The 1st Link. The 1st pixel output data when Dual out. Output data when Single out. LVDS OUT LVDS Clock Out for 1st Link. The 2nd Link. The 2nd pixel output data when Dual out. LVDS Clock Out for 2nd Link. IN Pixel Data Inputs. IN IN IN IN Data Enable Input. Vsync Input. Hsync Input. Clock Input. Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge LVDS swing mode select. RS H L LVDS Swing(VOD, see Fig.7 and Fig.8) 350mV 200mV LVDS mapping table select. See Fig.12 and Fig.13. E8 MAP MAP H L IN Mapping Mode Mapping MODE1 Mapping MODE2 Pixel data mode. See Fig.10 and Fig.11. MODE E7 IN O/E D9 IN /PDWN D8 IN C1 IN PRBS (*a) Copyright(c)2018 THine Electronics, Inc. MODE H L Modes Single out (Single-in / Single-out) Dual out (Single-in / Dual-out) Output enable H: Output enable. L: Output disable (all outputs are Hi-Z). Power Down enable H: Normal operation. L: Power down (all outputs are Hi-Z and all circuits are stand-by mode with minimum current (ITCCS)). Must be tied to GND. 3 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Pin Description (Continued) Pin Name Reserved1 Pin # C3 Type IN 6B/8B F7 IN DDRN E9 IN N/C VCC IOVCC LVDSVCC PLLVCC C2 G3,G5 G7 C5,D3 C7 F3,G4,G6,C4, E3,C6,D7 - GND Power Ground Description Must be tied to GND. 6bit / 8bit mode select. H: 6bit mode (21bit mode), L: 8bit mode (27bit mode). DDR function is active when MODE=L (Dual-out mode) H: DDR (Double Edge input) function disable (Fig.7). L: DDR (Double Edge input) function enable (Fig.8). Must be Open. Power Supply Pins for digital circuitry. Power Supply Pins for IO inputs circuitry. Power Supply Pins for LVDS Outputs. Power Supply Pins for PLL circuitry. Ground Pins. (*a) : Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of 223-1. The generated PRBS is fed into input data latches, encoded and serialized into LVDS OUT. This function is normally to be used for analyzing the signal integrity of the transmission channel including PCB traces, connectors, and cables. Copyright(c)2018 THine Electronics, Inc. 4 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Absolute Maximum Ratings Table 2. Absolute Maximum Rating Parameter Min Max Power Supply Voltage (IOVCC) Power Supply Voltage (VCC,PLLVCC,LVDSVCC) CMOS/TTL Input Voltage LVDS Transmitter Output Voltage Output Current Junction Temperature Storage Temperature Range Reflow Peak Temperature / Time Maximum Power Dissipation @+25C -0.3 -0.3 -0.3 -0.3 -50 -55 - Unit +4.0 +2.1 IOVCC+0.3 LVDSVCC+0.3 +50 +125 +125 +260 / 10sec 1.3 V V V V mA C C C W Recommended Operating Conditions Table 3. Operating Condition Parameter Symbol Ta Min Typ Max Unit Operating Ambient Temperature -40 +105 C IOVCC Power Supply Voltage 1.62 25 1.8 2.5 3.3 3.6 V PLLVCC LVDSVCC VCC Power Supply Voltage 1.62 1.8 1.98 V 20 10 10 10 - 174 87 174 174 MHz 10 10 - 174 174 Fclk Clock Frequency Single Edge Input (DDRN=H) MODE = L Double Edge Dual - out Input (DDRN=L) MODE=H Single - out Copyright(c)2018 THine Electronics, Inc. Input LVDS Output Input LVDS Output Input LVDS Output 5 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Electrical Characteristics CMOS/TTL (Pin type "IN") DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Table 4. CMOS/TTL DC Specifications Symbol VIH18 Parameter Conditions High Level Data Input Voltage Min Typ Max Unit 0.65*IOVCC - IOVCC V GND - 0.35*IOVCC V 1.7 - IOVCC V GND - 0.7 V 2.0 - IOVCC V GND - 0.8 V -10 - +10 A IOVCC=1.62V~1.98V VIL18 Low Level Data Input Voltage VIH25 High Level Data Input Voltage IOVCC=2.3V~2.7V VIL25 Low Level Data Input Voltage VIH33 High Level Data Input Voltage IOVCC=3.0V~3.6V VIL33 Low Level Data Input Voltage IINC Input Current VIN=GND~IOVCC LVDS Transmitter (Pin type "LVDS OUT") DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Table 5. LVDS Transmitter DC Specifications Symbol VOD VOD VOC Parameter Differential Output Voltage Conditions RL = 100 Min Typ Max Normal swing RS=H 250 350 450 Reduced swing RS=L 140 200 300 - - 35 1.125 1.25 1.375 V - - 35 mV - - 100 mA -20 - +20 A Change in VOD between complementary output states Common Mode Voltage RL = 100 VOC Change in VOC between complementary output states IOS Output Short Circuit Current VOUT=GND, RL = 100 IOZ Output TRI-State Current /PDWN=L, VOUT = GND ~ LVDSVCC Copyright(c)2018 THine Electronics, Inc. 6 / 18 Unit mV THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Electrical Characteristics (Continued) Power Supply Current Over recommended operating supply and temperature ranges unless otherwise specified. Table 6. Power Supply Current Symbol Parameter Conditions CLKIN=37MHz MODE = H Single - out CLKIN=65MHz CLKIN=72MHz CLKIN=89MHz ITCCW Operating Current RL=100 CL=5pF RS=H (RS=L) MODE = L Dual - out DDRN = H DDR Input Off CLKIN=119MHz CLKIN=139MHz CLKIN=154MHz CLKIN=44.5MHz MODE = L Dual - out DDRN = L DDR Input On CLKIN=59.5MHz CLKIN=69MHz CLKIN=77MHz Typ(a) 24 (18) 29 (23) 30 (24) 48 (36) 53 (41) 56 (44) 58 (46) 47 (35) 51 (39) 54 (42) 56 (44) Max(b) 33 (26) 43 (37) 46 (40) 65 (53) 75 (63) 82 (70) 88 (76) 64 (52) 74 (62) 80 (68) 85 (73) Unit mA Power Down /PDWN = L, All Inputs = Fixed L or H 1 140 A Current (a) All Typ. values are at VCC=1.8V, Ta=25C . The 256 Grayscale Test Pattern inputs test for a typical display pattern. (b) All Max. values are at VCC=1.98V, Ta=105C . Worst Case Test Pattern produces maximum switching frequency for all the LVDS outputs (Fig.3). ITCCS Figure 3. Test Pattern (LVDS Output Full Toggle Pattern) Copyright(c)2018 THine Electronics, Inc. 7 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Table 7. Switching Characteristics Symbol Parameter Min Typ Max Unit 5.75 - 100 ns tTCIP CLKIN Period (Fig.7,8) tTCH CLKIN High Time (Fig.7,8) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns tTCL CLKIN Low Time (Fig.7,8) 0.35tTCIP 0.5tTCIP 0.65tTCIP ns tTS TTL Data Setup to CLK IN (Fig.7,8) 0.8 - - ns tTH TTL Data Hold to CLK IN (Fig.7,8) 0.8 - - ns CLKIN to TCLK+/Delay (Fig7,8) MODE=L,DDRN=H 9tTCIP +3.1 - 9tTCIP +8.0 ns tTCD Others 5tTCIP +3.1 - 5tTCIP +8.0 ns tTCOP TCLK1,2 Period (Fig.6) 5.75 - 100 ns tLVT LVDS Transition Time (Fig.4) - 0.6 1.5 ns tTOP1 Output Data Position0 (Fig.9) -0.15 0.0 +0.15 ns tTOP0 Output Data Position1 (Fig.9) tTOP6 Output Data Position2 (Fig.9) tTOP5 Output Data Position3 (Fig.9) tTOP4 Output Data Position4 (Fig.9) tTOP3 Output Data Position6 (Fig.9) tTPLL Phase Lock Time (Fig.5) tDEINT DE Input Period (Fig.6) Dual out mode only(MODE=L) DE Input Period (Fig.6) Dual out mode only(MODE=L) DE Input Period (Fig.6) Dual out mode only(MODE=L) tDEH tDEL tTCOP =5.75ns~15ns Output Data Position5 (Fig.9) tTOP2 +0.15 -0.15 2 tTCOP 3 tTCOP 4 tTCOP 5 tTCOP 6 tTCOP 2 2 tTCOP +0.15 ns -0.15 3 tTCOP 3 tTCOP +0.15 ns -0.15 4 tTCOP 4 tTCOP +0.15 ns 5 tTCOP 5 tTCOP +0.15 ns 6 tTCOP 6 tTCOP +0.15 ns -0.15 -0.15 -0.15 - - 10.0 ms 4tTCIP tTCIP *(2n)(a) - ns 2tTCIP tTCIP *(2m)(a) - ns 2tTCIP - - ns (a) Refer to Fig.6 for details. Copyright(c)2018 THine Electronics, Inc. 8 / 18 ns tTCOP THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E AC Timing Diagrams RL= Figure 4. LVDS Output Load and Transition Time Figure 5. PLL Lock Time Note: Dual-out mode(MODE=L) The period between rising edges of DE (tDEINT), high time of DE (tDEH) should always satisfy following equations. tDEH = tTCIP * (2m) tDEINT = tTCIP * (2n) m, n = integer Figure 6. Dual-out mode DE input timing Copyright(c)2018 THine Electronics, Inc. 9 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E AC Timing Diagrams(Continued) Figure 7. CLKIN Period, High/Low Time, Setup/Hold Timing for Single Edge Input Mode MODE = H or DDRN = H Figure 8. CLKIN Period, High/Low Time, Setup/Hold Timing for Double Edge Input Mode(DDR) MODE = L, DDRN = L Copyright(c)2018 THine Electronics, Inc. 10 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E AC Timing Diagrams(Continued) Figure 9. LVDS Output Data Position Copyright(c)2018 THine Electronics, Inc. 11 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Single-In / Dual-Out Mode (MODE = L) Figure 10. Single-In / Dual-Out Mode (MODE = L) Copyright(c)2018 THine Electronics, Inc. 12 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Single-In / Single-Out Mode (MODE = H) Figure 11. Single-In / Single-Out Mode (MODE = H) Copyright(c)2018 THine Electronics, Inc. 13 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E LVDS Data Mapping for 8 bit Mode (6B/8B = L) TCLKn+/Previous Cycle Current Cycle TAn+/- R13 R12 G12 R17 R16 R15 R14 R13 R12 TBn+/- G14 G13 B13 B12 G17 G16 G15 G14 G13 TCn+/- B15 B14 DE B17 B16 B15 B14 TDn+/- R11 R10 0 G11 G10 R11 R10 VSYNC HSYNC B11 B10 n=1,2 (a) LVDS Data Mapping when MAP = H (Mapping Mode 1) TCLKn+/Previous Cycle Current Cycle TAn+/- R11 R10 G10 R15 R14 R13 R12 R11 R10 TBn+/- G12 G11 B11 B10 G15 G14 G13 G12 G11 TCn+/- B13 B12 DE B15 B14 B13 B12 TDn+/- R17 R16 0 G17 G16 R17 R16 VSYNC HSYNC B17 B16 n=1,2 (b) LVDS Data Mapping when MAP = L (Mapping Mode 2) Figure 12. LVDS Data Mapping for 8 bit Mode (6B/8B = L) Copyright(c)2018 THine Electronics, Inc. 14 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E LVDS Data Mapping for 6 bit Mode (6B/8B = H) TCLKn+/Previous Cycle Current Cycle TAn+/- R13 R12 G12 R17 R16 R15 R14 R13 R12 TBn+/- G14 G13 B13 B12 G17 G16 G15 G14 G13 TCn+/- B15 B14 DE B17 B16 B15 B14 VSYNC HSYNC HiZ TDn+/n=1,2 (a) LVDS Data Mapping when MAP = H (Mapping Mode 1) TCLKn+/Previous Cycle Current Cycle TAn+/- R11 R10 G10 R15 R14 R13 R12 R11 R10 TBn+/- G12 G11 B11 B10 G15 G14 G13 G12 G11 TCn+/- B13 B12 DE B15 B14 B13 B12 VSYNC HSYNC HiZ TDn+/n=1,2 (b) LVDS Data Mapping when MAP = L (Mapping Mode 2) Figure 13. LVDS Data Mapping for 6 bit Mode (6B/8B = H) Note: Input pins which are not used in 6 bit Mode (R10-11,G10-11,B10-11 on Mapping Mode 1, R16-17,G16-17,B16-17 on Mapping Mode 2) can be H, L, or Open. Copyright(c)2018 THine Electronics, Inc. 15 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Note 1) Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 2) GND Connection Connect the each GND of the PCB which THC63LVD827-Z and LVDS-Rx on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 3) Multi Drop Connection Multi drop connection is not recommended. TCLK+ THC63LVD827-Z LVDS-Rx TCLKLVDS-Rx Figure 14. Multi Drop Connection 4) Asynchronous Use Asynchronous use such as following systems are not recommended. CLKOUT IC CLKOUT TCLK+ THC63LVD827-Z DATA CLKOUT TCLK- LVDS-Rx DATA LVDS-Rx DATA IC TCLK+ THC63LVD827-Z DATA TCLK- CLKOUT IC TCLK+ THC63LVD827-Z DATA CLKOUT DATA TCLKTCLK+ THC63LVD827-Z IC TCLK- Figure 15. Asynchronous Use Copyright(c)2018 THine Electronics, Inc. 16 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Package TFBGA Figure 16. Package Diagram Copyright(c)2018 THine Electronics, Inc. 17 / 18 THine Electronics, Inc. Security E THC63LVD827-Z_Rev.1.00_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. THine Electronics, Inc. ("THine") is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately. 3. This material contains THine's copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without THine's prior permission is prohibited. 4. Note that even if infringement of any third party's industrial ownership should occur by using this product, THine will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. Product Application 5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of IATF16949 ("the Specified Product") in this data sheet. THine accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user's request, testing of all functions and performance of the product is not necessarily performed. 9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Act. 10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. THine Electronics, Inc. sales@thine.co.jp https://www.thine.co.jp Copyright(c)2018 THine Electronics, Inc. 18 / 18 THine Electronics, Inc. Security E