LT4295 IEEE 802.3bt PD Interface with Forward/Flyback Controller FEATURES DESCRIPTION IEEE 802.3af/at/bt Powered Device (PD) with Forward/Flyback Controller nn Supports Up to 71.3W PDs nn 5-Event Classification Sensing nn Superior Surge Protection (100V Absolute Maximum) nn Wide Junction Temperature Range (-40C to 125C) nn >94% End-to-End Efficiency with LT4321 Ideal Bridge nn External Hot Swap N-Channel MOSFET for Lowest Power Dissipation and Highest System Efficiency nn No-Opto Flyback Operation nn Auxiliary Power Support as Low as 9V nn Easy Migration of LTPoE++(R) PDs to IEEE 802.3bt PDs nn Pin Compatible with LT4276A/B/C nn 28-Lead 4mm x 5mm QFN Package The LT(R)4295 is an IEEE 802.3af/at/bt-compliant powered device (PD) interface controller with a switching regulator controller. The T2P output indicates the number of classification events received during IEEE 802.3bt-compliant mutual identification and negotiation of available power. APPLICATIONS The LT4295 also includes an on-chip detection signature resistor, thermal protection, slope compensation, and many user configurable settings including classification signature, inrush current, switcher frequency, gate drive delay, soft-start and load compensation. nn High Power Wireless Data Systems Outdoor Security Camera Equipment nn Commercial and Public Information Displays nn High Temperature Applications nn nn The LT4295 supports both forward and flyback power supply topologies. The flyback topology supports No-Opto feedback. Auxiliary input voltages can be accurately sensed with just a resistor divider connected to the AUX pin. The LT4295 utilizes an external, low RDS(on) N-channel hot swap MOSFET and supports the LT4320/LT4321 ideal diode bridges, to extend the end-to-end power delivery efficiency and eliminate costly heat sinks. All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION IEEE 802.3bt 71.3W (Class 8) PD Controller and Power Supply in Forward Mode AUX 37V TO 57V VPORT + - + - 22F FMMT723 0.1F 3.3k 10nF VPORT HS GATE AUX * + 100H BAV19WS (TRR 50ns) 10F VIN HS SW SRC VCC VCC FFS PG DLY ISEN+ LT4295 VCC 20m ISEN- RCLASS RCLASS++ GND FB31 SS ROSC * SG T2P ITHB OPTO 0.1F 10k 100pF 100k TO MICROPROCESSOR + Single-Signature Power Classification (at PD Input) 5V 13A CLASS POWER - 0 13W 1 3.84W 2 6.49W 3 13W 4 25.5W 5 40W 6 51W 7 62W 8 71.3W 4295 TA01 Rev. B Document Feedback For more information www.analog.com 1 LT4295 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) SWVCC VIN HSSRC HSGATE NC VPORT TOP VIEW 28 27 26 25 24 23 GND 1 22 DNC AUX 2 21 VCC RCLASS++ 3 20 PG 29 GND RCLASS 4 T2P 5 19 GND 18 SG 17 ISEN+ VCC 6 VCC 7 16 ISEN- VCC 8 15 RLDCMP FB31 ITHB FFSDLY SFST VCC 9 10 11 12 13 14 ROSC VPORT, HSSRC, VIN Voltages................... -0.3V to 100V HSGATE Current.................................................. 20mA VCC Voltage................................................... -0.3V to 8V RCLASS, RCLASS++ Voltages............................... -0.3V to 8V (and VPORT) SFST, FFSDLY, ITHB, T2P Voltages.... -0.3V to VCC+0.3V ISEN+, ISEN- Voltages............................................0.3V FB31 Voltage...................................................+12V/-30V RCLASS/RCLASS++ Current............................... -50mA AUX Current......................................................... 1.4mA ROSC Current...................................................... 100A RLDCMP Current.................................................500A T2P Current..........................................................-2.5mA Operating Junction Temperature Range (Note 3) LT4295I.................................................-40C to 85C LT4295H............................................. -40C to 125C Storage Temperature Range................... -65C to 150C UFD PACKAGE 28-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 150C, JC = 3.4C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4295IUFD#PBF LT4295IUFD#TRPBF 4295 28-Lead (4mm x 5mm) Plastic QFN -40C to 85C LT4295HUFD#PBF LT4295HUFD#TRPBF 4295 28-Lead (4mm x 5mm) Plastic QFN -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. B 2 For more information www.analog.com LT4295 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VVPORT = VHSSRC = VVIN = 40V, VVCC = VCCREG, ROSC, PG, and SG Open, RFFSDLY = 5.23k to GND. AUX connected to GND unless otherwise specified. (Note 2) SYMBOL PARAMETER CONDITIONS MIN VPORT, HSSRC, VIN Operating Voltage At VPORT Pin l TYP MAX 60 UNITS V VSIG VPORT Detection Signature Range At VPORT Pin l 1.5 10 V VCLASS VPORT Classification Signature Range At VPORT Pin l 12.5 21 V VMARK VPORT Mark Event Range At VPORT Pin, After 1st Classification Event l 5.6 10 V VPORT AUX Range At VPORT Pin, VAUX 6.45V l 8 60 V Detect/Class Hysteresis Window l 1.0 2.6 Reset Threshold l VHSON Hot Swap Turn-On Voltage l VHSOFF Hot Swap Turn-Off Voltage l 30 Hot Swap On/Off Hysteresis Window l 3 V 35 5.6 V 37 V 31 V V Supply Current VPORT, HSSRC and VIN Supply Current VVPORT = VHSSRC = VVIN = 60V VPORT Supply Current During Classification VVPORT = 17.5V, RCLASS, RCLASS++ Open 2 mA 1.3 mA 2.2 mA 24.4 25.5 k 5.2 8.3 11.4 k 1.36 1.40 1.43 V l l 0.7 VVPORT = VMARK after 1st Classification Event l 0.4 Detection Signature Resistance VSIG (Note 4) l 23.6 Resistance During Mark Event RCLASS/RCLASS++ Voltage VMARK (Note 4) l -10mA IRCLASS -36mA, VCLASS l VVPORT Step GND to 17.5V, 35.7 from RCLASS to GND l VPORT Supply Current During Mark Event 1.0 Detection and Classification Signature Classification Signature Stability Time 2 ms Digital Interface VAUXT AUX Threshold VPORT = 17.5V, VIN = VHSSRC = 18.5V l 6.05 6.25 6.45 V IAUXH AUX Pin Current VAUX = 6.05V, VPORT = 17.5V, VIN = 9V, VCC = 0V l 3.3 5.3 7.3 A T2P Output High VVCC - VT2P, -1mA Load l 0.3 V T2P Leakage VT2P = 0V l -1 1 A HSGATE Pull Up Current VHSGATE - VHSSRC = 5V (Note 5) l -27 -18 A HSGATE Voltage -10A Load, with Respect to HSSRC l 10 14 V HSGATE Pull Down Current VHSGATE - VHSSRC = 5V l 400 l 7.2 7.6 8.0 l 3.11 3.17 3.23 Hot Swap Control IGPU -22 A VCC Supply VCCREG VCC Regulation Voltage V Feedback Amplifier VFB FB31 Regulation Voltage -0.1 V FB31 Pin Bias Current RLDCMP Open A gm Feedback Amplifier Average Trans-Conductance Time Average, -2A < IITHB < 2A l -52 -40 -26 A/V ISINK ITHB Average Sink Current Time Average, VFB31 = 0V l 4.4 8.0 13.4 A Charging Current VSFST = 0.5V, 3.0V l -49 -42 -36 A Soft-Start ISFST Rev. B For more information www.analog.com 3 LT4295 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VVPORT = VHSSRC = VVIN = 40V, VVCC = VCCREG, ROSC, PG, and SG Open, RFFSDLY = 5.23k to GND. AUX connected to GND unless otherwise specified. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Outputs VCC -0.1 V PG, SG Output High Level I = -1mA l PG, SG Output Low Level I = 1mA l PG Rise Time, Fall Time PG = 1000pF 15 ns SG Rise Time, Fall Time SG = 400pF 15 ns 1 V Current Sense/Overcurrent VFAULT Overcurrent Fault Threshold l 125 140 155 mV VSENSE/ VITHB Current Sense Comparator Threshold with Respect to VITHB VISEN+ - VISEN- l -130 -111 -92 mV/V VITHB(OS) VITHB Offset l 3.03 3.17 3.33 V Timing fOSC fT2P Default Switching Frequency ROSC Pin Open l 200 214 223 kHz Switching Frequency 45.3k from ROSC to GND l 280 300 320 kHz T2P Signal Frequency fSW/256 T2P Duty Cycle in PoE Operation (Note 7) After 4-Event Classification After 5-Event Classification (RCLASS++ Has Resistor to GND) 50 25 % % T2P Duty Cycle in Auxiliary Supply Operation (Note 7) V(AUX) > VAUXT, and RCLASS++ Has Resistor to GND 25 % tMIN Minimum PG On Time DMAX Maximum PG Duty Cycle tPGDELAY PG Turn-On Delay-Flyback PG Turn-On Delay-Forward l 175 l 63 5.23k from FFSDLY to GND 52.3k from FFSDLY to GND 10.5k from FFSDLY to VCC 52.3k from FFSDLY to VCC 250 330 66 70 ns % 45 171 92 391 ns ns ns ns tFBDLY Feedback Amp Enable Delay Time 350 ns tFB Feedback Amp Sense Interval 550 ns tPGSG PG Falling to SG Rising Delay Time-Flyback PG Falling to SG Falling Delay TimeForward Resistor from FFSDLY to GND 10.5k from FFSDLY to VCC 52.3k from FFSDLY to VCC 20 67 301 ns ns ns tSTART Start Timer (Note 6) Delay After Power Good l 80 86 93 ms tFAULT Fault Timer (Note 6) Delay After Overcurrent Fault l 80 86 93 ms IMPS MPS Current l 10 12 14 mA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted. Note 3. This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature can exceed 150C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4. Detection signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. Note 5. IGPU available in PoE powered operation. That is, available after V(VPORT) > VHSON and V(AUX) < VAUXT, over the range where V(VPORT) is between VHSOFF and 60V. Note 6. Guaranteed by design, not subject to test. Note 7. Specified as the percentage of the period which T2P is low impedance with respect to VCC. Rev. B 4 For more information www.analog.com LT4295 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Signature Range SIGNATURE RESISTANCE (k) 125C 85C 25C -40C 0.4 VPORT CURRENT (mA) 26.25 0.3 0.2 0.1 0 2 0 4 6 VPORT VOLTAGE (V) 8 125C 85C 25C -40C 25.75 24.25 3.178 1 2 3 4 5 6 7 VPORT VOLTAGE (V) 15 3.176 8 -25 0 25 50 75 TEMPERATURE (C) 100 5 0 -5 -15 2.57 125 2.77 2.97 3.17 3.37 FB31 VOLTAGE (V) 3.57 10 20 30 40 50 DUTY CYCLE (%) 300 TPGDELAY, 52.3k FROM FFSDLY TO GND 150 100 60 70 4295 G07 0 -50 250 100 125 -25 0 25 50 75 TEMPERATURE (C) 100 4295 G08 TPGSG, 52.3k FROM FFSDLY TO VCC 150 50 125 TPGDELAY, 52.3k FROM FFSDLY TO VCC 200 100 TPGDELAY, 5.23k FROM FFSDLY TO GND VITHB = 2.9V 0 25 50 75 TEMPERATURE (C) 400 50 VITHB = 2.6V -25 PG, SG Delay Time vs Temperature in Forward Mode DELAY TIME (ns) PG DELAY TIME (ns) V(ISEN+ - ISEN-) (mV) VITHB = 2.3V 0 ROSC OPEN 350 80 20 225 4295 G06 250 VITHB = 1.8V 40 250 175 -50 3.77 200 60 275 PG Delay Time vs Temperature in Flyback Mode 100 0 45.3k FROM ROSC TO GND 300 VITHB = 0.96V (FB31 = 0V) 120 125 325 4295 G05 Current Sense Voltage vs Duty Cycle, ITHB 140 100 200 4295 G04 160 0 25 50 75 TEMPERATURE (C) Switching Frequency vs Temperature -10 3.164 3.162 -50 -25 4295 G03 FREQUENCY (kHz) ITHB CURRENT (A) 3.174 3.166 4 0 -50 9 125C 85C 25C -40C 10 3.168 214kHz 6 2 Feedback Amplifier Output Current vs VFB31 3.170 8 4295 G02 VFB31 vs Temperature VFB31 (V) 300kHz 24.75 4295 G01 3.172 VCC Current vs Temperature 10 25.25 23.75 10 12 VCC CURRENT (mA) 0.5 Detection Signature Resistance vs Input Voltage 0 -50 TPGDELAY, 10.5k FROM FFSDLY TO VCC TPGSG, 10.5k FROM FFSDLY TO VCC -25 0 25 50 75 TEMPERATURE (C) 100 125 4295 G09 Rev. B For more information www.analog.com 5 LT4295 PIN FUNCTIONS GND(Pins 1, 19, Exposed Pad Pin 29): Device Ground. Exposed Pad must be electrically and thermally connected to pins 1, 19 and PCB GND. AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive divider from the auxiliary power input to set the voltage at which the auxiliary supply takes over. Asserting AUX pulls down HSGATE, disconnects the detection signature resistor and disables classification signature. The AUX pin sinks IAUXH when below its threshold voltage, of VAUXT, to provide hysteresis. Connect to GND if not used. RCLASS++ (Pin 3): Class Select Input. Connect a resistor between RCLASS++ to GND per Table1. RCLASS (Pin 4): Class Select Input. Connect a resistor between RCLASS and GND per Table1. T2P (Pin 5): PSE Type Indicator. Open drain with respect to VCC. See the T2P Output section for pin behavior. VCC (Pins 6, 7, 8, 9, 21): Switching Regulator Controller Supply Voltage. Connect a local ceramic capacitor from VCC pin 21 to GND pin 19 as close as possible to LT4295 as shown in Table3. ROSC (Pin 10): Programmable Frequency Adjustment. Resistor to GND programs operating frequency. Leave open for default frequency of 214kHz. FB31 (Pin 14): Feedback Input. In flyback mode, connect external resistive divider from the third winding feedback. Reference voltage is 3.17V. Connect to GND in forward mode. RLDCMP (Pin 15): Load Compensation Adjustment. Optional resistor to GND controls output voltage set point as a function of peak switching current. Leave RLDCMP open if load compensation is not needed. ISEN- (Pin 16): Current Sense, Negative Input. Route as a dedicated trace to the return side of the current sense resistor. ISEN+ (Pin 17): Current Sense, Positive Input. Route as a dedicated trace to the sense side of the current sense resistor. SG (Pin 18): Secondary (Synchronous) Gate Drive Output. PG (Pin 20): Primary Gate Drive Output. DNC (Pin 22): Do Not Connect. Leave pin open. SWVCC (Pin 23): Switch Driver for VCC's Buck Regulator. This pin drives the base of a PNP in a buck regulator to generate VCC. VIN (Pin 24): Buck Regulator Supply Voltage. Usually separated from HSSRC by a pi filter. SFST (Pin 11): Soft-Start. Capacitor to GND sets softstart timing. HSSRC (Pin 25): External Hot Swap MOSFET Source. Connect to source of the external MOSFET. FFSDLY (Pin 12): Forward/Flyback Select and Primary Gate Delay Adjustment. Resistor to GND adjusts gate drive delay for a flyback topology. Resistor to VCC adjusts gate drive delay for a forward topology. HSGATE (Pin 26): External Hot Swap MOSFET Gate Control Output. Capacitance to GND determines inrush time. ITHB (Pin 13): Current Threshold Control. The voltage on this pin corresponds to the peak current of the external primary FET. Note that the voltage gain from ITHB to the input of the current sense comparator (VSENSE) is negative. VPORT (Pin 28): PD Interface Supply Voltage and External Hot Swap MOSFET Drain Connection. NC (Pin 27): No Connection. Not internally connected. Rev. B 6 For more information www.analog.com LT4295 BLOCK DIAGRAM VPORT VIN SWVCC START-UP REGULATOR INTERNAL BUCK CONTROLLER CP HSGATE VCC 11V VCC PD INTERFACE CONTROLLER HSSRC VPORT - + - + RCLASS T2P 1.4V 1.4V TSD GND VPORT RCLASS++ PG SG + - AUX VAUXT IAUXH FB31 VFB + - ITHB VCC FEEDBACK AMP gm = -40A/V SFST SWITCHING REGULATOR CONTROLLER LOAD COMP FFSDLY OSC + - VFAULT + - - + AV = 10 AV = SLOPE COMP VSENSE VITHB VSENSE AV = 1 ISEN+ - + CURRENT SENSE COMPARATOR - + CURRENT FAULT COMPARATOR ROSC VITHB(OS) 4295 BD ISEN- RLDCMP Rev. B For more information www.analog.com 7 LT4295 APPLICATIONS INFORMATION OVERVIEW VSENSE Power over Ethernet (PoE) continues to gain popularity as products take advantage of the combination of DC power and high speed data available from a single RJ45 connector. The LT4295 is IEEE 802.3bt-compliant and allows up to 71.3 Watt operation while maintaining backwards compatibility with existing PSE systems. The LT4295 combines a PoE PD interface controller and a switching regulator controller capable of either flyback or forward isolated power supply operation. SIGNIFICANT DIFFERENCES FROM PREVIOUS PRODUCTS The LT4295 has several significant differences from previous Analog Devices products. These differences are briefly summarized below. IEEE 802.3bt vs LTPoE++ Available PD Power The LT4295 supports IEEE 802.3bt PD power levels up to 71.3 Watts. A PD requiring more than 71.3 Watts is beyond the allowable power levels of IEEE 802.3bt. The LT4293, LT4275A and LT4276A are available to support PD power levels up to 90W under the LTPoE++ standard. See the Related Parts section for a list of LTPoE++ PSEs and PDs. ITHB Is Inverted from the Usual ITH pin The ITHB pin voltage has an inverse relationship to the current sense comparator threshold, VSENSE. Furthermore, the ITHB pin offset voltage, VITHB(OS), is 3.17V. See Figure1. VSENSE VITHB VITHB(OS) VITHB 4295 F01 Figure1. VSENSE vs. VITHB Duty-Cycle Based Soft-Start The LT4295 uses a duty cycle ramp soft-start that injects charge into ITHB. This allows startup without appreciable overshoot using inexpensive external components. The Feedback Pin FB31 is 3.17V Rather Than 1.25V The error amp feedback voltage VFB is 3.17V. Flyback/Forward Mode Is Pin Selectable The LT4295 operates in flyback mode if FFSDLY is pulled down by a resistor to GND. It operates in forward mode if FFSDLY is pulled up by a resistor to VCC. The value of this resistor determines the tPGDELAY and tPGSG. T2P Pin Response The T2P pin outputs high impedance to VCC, low impedance to VCC, 50% duty cycle, or 25% duty cycle, responsive to the number of class/mark event and responsive to Table1. Single-Signature Classification, Power Levels and Resistor Selection PD REQUESTED CLASS 0 1 2 3 4 5 6 7 8 PD REQUESTED POWER 13W 3.84W 6.49W 13W 25.5W 40W 51W 62W 71.3W PD TYPE Type 1 Type 1 or 3 Type 1 or 3 Type 1 or 3 Type 2 or 3 Type 3 Type 3 Type 4 Type 4 NOMINAL CLASS CURRENT 2.5mA 10.5mA 18.5mA 28mA 40mA 40mA/2.5mA 40mA/10.5mA 40mA/18.5mA 40mA/28mA RESISTOR (1%) RCLS RCLS++ 1.00k Open 150 Open 80.6 Open 52.3 Open 35.7 Open 1.00k 37.4 150 47.5 80.6 64.9 52.3 118 Rev. B 8 For more information www.analog.com LT4295 APPLICATIONS INFORMATION PoE or auxiliary power operation. See T2P Output section in the Applications Information. POWER ON VHSON VHSOFF VCC Is Powered by Internally Driven Buck Regulator 1ST CLASS VPORT The LT4295 includes a buck regulator controller that must be used to generate the VCC supply voltage. VCLASSMIN VMARKMAX POE MODES OF OPERATION The LT4295 has several modes of operation, depending on the input voltage sequence applied to the VPORT pin. During detection, the PSE looks for a 25k detection signature resistor which identifies the device as a PD. The LT4295 detection signature resistor is smaller than 25k to compensate for the additional series resistance introduced by the IEEE required diode bridge or the LT4321based ideal diode bridge. IEEE 802.3bt Single-Signature vs Dual-Signature PDs IEEE 802.3bt defines two PD topologies: single-signature and dual-signature. The LT4295 primarily targets single-signature PD topologies, eliminating the need for a second PD controller. All PD descriptions and IEEE 802.3 standard references in this data sheet are limited in scope to single-signature PDs. The LT4295 may be deployed in dual-signature PD applications. For more information, contact Analog Devices Applications. Classification Signature and Mark The class/mark process varies depending on the PSE type. A PSE, after a successful detection, may apply a classification probe voltage of 15.5V to 20.5V and measure the PD classification signature current. Once the PSE applies a classification probe voltage, the PSE returns the PD voltage into the mark voltage range before applying another classification probe voltage, or powering up the PD. An example of 1-Event classification is shown in Figure2. In 2-Event classification, a PSE probes for power classification twice as shown in Figure3. An IEEE 802.3bt PSE may apply as many as 5 events before powering up the PD. 1ST MARK VRESET VSIGMIN 4295 F02 Figure2. Type 3 or Type 4 PSE, 1-Event Class Sequence POWER ON VHSON VHSOFF 1ST CLASS 2ND CLASS VPORT Detection Signature DETECT VCLASSMIN VMARKMAX VRESET VSIGMIN DETECT 1ST MARK 2ND MARK 4295 F03 Figure3. Type 2 PSE, 2-Event Class Sequence IEEE 802.3bt Physical Classification and Demotion IEEE 802.3bt defines physical classification to allow a PD to request a power allocation from the connected PSE and to allow the PSE to inform the PD of the PSE's available power. Demotion is provided if the PD Requested Power level is not available at the PSE. If demoted, the PD must operate in a lower power state. IEEE 802.3bt provides nine PD classes and four PD types, as shown in Table1. The LT4295 class is configured by setting the RCLS and RCLS++ resistor values. The number of class/mark events issued by the PSE directly indicates the power allocated to the PD and is summarized in Table2. Rev. B For more information www.analog.com 9 LT4295 APPLICATIONS INFORMATION PD REQUESTED CLASS NUMBER OF PSE CLASS/MARK EVENTS 1 2 3 4 0 13W 1 3.84W 2 6.49W 3 13W 5 4 13W 5 13W 25.5W 40W 6 13W 25.5W 51W 7 13W 25.5W 51W 62W 8 13W 25.5W 51W 71.3W 25.5W Note: Bold indicates the PD has been demoted. IEEE 802.3bt PSEs present a single classification event (see Figure 2) to Class 0 through 3 PDs. A Class 0 through3 PD presents its class signature to the PSE and is then powered on if sufficient power is available. Power limited IEEE 802.3bt PSEs may issue a single event to Class 4 and higher PDs in order to demote those PDs to Class 3 (13W). IEEE 802.3bt PSEs present up to three classification events depending on type to Class 4 PDs (see Figure4). Class 4 PDs present a class signature 4 on all events. This third event differentiates a Class 4 PD from a higher class PD. Power limited IEEE 802.3bt PSEs may issue three events to Class 5 and higher PDs in order to demote those PDs to Class 4 (25.5W). POWER ON IEEE 802.3bt PSEs present four classification events (see Figure5) to Class 5 and 6 PDs. Class 5 and 6 PDs present a class signature 4 on the first two events. Class 5 and 6 PDs present a class signature 0 or 1, respectively, on the remaining events. Power limited IEEE 802.3bt PSEs may issue four events to Class 7 and higher PDs in order to demote those PDs to Class 6 (51W). IEEE 802.3bt PSEs present five classification events (see Figure6) to Class 7 and 8 PDs. Class 7 and 8 PDs present a class signature 4 on the first two events. Class 7 and 8 PDs present a class signature 2 or 3 respectively, on the remaining events. The PD must monitor the number of classification/mark events, which is communicated through the LT4295 T2Ppin. POWER ON VHSON VHSOFF 1ST CLASS 2ND CLASS 3RD CLASS 4TH CLASS VCLASSMIN VPORT Table2. PSE Allocated Power VMARKMAX DETECT 1ST MARK VRESET 2ND MARK 3RD MARK 4TH MARK VSIGMIN 4295 F05 Figure5. Type 3 or Type 4 PSE, 4-Event Class Sequence POWER ON VHSON VHSOFF VHSON VHSOFF 1ST CLASS VCLASSMIN VMARKMAX VRESET VSIGMIN VPORT VPORT 1ST CLASS 2ND CLASS 3RD CLASS DETECT 1ST MARK 2ND CLASS 3RD CLASS 4TH CLASS 5TH CLASS VCLASSMIN VMARKMAX 2ND MARK 3RD MARK DETECT VRESET 4295 F04 Figure4. Type 3 or Type 4 PSE, 3-Event Class Sequence 1ST MARK 2ND MARK 3RD MARK 4TH MARK VSIGMIN 5TH MARK 4295 F06 Figure6. Type 4 PSE, 5-Event Class Sequence Rev. B 10 For more information www.analog.com LT4295 APPLICATIONS INFORMATION Classification Resistors (RCLS and RCLS++) The RCLS and RCLS++ resistors set the classification currents corresponding to the PD power classification. Select the value of RCLS and RCLS++ from Table1 and connect the 1% resistor between the RCLASS, RCLASS++ pin and GND. Detection Signature Corrupt During Mark Event During the mark event, the LT4295 presents <11k to the port as required by the IEEE 802.3 specification. Inrush and Powered On After the PSE detects and optionally classifies the PD, the PSE then powers on the PD. When the PD port voltage rises above the VHSON threshold, it begins to source IGPU out of the HSGATE pin. This current flows into an external capacitor CGATE in Figure7 and causes a voltage to ramp up the gate of the external MOSFET. The external MOSFET acts as a source follower and ramps the voltage up on the output bulk capacitor, CPORT, thereby determining the inrush current, IINRUSH. Design IINRUSH to be ~100mA. the switching regulator controller operates after a delay of tSTART. EXTERNAL VCC SUPPLY The external VCC supply must be configured as a buck regulator shown in Figure8. To optimize the buck regulator, use the external component values in Table3 corresponding to the VIN operating range. This buck regulator runs in discontinuous mode with the inductor peak current considerably higher than average load current on VCC. Thus, the saturation current rating of the inductor must exceed the values shown in Table3. Place the capacitor, C, as close as possible to VCC pin 21 and GND pin 19. For optimal performance, place these components as close as possible to the LT4295. VIN VIN Re SWVCC LT4295 D IINRUSH + VPORT 3.3k IGPU VCC GND CPORT CGATE VPORT L VCC C 4276 F08 Figure8. VCC Buck Regulator HSGATE C IINRUSH =IGPU * PORT CGATE FMMT723 PBSS9110T HSSRC Table3. Buck Regulator Component Selection VIN 9V-57V PoE LT4295 GND C 22F 10F L ISAT Re 1 22H 1.2A 100H 300mA 20 D Schottky Ultrafast Diode 4276 F07 AUXILIARY SUPPLY OVERRIDE Figure7. Programming IINRUSH The LT4295 internal charge pump enables an N-channel MOSFET solution, replacing a larger and more costly P-channel FET. The low RDS(ON) MOSFET also maximizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. DELAY START After the HSGATE charges up to approximately 7V above HSSRC, fully enhancing the external hot swap MOSFET, If the AUX pin is held above VAUXT, the LT4295 enters auxiliary power operation. In this mode the detection signature resistor is disconnected, classification is disabled, and HSGATE is pulled down. The AUX pin allows for setting the auxiliary supply turn on (VAUXON) and turn off (VAUXOFF) voltage thresholds. The auxiliary supply hysteresis voltage, VAUXHYS, is set by sinking current, IAUXH, only when the AUX pin voltage is less than VAUXT. Use the following equations to set Rev. B For more information www.analog.com 11 LT4295 APPLICATIONS INFORMATION VAUXON and VAUXOFF via R1 and R2 in Figure9. Note that an internal 6.5V Zener limits the voltage on the AUX pin. A capacitor up to 1000pF may be placed between the AUX pin and GND to improve noise immunity. VAUXON must be lower than VHSOFF. VAUXON - VAUXOFF VAUXHYS = IAUXH IAUXH R1= R2 = R1 + R1 LT4295 R1 VAUXOFF - 1 V AUXT VAUX AUX R2 VAUX(MAX) - VAUXT - 1.4mA GND 4295 F09 Figure9. AUX Threshold and Hysteresis Calculation T2P Output The LT4295 communicates the PSE allocated power to the PD application via the T2P pin. The T2P pin state is determined by the AUX pin, the RCLASS++ pin, and the number of classification events. The LT4295 uses a 4-state encoding for the T2P output. T2P state and the associated PSE allocated power are shown in Table4. The highest priority input is the AUX pin. AUX is asserted to enter the auxiliary power state and deasserted to enter the PoE state. In the auxiliary power state, the T2P pin indicates the highest available power, based on PD Requested Class. The auxiliary power supply must be sized to provide at least the PD Requested Power. Second, PD Requested Class and PD Requested Power are configured using the RCLASS and RCLASS++ pins. The RCLASS++ pin alone can be used to determine if the PD Class is 0-4 or 5-8, as shown in Table1. Last, the number of classification events determines the amount of power allocated by the PSE as described inTable2. Table4. T2P Response to Determine PSE Allocated Power STATE Auxiliary PD REQUESTED CLASS 0-4 5-8 0-4 PoE 5-8 NUMBER OF CLASSIFICATION EVENTS N/A N/A T2P* Low-Z 25% 1 Hi-Z 2 1 2 or 3 Low-Z Hi-Z Low-Z 4 50% 5 25% PSE ALLOCATED POWER Aux. Power Aux. Power Min (PD Requested Power, 13W) 25.5W 13W 25.5W Min (PD Requested Power, 51W) Min (PD Requested Power, 71.3W) * Specified as the percentage of the period which T2P is low impedance with respect to VCC. Rev. B 12 For more information www.analog.com LT4295 Interoperability Across Various PSEs and Auxiliary Power Source SWITCHING REGULATOR CONTROLLER OPERATION Table5 summarizes the expected T2P response, the PSE allocated power, and the number of classification events. The result is a function of PD Requested Class and power source--Auxiliary or PoE. The switching regulator controller portion of the LT4295 is a current mode controller capable of implementing either a flyback or a forward power supply. When used in flyback mode, no opto-isolator is required for feedback because the output voltage is sensed via the transformer's third winding. Table5. LT4295 Interoperability {T2P Response*, PSE Allocated Power, Number of Classification Events} PD REQUESTED CLASS (PD REQUESTED POWER) Class 0-3 (up to 13W) Class 4 (25.5W) Class 5 (40W) Class 6 (51W) Class 7 (62W) Class 8 (71.3W) PSE TYPE, CLASS (POWER) IEEE IEEE IEEE 802.3 IEEE 802.3 802.3 802.3 Type 3 Type 4 Type 1 Type 2 Class 3 Class 4 Class 4 Class 5 Class 6 Class 7 Class 8 (13W) (25.5W) (25.5W) (40W) (51W) (62W) (71.3W) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z up to 13W up to 13W up to 13W up to 13W up to 13W up to 13W up to 13W 1-Event 1-Event 1-Event 1-Event 1-Event 1-Event 1-Event Hi-Z Low-Z Low-Z Low-Z Low-Z Low-Z Low-Z 13W 25.5W 25.5W 25.5W 25.5W 25.5W 25.5W 1-Event 2-Event 3-Event 3-Event 3-Event 3-Event 3-Event Hi-Z Low-Z Low-Z 50% 50% 50% 50% 13W 25.5W 25.5W 40W 40W 40W 40W 1-Event 2-Event 3-Event 4-Event 4-Event 4-Event 4-Event Hi-Z Low-Z Low-Z Low-Z 50% 50% 50% 13W 25.5W 25.5W 25.5W 51W 51W 51W 1-Event 2-Event 3-Event 3-Event 4-Event 4-Event 4-Event Hi-Z Low-Z Low-Z Low-Z 50% 25% 25% 13W 25.5W 25.5W 25.5W 51W 62W 62W 1-Event 2-Event 3-Event 3-Event 4-Event 5-Event 5-Event Hi-Z Low-Z Low-Z Low-Z 50% 50% 25% 13W 25.5W 25.5W 25.5W 51W 51W 71.3W 1-Event 2-Event 3-Event 3-Event 4-Event 4-Event 5-Event AUXILIARY POWER SOURCE** Low-Z Aux. Power N/A Low-Z Aux. Power N/A 25% Aux. Power N/A 25% Aux. Power N/A 25% Aux. Power N/A 25% Aux. Power N/A Note 1. Shade of blue indicates the PD has been demoted * Specified as the percentage of the period which T2P is low impedance with respect to VCC ** Auxiliary Power Supply must be sized to provide PD Requested Power T2P Response* PSE Allocated Power Number of Classification Events 25% 71.3W 5-Event Rev. B For more information www.analog.com 13 LT4295 APPLICATIONS INFORMATION Flyback Mode Forward Mode The LT4295 is programmed into flyback mode by placing a resistor RFFSDLY from the FFSDLY pin to GND. This resistor must be in the range of 5.23k to 52.3k. If using a potentiometer to adjust RFFSDLY, ensure the adjustment of the potentiometer does not exceed 52.3k.The value of RFFSDLY determines tPGDELAY according to the following equations: The LT4295 is programmed into forward mode by placing a resistor RFFSDLY from the FFSDLY pin to VCC. The RFFSDLY resistor must be in the range of 10.5k to 52.3k. If using a potentiometer to adjust RFFSDLY ensure the adjustment of the potentiometer does not exceed 52.3k. tPGDELAY 2.69ns / k * RFFSDLY + 30ns The value of RFFSDLY determines tPGDELAY and tPGSG according to the following equations: tPGDELAY 7.16ns/k * RFFSDLY + 17ns tPGSG 20ns tPGSG 5.60ns/k * RFFSDLY + 7.9ns The SG pin must be connected to the secondary side MOSFET through a gate drive transformer as shown in Figure11. Add a Schottky diode from PG to GND as shown in Figure11 to prevent PG from going negative. tPGon PG tPGDELAY The PG and SG relationships in forward mode are shown in Figure12. In forward mode, the SG pin has the correct polarity to drive the active clamp P-channel MOSFET through a simple level shifter as shown in Figure13. Add a Schottky diode from the PG to GND as shown in Figure13 to prevent PG from going negative. tPGSG SG PG 4295 F10 Figure10. PG and SG Timing Relationship in Flyback Mode SG tPGDELAY * tPGSG 4295 F12 + Figure12. PG and SG Timing Relationship in Forward Mode * PG LT4295 VCC * RFFSDLY VCC ISEN- GND * ISEN+ FFSDLY PG FFSDLY SG RFFSDLY * * LT4295 ISEN+ ISEN- 4295 F11 GND Figure11. Example PG and SG Connections in Flyback Mode SG 4295 F13 Figure13. Example PG and SG Connections in Forward Mode Rev. B 14 For more information www.analog.com LT4295 APPLICATIONS INFORMATION Feedback Amplifier FEEDBACK AMPLIFIER OUTPUT, ITHB In the flyback mode, the feedback amplifier senses the output voltage through the transformer's third winding as shown in Figure14. The amplifier is enabled only during the fixed interval, tFB, as shown in Figure15. This eliminates the opto-isolator in isolated designs, thus greatly improving the dynamic response and stability over lifetime. Since tFB is a fixed interval, the time-averaged transconductance, gm, varies as a function of the user-selected switching frequency. As shown in the Block Diagram, VSENSE is the input of the Current Sense Comparator. VSENSE is derived from the output of a linear amplifier whose input is the voltage on the ITHB pin, VITHB. RFB1 FB31 VFB RFB2 + - ITHB VIN * AV = 10 + - VOUT * PRIMARY PG + - THIRD LT4295 FEEDBACK SECONDARY * ISEN+ ISEN- RSENSE 4295 F14 Figure14. Feedback and Load Compensation Connection FB31 VOLTAGE VSENSE -1 VITHB = VITHB(OS) + VSENSE * VITHB The block diagram shows VSENSE is compared against the voltage across the current sense resistor, V(ISEN+)V(ISEN-) modified by the internal slope compensation voltage discussed subsequently. LOAD COMPENSATION RLDCMP RLDCMP This linear amplifier inverts its input, VITHB, with a gain, VSENSE/VITHB, and with an offset voltage of VITHB(OS) to yield its output, VSENSE. This relationship is shown graphically in Figure1. Note the slope VSENSE/VITHB is a negative number and is provided in the electrical characteristics table. VFB GND PG As can be seen in Figure15, the voltage on the FB31 pin droops slightly during the flyback period. This is mostly caused by resistances of components of the secondary side such as: the secondary winding, RDS(ON) of the synchronous MOSFET, ESR of the output capacitor, etc. These resistances cause a feedback error that is proportional to the current in the secondary loop at the time of feedback sample window. To compensate for this error, the LT4295 places a voltage proportional to the peak current in the primary winding on the RLDCMP pin. Determining Feedback and Load Compensation Resistors SG 4295 F15 tFBDLY tFB Figure15. Feedback Amplifier Timing Diagram Because the resistances of components on the secondary side are generally not well known, an empirical method must be used to determine the feedback and load compensation resistor values. INITIALLY SET RFB2 = 2k RFB1 RFB2 VOUT NTHIRD - RFB2 VFB NSECONDARY Rev. B For more information www.analog.com 15 LT4295 APPLICATIONS INFORMATION Connect the resistor RLDCMP between the RLDCMP pin and GND. RLDCMP must be at least 10k. Adjust RLDCMP for minimum change of VOUT over the full input and output load range. A potentiometer in series with 10k may be initially used for RLDCMP and adjusted. The potentiometer+10k may then be removed, measured, and replaced with the equivalent fixed resistor. The resulting VOUT differs from the desired VOUT due to offset injected by load compensation. The change to RFB2 to correct this is predicted by: RFB2 = VOUT NTHIRD RFB22 VFB NSECONDARY RFB1 In PoE applications, a proper soft-start design is required to prevent the PD from drawing more current than the PSE can provide. The soft-start time, tSFST, is approximately the time in which the power supply output voltage, VOUT, is charging its output capacitance, COUT. This results in an inrush current at the port of the PD, Iport_inrush (not to be confused with IINRUSH discussed earlier in Applications Information section). Care must be taken in selecting tSFST to prevent the PD from drawing more current than the PSE can provide. In the absence of an output load current, the Iport_inrush, is approximated by the following equation: Where: VOUT is the desired change to VOUT RFB2 is the required change to RFB2 SOFT-START NTHIRD/NSECONDARY is the transformer third winding to secondary winding C *V 2 Iport_inrush OUT OUT * tSFST * VIN where is the power supply efficiency, OPTO-ISOLATOR FEEDBACK For forward mode operation, the flyback voltage cannot be sensed across the transformer. Thus, opto-isolator feedback must be used. When using opto-isolator feedback, connect the FB31 pin to GND and leave the RLDCMP pin open. In this condition, the feedback amplifier sinks an average current of ISINK into the ITHB pin. An example for feedback connections is shown in Figure16. Note that since ISINK is time-averaged over the switching period, the sink current varies as a function of the user-selected switching frequency. VOUT VCC VIN is the input voltage of the PD Iport_inrush plus the port current due to the load current must be below the current the PSE can provide. Note that the PSE current capability depends on the PSE operating standard. The LT4295 contains a soft-start function that controls tSFST by connecting an external capacitor, CSFST, between the SFST pin and GND. The SFST pin is pulled up with ISFST when the LT4295 begins switching. The voltage ramp on the SFST pin is proportional to the duty cycle ramp for PG. For flyback mode, the soft-start time is: LT4295 ITHB GND RX CX FB31 4295 F16 Figure16. Opto-isolator Feedback Connections in the Forward Mode tSFST = 600A CSFST ( tPGon + tPGDELAY - tMIN ) nF ISFST where tPGon is the time when PG is high as shown in Figure8 once the power supply is in steady-state. In forward mode, each of the back page applications schematics provides a chart with tSFST vs. CSFST. Select the application and choose a value of CSFST that corresponds to the desired soft-start time. Rev. B 16 For more information www.analog.com LT4295 APPLICATIONS INFORMATION CURRENT SENSE COMPARATOR SHORT CIRCUIT RESPONSE The LT4295 uses a differential current sense comparator to reduce the effects of stray resistance and inductance on the measurement of the primary current. ISEN+ and ISEN- must be Kelvin connected to the sense resistor pads. If the power supply output voltage is shorted, overloaded, or if the soft-start capacitor is too small, an overcurrent fault event occurs when the voltage across the sense pins exceeds VFAULT (after the blanking period of tMIN). This begins the internal fault timer tFAULT. For the duration of tFAULT, the LT4295 turns off PG and SG and pulls the SFST pin to GND. After tFAULT expires, the LT4295 initiates soft-start. Like most switching regulator controllers, the current sense comparator begins sensing the current tMIN after PG turns on. Then, the comparator turns PG off after the voltage across ISEN+ and ISEN- exceeds the current sense comparator threshold, VSENSE. Note that the voltage across ISEN+ and ISEN- is modified by LT4295's internal slope compensation. The fault and soft-start sequence repeats as long as the short circuit or overload conditions persist. This condition is recognized by the PG waveform shown in Figure17 repeating at an interval of tFAULT. SLOPE COMPENSATION The LT4295 incorporates current slope compensation. Slope compensation is required to ensure current loop stability when the duty cycle is greater than or near 50%. The slope compensation of the LT4295 does not reduce the maximum peak current at higher duty cycles. CONTROL LOOP COMPENSATION In flyback mode, loop frequency compensation is performed by connecting a resistor/capacitor network from the output of the feedback amplifier (ITHB pin) to GND as shown in Figure14. In forward mode, loop compensation is performed by varying RX and CX in Figure16. ADJUSTABLE SWITCHING FREQUENCY The LT4295 has a default switching frequency, fOSC, of 214 kHz when the ROSC pin is left open. If a higher switching frequency, fSW, is desired (up to 300kHz), a resistor no smaller than 45.3k may be added between the ROSC pin to GND. The resistor can be calculated below: ROSC = tFAULT 4295 F17 Figure17. PG Waveforms with Output Shorted OVERTEMPERATURE PROTECTION The IEEE 802.3 specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. During classification, however, the power dissipation in the LT4295 may be as high as 1.5W. The LT4295 can easily tolerate this power for the maximum IEEE classification timing but overheats if this condition persists abnormally. The LT4295 includes an overtemperature protection feature which is intended to protect the device during momentary overload conditions. If the junction temperature exceeds the overtemperature threshold, the LT4295 pulls down HSGATE pin, disables classification, and disables the switching regulator operation. 3900k * kHz (k) ( fSW - fOSC ) Rev. B For more information www.analog.com 17 LT4295 APPLICATIONS INFORMATION MAXIMUM DUTY CYCLE The maximum duty cycle of the PG pin is modified by the chosen tPGDELAY and fSW. It is calculated below: MAX POWER SUPPLY DUTY CYCLE = DMAX - tPGDELAY * fSW For an appropriate margin during transient operation, the forward or flyback power supply should be designed so that its maximum steady-state duty cycle should be about 10% lower than the LT4295 Maximum Power Supply Duty Cycle calculated above. EXTERNAL INTERFACE AND COMPONENT SELECTION PoE Input Bridge A PD is required to polarity-correct its input voltage. There are several different options available for bridge rectifiers; silicon diodes, Schottky diodes, and ideal diodes. When silicon or Schottky diode bridges are used, the diode forward voltage drops affect the voltage at the VPORT pin. The LT4295 is designed to tolerate these voltage drops. Note, the voltage parameters shown in the Electrical Characteristics section are specified at the LT4295 package pins. A silicon diode bridge consumes up to 4% of the available power. In addition, silicon diode bridges exhibit poor pairset-to-pairset unbalance performance. Each branch of a silicon diode bridge shares source/return current, and thermal runaway can cause large, non-compliant current unbalances between pairsets. While using Schottky diodes can help reduce the power loss with a lower forward voltage, the Schottky bridge may not be suitable for high temperature PD applications. Schottky diode bridges exhibit temperature induced leakage currents. The leakage current has a voltage dependency that can invalidate the measured detection signature. In addition, these leakage currents can back-feed through the unpowered branch and the unused bridge, violating IEEE 802.3 specifications. For high efficiency applications, the LT4295 supports an LT4321-based PoE ideal diode bridge that reduces the forward voltage drop from 0.7V to 20mV per diode while maintaining IEEE 802.3 compliance. The LT4321 simplifies thermal design, eliminates costly heatsinks, and can operate in space-constrained applications. Rev. B 18 For more information www.analog.com LT4295 APPLICATIONS INFORMATION Auxiliary Input Diode Bridge Input Capacitor Some PDs are required to receive AC or DC power from an auxiliary power source. A diode bridge is typically required to handle the voltage rectification and polarity correction. A 0.1F capacitor is needed from VPORT to GND to meet the input impedance requirement in IEEE 802.3 and to properly bypass the LT4295. When operating with the LT4321, locally bypass each with a 0.047F capacitor, thus keeping the total port capacitance within specification. In high efficiency applications, or in low auxiliary input voltage applications, the voltage drop across the rectifier cannot be tolerated. The LT4295 can be configured with an LT4320-based ideal diode bridge to recover the diode voltage drop and ease thermal design. For applications with auxiliary input voltages below 10V, the LT4295 must be configured with an LT4320-based ideal diode bridge to recover the voltage drop and guarantee the minimum VPORT voltage is within the VPORT AUX range as specified in the Electrical Characteristics table. Transient Voltage Suppressor The LT4295 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events due to Ethernet cable surges. To protect the LT4295 from an overvoltage event, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ58A between the VPORT and GND pins. For PD applications that require an auxiliary power input, install a TVS between VIN and GND. For extremely high cable discharge and surge protection, contact Analog Devices Applications. Rev. B For more information www.analog.com 19 LT4295 TYPICAL APPLICATIONS 13W PoE Power Supply in Flyback Mode with 5V, 2.3A Output L2 10H Q1 VPORT L1: COILCRAFT, DO1813P-181HC L2: COILCRAFT, DO1608C-103 L4: COILCRAFT, DO1608C-104 C2: 22F, 6.3V, MURATA GRM31CR70J226KE19 C5: 47F, 6.3V, PANASONIC 6SVP47M C7: 2.2F, 100V, MURATA GRM32ER72A225KA35 T1: WURTH, 750313109 Q1: PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL + C7 2.2F 10F 100V * L1 180nH 3.3k 10nF 100V L4 100H * 47pF 630V 270 1/4W 20 FMMT723 6.04k C5 47F 6.3V * VIN SWVCC VCC FB31 PG FDN86246 11 1/4W BAT54WS VPORT PSMN4R2-30MLD 1nF ISEN+ LT4295 60m 1/4W - MMBT3906 ISEN 0.1F 100V PTVS58VP1UTP GND RCLASS FFSDLY 52.3 SFST ROSC 5.23k 100 ITHB * * 10k BAT46WS 4.7nF 330pF 20k GND 2.2nF 2KV 4295 TA02a VOUT vs Load Current Efficiency vs Load Current 92 5.20 90 5.15 88 5.10 86 5.05 VOUT (V) EFFICIENCY (%) 1F 2.2nF T2 1F 107k 0.1F MMBT3904 15 SG 84 82 80 5.00 4.95 4.90 VPORT = 37V VPORT = 48V VPORT = 57V 78 76 +VOUT 5V AT 2.3A -VOUT T1 HSGATE 8.2 C2 22F 2k 10F BAV19WS 10V HSSRC 2.2nF 2kV 0 0.5 1 1.5 LOAD CURRENT (A) 2 VPORT = 37V VPORT = 48V VPORT = 57V 4.85 4.80 2.5 4295 TA02b 0 0.5 1 1.5 LOAD CURRENT (A) 2 2.5 4295 TA02c Rev. B 20 For more information www.analog.com SPARE PAIRS 8 5 7 4 6 2 3 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q4 Q7 Q9 Q6 Q8 LT4321 Q3 Q2 For more information www.analog.com SPARE PAIRS DATA PAIRS 8 5 7 4 6 2 3 1 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q3 Q7 Q9 Q6 Q8 LT4321 Q4 Q2 EN OUTN TG78 BG78 EN OUTP BG36 TG36 L1: COILCRAFT, DO1813P-181HC L2: COILCRAFT, DO1608C-103 L4: COILCRAFT, DO1608C-104 C2, C3: 10F, 16V, MURATA GRM31CR61C106KA88 C5: 33F, 25V, PANASONIC EEHZA1E330R C7: 2.2F, 100V, MURATA GRM32ER72A225KA35 T1: WURTH, 750316115 OR PCA EPC3634G Q1-Q9: PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 7499511001A J1 80 82 84 86 24V 88 90 92 94 EN OUTN TG78 BG78 EN OUTP BG36 TG36 L1: COILCRAFT, DO1813P-181HC L2: COILCRAFT, DO1608C-103 L4: COILCRAFT, DO1608C-104 C2, C3: 10F, 16V, MURATA GRM31CR61C106KA88 C5: 33F, 25V, PANASONIC EEHZA1E330R C7: 2.2F, 100V, MURATA GRM32ER72A225KA35 T1: WURTH, 750316115 OR PCA EPC3634G Q1-Q9: PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 7499511001A J1 0 47nF 100V 47nF 100V 10nF 100V + L2 10H VIN SWVCC 37.4 20 107k 220pF ITHB T2P SG ISEN- ISEN+ VCC FB31 PG 26.1k 3.3nF 1F MOC207M 5.1k 100 BAT54WS T1 * L1 180nH TO MICROPROCESSOR BAT46WS 15 1F -VOUT +VOUT 12V AT 3A 4295 TA03a 3 4295 TA03b 2.5 VPORT = 44V VPORT = 50V VPORT = 57V 10k 10k C5 33F MMBT3904 TPN1600ANH C2, C3 10F MMBT3906 2.2nF 2.2nF VOUT 2KV * T2 * 11 1/2W 470pF * 25m 1/4W 100pF 630V 100 1/2W BSZ90020NS3 2.00k 6.65k 2.2nF 2kV 1 1.5 2 LOAD CURRENT (A) 7.5k 0.1F ROSC 10F 10V FFSDLY SFST LT4295 BAV19WS L4 FMMT723 100H 1.00k GND RCLASS++ RCLASS VPORT HSSRC HSGATE C7 2.2F 0.5 47nF 100V 10F 100V PTVS58VP1UTP 8.2 3.3k Q1 * 47nF 100V 10F 100V PTVS58VP1UTP 8.2 10nF 100V + Efficiency vs Load Current 24V 3.3k Q1 L2 10H VIN SWVCC 11.98 12.00 12.02 12.04 12.06 12.08 12.10 12.12 12.14 37.4 0 220pF ITHB T2P SG ISEN- ISEN+ 0.5 1 1.5 2 LOAD CURRENT (A) 3 4295 TA03c 2.5 3.3nF MOC207M T1 * 4295 TA03a 10k BAT46WS 15 TO MICROPROCESSOR 10k C5 33F MMBT3904 TPN1600ANH C2, C3 10F L1 180nH MMBT3906 2.2nF 2.2nF VOUT 2KV * T2 * 11 1/2W 470pF * * 2.2nF 2kV 25m 1/4W 1F 5.1k 100 BAT54WS 26.1k VPORT = 44V VPORT = 50V VPORT = 57V VOUT vs Load Current 7.5k 107k ROSC 0.1F FFSDLY SFST LT4295 100pF 630V 100 1/2W BSZ90020NS3 2.00k 10F BAV19WS 10V VCC FB31 PG 6.65k L4 FMMT723 100H 20 1.00k GND RCLASS++ RCLASS VPORT HSSRC HSGATE C7 2.2F V(OUT) (V) DATA PAIRS 1 EFFICIENCY (%) 40W PoE Power Supply in Flyback Mode with 12V, 3A Output 1F -VOUT +VOUT 12V AT 3A LT4295 TYPICAL APPLICATIONS Rev. B 21 GND VPORT PTVS58VP1UTP 8.2 10nF 100V 3.3k Q1 For more information www.analog.com 76 78 80 82 84 86 88 90 92 0 20 2 4 6 8 10 LOAD CURRENT (A) 14 4295 TA04b 12 VPORT = 41V VPORT = 50V VPORT = 57V Efficiency vs Load Current 0.47F 107k 118 52.3 SG ISEN- ISEN+ VCC FFSDLY PG 13k VCC ROSC ITHB LT4295 10F 10V BAV19WS FMMT723 L4 100H VIN SWVCC C7 2.2F (x2) GND FB31 RCLASS RCLASS++ SFST T2P VPORT HSGATE HSSRC 22F 100V 0.1F 100V 94 + L2 4.9H 20m 1/2W 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0 100pF 750 * 10nF 250V T1 OPTO 2.2nF 2kV M0C207M VCC 100 1206 100nF 250V * 2 10 10k 330 14 4295 TA04c 12 VPORT = 41V VPORT = 50V VPORT = 57V 10.0k 10.0k 18V CMHZ5248B BSC054N04NS 12 38 3.8 1.0 1.2 0.33 tSFST (ms) 0.10 4295 TA04a CSFST (F) 3.3 L1 2.2H C5 100F (x2) + -VOUT +VOUT +5V AT C8 13A 100F 6HVA100M L1: COILCRAFT, XAL-1010-222ME L2: WURTH, 744314490 L4: COILCRAFT, DO1608C-104 C5, 100F, 6.3V, SUNCON 6HVA100M C7: 2.2F, 100V, MURATA GRM32ER72A225KA35L C8: 100F, 6.3V, SUNCON 6HVA100M T1: WURTH, 750313095 Q1: PSMN040-100MSE 10nF TO MICROPROCESSOR ZR431 4.7n 33nF +VOUT 0.1F 5 CMMSH1-40L 18V CMHZ5248B 240 1k 0.1F 8.2V CMHZ4694 MMBT3904 4 6 8 10 LOAD CURRENT (A) 10 CMMSH1-40L BSC054N04NS CMMSH1-40L VOUT vs Load Current 10k FDMC2523P CMMSH1-40L 100k 0.1F BAT54WS BSC190N12NS3 V(OUT) (V) 22 EFFICIENCY (%) 71.3W PoE Power Supply in Forward Mode with 5V, 13A Output LT4295 TYPICAL APPLICATIONS Rev. B SPARE PAIRS 8 5 7 4 6 2 3 DATA PAIRS 1 T2 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q7 Q9 Q6 Q8 LT4321 Q4 Q3 EN OUTN TG78 BG78 EN OUTP BG36 TG36 47nF 100V PTVS58VP1UTP 8.2 10nF 100V 3.3k + 22F 100V For more information www.analog.com 78 80 82 84 86 88 90 92 94 0 1 5 6 4295 TA05b VPORT = 41V VPORT = 50V VPORT = 57V 2 3 4 LOAD CURRENT (A) LT4295 10F BAV19WS 10V L4 100H 52.3 118 1F ISEN 107k 11.60 11.70 11.80 11.90 12.00 12.10 12.20 12.30 0 100pF 15m 1/2W 33nF 250V OPTO 2.2nF 2kV M0C207M VCC 100 1206 0.22F 250V 750 * CMMSH1-60 * T1 10k 820 1 2 3 4 LOAD CURRENT (A) 5 6 4295 TA05c VPORT = 41V VPORT = 50V VPORT = 57V ZR431 100pF 330pF BSC123N08S3 7.5V CMHZ5236B 5.1k 100pF FMMT624 +VOUT CMMSH1-100 tSFST (ms) 1.5 4.9 15 48 CSFST (F) 0.10 0.33 1.0 3.3 4295 TA05a L1: COILCRAFT, XAL-1010-822ME L2: WURTH, 744314650 L4: COILCRAFT, DO1608C-104 C7: 2.2F, 100V, MURATA GRM32ER72A225KA35L C8: 100F, 16V, SUNCON 16HVA100M T1: PCA EPC3577G-LF T2: WURTH, 749022016 Q1: PSMN040-100MSE Q2-Q9: PSMN075-100MSE FMMT624 +VOUT CMMSH1-100 TO MICROPROCESSOR 10.0k 38.3k +VOUT 0.1F 7.5V CMHZ5236B 5.1k 20k 100pF 6.8nF 0.1F 13V CMHZ4700 13k 7.5 820pF MMBT3904 10 VOUT vs Load Current 100pF 10k FDMC2523P CMMSH1-40L 100k 0.1F 12.40 ITHB SG ISEN- + BAT54WS BSC190N12NS3 29.4k VCC VCC FFSDLY PG GND FB31 RCLASS RCLASS++ SFST ROSC VPORT T2P HSGATE 20 FMMT723 VIN SWVCC C7 2.2F (x2) HSSRC L2 6.5H Efficiency vs Load Current VCC 47nF 100V Q1 V(OUT) (V) Q2 EFFICIENCY (%) 71.3W PoE Power Supply in Forward Mode with 12V, 5.5A Output BSC123N08S3 22F 16V (x2) L1 8.2H -VOUT C8 100F +VOUT +12V AT 5.5A LT4295 TYPICAL APPLICATIONS Rev. B 23 SPARE PAIRS 8 5 7 4 6 2 3 DATA PAIRS 1 J1 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q4 Q7 Q9 Q6 Q8 LT4321 Q3 Q2 EN OUTN TG78 BG78 EN OUTP BG36 TG36 For more information www.analog.com 78 80 82 84 86 88 90 92 94 0 47nF 100V 47nF 100V 10F 100V PTVS58VP1UTP 8.2 10nF 100V + 1 2 3 4 5 LOAD CURRENT (A) 7 4295 TA06b 6 VPORT = 50V VPORT = 57V Efficiency vs Load Current 24V 3.3k Q1 L2 10H VIN SWVCC LT4295 BAV19WS FMMT723 20 37.4 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 7.50k 0 0.1F 220pF 107k 3.3nF 20k 1 2 3 4 5 LOAD CURRENT (A) 7 4295 TA06c 6 VPORT = 50V VPORT = 57V 100 BAT54WS * * 1F T2 OPTO 2.2nF 2KV * * 5.1 1/4W 1nF T1 * 2.2nF 2kV 40m 1/4W 100pF 100V 80 1/4W BSZ900N20 NS3G VOUT vs Load Current 51k ITHB T2P SG ISEN- ISEN+ 2.00k 10F 10V VCC FB31 PG 5.90k L4 100H RCLASS++ FFSDLY SFST RLDCMP ROSC 1.00k RCLASS GND VPORT HSSRC HSGATE C7 2.2F L1: COILCRAFT, DO1813P-181HC L2: COILCRAFT, DO1608C-103 L4: COILCRAFT, DO1608C-104 C2, C3: 47F, 6.3V, GRM31CR60J476ME19L C5: 47F, 6.3V, PANASONIC 6SVP47M C7: 2.2F, 100V, MURATA GRM32ER72A225KA35L T1: WURTH, 750314783 OR PCA EPC3586G Q1-Q9: PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 7499511001A V(OUT) (V) 24 EFFICIENCY (%) 40W PoE Power Supply in Flyback Mode with 5V, 7.3A Output 10k BAT46WS 15 MMBT3904 4295 TA06a 1F -VOUT +VOUT 5V AT 7.3A TO MICROPROCESSOR MMBT3906 2.2nF C5 47F PSMN2R4-30MLD C2, C3 47F||47F L1 180nH LT4295 TYPICAL APPLICATIONS Rev. B For more information www.analog.com SPARE PAIRS 8 5 7 4 6 2 3 DATA PAIRS 1 J1 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 MMSD4148 x3 VAUX 9V TO 57VDC OR 24VAC Q5 Q4 Q7 Q9 Q6 Q8 LT4321 Q3 Q2 72 76 80 84 88 92 0 EN OUTN TG78 BG78 EN OUTP BG36 TG36 EFFICIENCY (%) 47nF 100V OUTN 1F 8.2 + + 0.5 1 1.5 LOAD CURRENT (A) 2 4295 TA07b VAUX = 9V VAUX = 24V VAUX = 42.5V VAUX = 57V 47nF 100V 931k 158k 10F 100V L2 8.2H L3 2.2H 680F 100nF 0.1F 100V 3.3k Q1 PTVS58VP1UTP LT4320 OUTP Efficiency vs Load Current 24V BG1 BG2 IN1 IN2 TG1 TG2 VIN SWVCC LT4295 22F 10V PMEG10010ELR L4 FMMT723 22H 1 35.7 11.50 11.75 12.00 12.25 12.50 0.1F 9.31k 0 220pF 107k ITHB T2P SG ISEN- ISEN+ VCC FB31 PG 4.7nF 43k 100 0.5 1 1.5 LOAD CURRENT (A) 4295 TA07c 2 VAUX = 9V VAUX = 24V VAUX = 42.5V VAUX = 57V T1 * 220pF * * 2.2nF 2kV T2 * OPTO 2.2nF 2KV * 15m 1/2W 82||82 1/4W 1F FDMC86160 100pF 100V 62 1/4W BAT54WS 2.00k 4.75k VOUT vs Load Current 51k GND RCLASS FFSDLY SFST RLDCMP ROSC VPORT AUX HSSRC HSGATE C7, C8 3.3F L1: COILCRAFT, DO1813P-561ML L2: WURTH, 7443330820 L3: MURATA, LQM21PN2R2NGCD L4: COILCRAFT, DO1813H-223 C2, C3: 10F, 16V, MURATA GRM31CR61C106KA88 C5: 33F, 20V, KEMET, T494V336M020AS C7, C8: 3.3F, 100V, TDK C3225X7S2A335M T1: PCA EPC3601G OR WURTH 750315422 Q1-Q9:PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 7499511611A V(OUT) (V) BSZ110N06NS3 x4 C5 33F 10k 4295 TA07a 1F -VOUT +VOUT 12V AT 1.9A TO MICROPROCESSOR BAT46WS 15 CMLT3820G BSZ900NF20NS3 C2, C3 10F||10F L1 560nH CMLT7820G 2.2nF 25.5W PoE and 9V to 57V Auxiliary Input Power Supply in Flyback Mode with 12V, 1.9A Output LT4295 TYPICAL APPLICATIONS Rev. B 25 SPARE PAIRS DATA PAIRS 8 5 7 4 6 2 3 1 J1 For more information www.analog.com 78 80 82 84 86 88 90 92 0 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q4 Q9 Q8 EN OUTN TG78 BG78 EN OUTP BG36 TG36 24V 2 4 6 LOAD CURRENT (A) 8 4295 TA08b VPORT = 42.5V VPORT = 50V VPORT = 57V Efficiency vs Load Current Q7 Q6 LT4321 Q3 Q2 47nF 100V 3.20 3.30 3.40 3.50 0 0.1F 107k ROSC 470pF ITHB T2P 2 SG ISEN - ISEN+ VCC FB31 PG 4 6 LOAD CURRENT (A) 4295 TA08c 8 2k 4.7nF 8.25k 100 BAT54WS * * 1F T2 * 5.1 1/4W OPTO 2.2nF 2KV * * 1nF T1 2.2nF 2kV 40m 1/4W 100pF 100V 100 1/4W BSZ900N20NS3 6.49k VPORT = 42.5V VPORT = 50V VPORT = 57V VOUT vs Load Current SFST LT4295 6.81k FFSDLY 35.7 GND RCLASS VPORT L4 100H 10F BAV19WS 10V FMMT723 20 L1: COILCRAFT, DO1813P-181HC L2: COILCRAFT, DO1608C-103 L4: COILCRAFT, DO1608C-104 C2, C3: 22F, 6.3V, MURATA GRM31CR70J226KE19 C5: 68F, 4V, 4SVPA68MAA C7: 2.2F, 100V, MURATA GRM32ER72A225KA35 T1: WURTH, 750310743 OR PCA EPC3408G Q1-Q9: PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 7499511001A VIN SWVCC C7 2.2F HSSRC HSGATE 47nF 100V 10F 100V PTVS58VP1UTP 8.2 + 10nF 100V 3.3k Q1 L2 10H V(OUT) (V) 26 EFFICIENCY (%) 25.5W PoE Power Supply in Flyback Mode with 3.3V, 6.8A Output 10k BAT46WS 15 MMBT3904 4295 TA08a 1F -VOUT +VOUT 3.3V AT 6.8A TO MICROPROCESSOR MMBT3906 2.2nF 47 C5 68F PSMN2R4-30MLD B0540WS C2, C3 22F||22F L1 180nH LT4295 TYPICAL APPLICATIONS Rev. B SPARE PAIRS 8 5 7 4 6 2 3 J1 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q4 For more information www.analog.com 80 82 84 86 88 90 EN OUTN TG78 BG78 EN OUTP BG36 TG36 24V 0.2 0.4 0.6 LOAD CURRENT (A) 0.8 4295 TA09b VPORT = 42.5V VPORT = 50V VPORT = 57V 1 47nF 100V Efficiency vs Load Current Q9 Q8 92 Q7 Q6 0 LT4321 Q3 Q2 23.4 23.6 23.8 24.0 24.2 24.4 24.6 0 10pF 107k 0.2 0.4 0.6 LOAD CURRENT (A) 0.8 1 4295 TA09c VPORT = 42.5V VPORT = 50V VPORT = 57V VOUT vs Load Current 0.47F 24k ITHB T2P SG ISEN- ISEN+ 100 1/4W 47pF 100V 160k 3.3nF 100 BAT54WS * 150pF T1 * OPTO 2.2nF 2KV * T2 C5 22F 10k 4295 TA09a 0.1F -VOUT 24V AT 0.95A +VOUT TO MICROPROCESSOR BAT46WS 15 MMBT3904 BSZ12DN20NS3 C2, C3 4.7F 50V MMBT3906 2.2nF 120||120 1/4W * * 2.2nF 2kV 40m 1/4W 1F BSZ520N15NS3G 2.00k 10F 10V VCC FB31 PG 6.49k L4 100H SFST RLDCMP ROSC 5.23k FFSDLY 35.7 GND RCLASS VPORT LT4295 BAV19WS FMMT723 20 L2: COILCRAFT, DO1608C-103 L4: COILCRAFT, DO1608C-104 C2: 4.7F, 50V, MURATA GRM31CR71H475KA12 C5: 22F, 35V, PANASONIC EEH-ZA1V220R C7: 2.2F, 100V, MURATA GRM32ER72A225KA35 T1: WURTH, 750314782 OR PCA EPC3603G Q1-Q9: PSMN075-100MSE T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 7499511001 VIN SWVCC C7 2.2F HSSRC HSGATE 47nF 100V 10F 100V PTVS58VP1UTP 8.2 + 10nF 100V 3.3k Q1 L2 10H V(OUT) (V) DATA PAIRS 1 EFFICIENCY (%) 25.5W PoE Power Supply in Flyback Mode with 24V, 0.95A Output LT4295 TYPICAL APPLICATIONS Rev. B 27 SPARE PAIRS 8 5 7 4 6 2 3 DATA PAIRS 1 J1 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q3 Q8 Q6 For more information www.analog.com 80 82 84 86 88 90 92 94 Q9 Q7 LT4321 Q4 Q2 0 24V 47nF 100V 0.5 3 4295 TA10b 2.5 C7, C8 2.2F 24.0 24.1 24.2 24.3 24.4 24.5 64.9 0 0.47F 5.23k 36k 330pF 107k SFST RLDCMP ROSC 0.5 1 1.5 2 LOAD CURRENT (A) 3 4295 TA10c 2.5 VPORT = 41V VPORT = 50V VPORT = 57V ITHB T2P SG ISEN- ISEN+ 27 1/2W 22k 10nF 100 BAT54WS * * 1F T2 * OPTO C5 47F 10k 4295 TA10a 0.1F -VOUT 24V AT 2.4A +VOUT TO MICROPROCESSOR BAT46WS 15 PBSS4140T BSC320N20NS3 C2 10F 50V L1 1.2H PBSS5140T 2.2nF 18 1W 2.2nF 2KV * * 330pF T1 4.7nF 2kV 15m 1/2W 220pF 100V BSC190N15NS3 2.00k 10F 10V VCC FB31 PG 3.74k L4 100H VOUT vs Load Current 80.6 FFSDLY LT4295 VIN SWVCC BAV19WS FMMT723 20 L1: COILCRAFT, DO1813H-122ML L2: WURTH, 744314490 L4: COILCRAFT, DO1608C-104 C2: MURATA GRM32ER61H106K C5: 47F, 35V, EEE-FT1V470AR C7, C8: 2.2F, 100V, MURATA GRM32ER72A225KA35 Q1: NXP PSMN040-100MSE Q2-Q9: PSMN075-100MSE T1: PCA EPC3630G OR WURTH 750316231 T2: PCA EPA4271GE OR PULSE PE-68386NL J1: WURTH 749022016 GND RCLASS++ RCLASS VPORT HSSRC HSGATE 47nF 100V 22F 100V PTVS58VP1UTP VPORT = 41V VPORT = 50V VPORT = 57V 1 1.5 2 LOAD CURRENT (A) + 10nF 100V 3.3k 8.2 Efficiency vs Load Current EN OUTN TG78 BG78 EN OUTP BG36 TG36 Q1 L2 4.9H V(OUT) (V) 28 EFFICIENCY (%) 62W PoE Power Supply in Flyback Mode with 24V, 2.4A Output LT4295 TYPICAL APPLICATIONS Rev. B SPARE PAIRS 8 5 7 4 6 2 3 DATA PAIRS 1 T2 BG45 TG45 IN78 IN45 IN36 IN12 TG12 BG12 Q5 Q7 Q9 Q6 Q8 LT4321 Q4 Q3 VCC 47nF 100V 47nF 100V PTVS58VP1UTP 8.2 10nF 100V 3.3k + 22F 100V For more information www.analog.com 80 82 84 86 88 90 92 94 0 0.5 3 4295 TA11b 2.5 VPORT = 41V VPORT = 50V VPORT = 57V 1 1.5 2 LOAD CURRENT (A) LT4295 10F BAV19WS 10V L4 100H 52.3 118 23.0 23.4 23.8 24.2 24.6 0 SG ITHB 15m 1/2W 100pF * 10nF 250V 0.5 1 1.5 2 LOAD CURRENT (A) 4295 TA11c 2.5 VPORT = 41V VPORT = 50V VPORT = 57V 3 OPTO 2.2nF 2kV M0C207M VCC 82 1206 750 10k FDMC2523P CMMSH1-40L 100k 0.1F BAT54WS 47nF 250V * T1 VOUT vs Load Current 107k 25.0 1F ISEN ISEN- + BSC190N12NS3 33k VCC VCC FFSDLY PG GND FB31 RCLASS RCLASS++ SFST ROSC VPORT T2P HSGATE 20 FMMT723 VIN SWVCC C7 2.2F (x2) HSSRC L2 6.5H Efficiency vs Load Current EN OUTN TG78 BG78 EN OUTP BG36 TG36 Q1 V(OUT) (V) Q2 EFFICIENCY (%) 10k 820 ZR431 1nF 6.8nF 47pF 3.3nF 1.4 2.4 4.4 0.22 0.47 3.3 46 15 tSFST (ms) 0.10 1.0 FMMT624 +VOUT SMD1200PL-TP C2 10F 35V L1 22H TPH5900CNH L1: PULSE PA2050.223 L2: WURTH, 744314650 L4: COILCRAFT, DO1608C-104 C1: PANASONIC EEHZA1V470P C2: MURATA GRM32ER6YA106KA12 C7: 2.2F, 100V, MURATA GRM32ER72A225KA35L Q1: PSMN040-100MSE Q2-Q9: PSMN075-100MSE T1: PCA EPC3636G T2: WURTH, 749022016 TPH5900CNH 7.5V CMHZ5236B 13k 47pF CSFST (F) 4295 TA11a FMMT624 +VOUT SMD1200PL-TP TO MICROPROCESSOR 10.0k 86.6k +VOUT +VOUT 7.5V CMHZ5236B 13k 1.2k 10k 0.1F 13V CMHZ4700 MMBT3904 47 220pF 71.3W PoE Power Supply in Forward Mode with 24V, 2.7A Output -VOUT C1 47F 35V +VOUT 24V AT 2.7A LT4295 TYPICAL APPLICATIONS Rev. B 29 LT4295 PACKAGE DESCRIPTION UFD Package 28-Lead Plastic QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1712 Rev C) 0.70 0.05 4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 3.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) R = 0.05 TYP 0.75 0.05 PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 0.10 (2 SIDES) 3.50 REF 3.65 0.10 2.65 0.10 (UFD28) QFN 0816 REV C 0.200 REF 0.00 - 0.05 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. B 30 For more information www.analog.com LT4295 REVISION HISTORY REV DATE DESCRIPTION A 09/18 Updated max input power to 71.3W per Draft 3.4 Revised T2P Output, PoE Input Bridge, Input Capacitor, and Transient Voltage Supressor Applications Information Changed RCLASS and/or RCLASS++ resistor values Added J1 transformer recommendations B 5/19 Removed Draft number Added Table 5-Interoperability PAGE NUMBER 1-30 12, 17 20, 26 19, 22-26, 30 1-30 13 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 31 LT4295 TYPICAL APPLICATION 51W PoE Power Supply in Flyback Mode with 12V, 3.9A Output + Q2 J1 DATA PAIRS 1 Q4 2 3 IN45 4 20 C7, C8 2.2F HSSRC HSGATE BG36 TG36 OUTP LT4321 24V 47nF 100V L4 FMMT723 100H VIN SWVCC VCC FB31 PG Q6 Q7 Q8 Q9 T1 +VOUT 12V AT 3.9A -VOUT TPH1500CNH TPH1500CNH 330pF 20 1/2W BAT54WS 20m 1/2W LT4295 ISEN- VPORT 100 T2P PTVS58VP1UTP 47.5 47nF 100V 5.23k 150 0.1F * * 10k 5.1k 3.3nF 330pF PBSS414OT 2.2nF T2 1F ITHB 107k PBSS514OT 15 SG GND RCLASS++ RCLASS FFSDLY SFST ROSC 8 C5 47F ISEN+ 10nF 100V EN OUTN TG78 BG78 BG45 TG45 2.00k C2, C3 10F * 220pF 630V 36 1/2W 5.62k 3.3k 8.2 IN78 5 7 10F 100V Q5 EN IN36 L1 * 10F BAV19WS 10V IN12 SPARE PAIRS * Q3 TG12 BG12 6 2.2nF 2kV C5: 47F, 35V, PANASONIC EEHZA1V470P C7, C8: 2.2F, 100V, MURATA GRM32ER72A225KA35 T1: WURTH, 750316116 OR PCA EPC3633G T2: PCA EPA4271GE OR PULSE PE-68386NL Q1: PSMN040-100MSE L2 Q2-Q9: PSMN075-100MSE 4.7H Q1 L1: WURTH 744316022 L2: WURTH 744316470 L4: COILCRAFT, DO1608C-104 C2, C3: 10F, 16V, MURATA GRM32DR61C106KA01 J1: WURTH 7499511001A 1F BAT46WS VOUT 30k 2.2nF 2KV 10k TO MICROPROCESSOR Efficiency vs Load Current 94 VOUT vs Load Current 12.02 MOC207M 4295 TA12a 12.01 90 V(OUT) (V) EFFICIENCY (%) 12.00 86 82 78 11.99 11.98 11.97 11.96 VPORT = 42.5V VPORT = 50V VPORT = 57V 74 70 0 1 2 3 LOAD CURRENT (A) VPORT = 42.5V VPORT = 50V VPORT = 57V 11.95 4 11.94 0 1 2 3 LOAD CURRENT (A) 4295 TA12b 4 4295 TA12c RELATED PARTS PART NUMBER DESCRIPTION LT4293 LT4294 LT4320/LT4320-1 LT4321 LTC4292/LTC4291-1 LTC4269-1 LTPoE++/IEEE 802.3bt PD Interface IEEE 802.3bt PD Controller Ideal Diode Bridge Controller PoE Ideal Diode Bridge Controller 4-Port IEEE 802.3bt PSE Controller IEEE 802.3at PD Interface with Integrated Flyback Switching Regulator IEEE 802.3at PD Interface with Integrated Forward Switching Regulator LTPoE++/PoE+/PoE PD Controller LTPoE++/PoE+/PoE PD with Forward/ Flyback Switching Regulator Controller LTC4269-2 LT4275A/B/C LT4276A/B/C LTC4278 COMMENTS Mutually identifies with LTPoE++ and IEEE 802.3bt PSEs External Switch, IEEE 802.3bt and AUX Support 9V-72V, DC to 600Hz Input. Controls 4-NMOSFETs, Voltage Rectification without Diode Drops Controls 8-NMOSFETs for IEEE-required PD Voltage Rectification without Diode Drops Transformer Isolation, Supports IEEE 802.3bt PDs 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, Aux Support 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to 500kHz, Aux Support External Switch, LTPoE++ Support External Switch, LTPoE++ Support, User-Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Incl Housekeeping Buck, Slope Compensation IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support Rev. B 32 05/19 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2016-2019