LTC4279 Single Port PoE/PoE+/ LTPoE++ PSE Controller FEATURES DESCRIPTION Compliant with IEEE 802.3at Type 1 and 2 nn Supports LTPoE++(R) Up to 90W nn Supports Dual-Signature PDs nn Fully Autonomous Operation without Microcontroller nn Very Low Power Dissipation - 0.1 Sense Resistance - Low RDS(ON) External MOSFET nn Very High Reliability 4-Point PD Detection - 2-Point Forced Voltage and Forced Current nn Robust Short-Circuit Protection nn Cable Surge Protected 80V OUT Pin nn Classification Dependent I CUT and ILIM Current Thresholds nn Supports 2-Pair and 4-Pair Output Power nn UltraPWR Mode Supports Custom PDs Up to 123W nn Pin-Selectable Detection Backoff Timer for Midspans nn Pin Programmable Legacy PD Detection nn Pin Programmable Maximum Power Mode nn Status LED Pin nn Available in 20-Pin QFN and 16-Pin SO Packages The LTC(R)4279 is an autonomous single port power sourcing equipment (PSE) controller designed for use in IEEE 802.3at Type 1, Type 2 and LTPoE++ compliant Power over Ethernet (PoE) systems. The LTC4279 provides fully autonomous IEEE 802.3 and LTPoE++ compliant operation without a microcontroller. The LTC4279 simplifies PSE implementation, requiring only a single supply and a small number of passive support components. nn APPLICATIONS The LTC4279 delivers lowest-in-industry heat dissipation by utilizing a low-RDS(ON) external MOSFET and a 0.1 sense resistor, eliminating the need for expensive heat sinks and increasing efficiency. PD discovery uses a proprietary dual-mode 4-point detection mechanism ensuring excellent immunity from false PD detection. Midspan PSEs are supported with physical layer classification and a 2.5 second backoff timer. Legacy and custom PDs are supported with pin-selectable LEGACY and UltraPWR modes. LEGACY mode detects and powers pre-IEEE specification PDs. UltraPWR mode aggressively turns on and powers custom PDs requiring high inrush and/or operational currents. L, LT, LTC, LTM, Linear Technology, the Linear logo and LTPoE++ are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. PoE PSE Endpoints (Switch/Router) nn PoE Midspan Power Injectors nn Power Forwarders nn Femto Cells nn Security Systems nn TYPICAL APPLICATION 10 TVSBULK CBULK LTC4279 RPM MID LEGACY DUALPD OUT GATE PWRMODE 1F 100V X7R SMAJ58A VEE LED RESET 0.22F 100V S1B X7R AGND + PORT - RGATE SENSE 0.1 VEE VSSK 4279 TA01 MAXIMUM PD INPUT POWER RPM (1%) Type 1 (13W) 2.37k Type 2 (25.5W) LTPoE++ 38.7W 3.32k LTPoE++ 52.7W LTPoE++ 70W 5.90k LTPoE++ 90W 10.0k UltraPWR - (Up to 123W*) 13.0k 4.64k 7.87k *Depending on VPSE 4279fa For more information www.linear.com/LTC4279 1 LTC4279 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 4) Supply Voltages AGND - VEE............................................ -0.3V to 80V VSSK.................................... VEE - 0.3V to VEE + 0.3V LEGACY, MID, DUALPD, LED, RESET, GATE, PWRMODE.......... VEE - 0.3V to VEE + 80V OUT............................................. VEE - 80V to VEE + 80V SENSE......................................... VEE - 20V to VEE + 80V Operating Ambient Temperature Range LTC4279I..............................................-40C to 85C Junction Temperature (Note 2)............................. 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec).................... 300C PIN CONFIGURATION DNC RESET TOP VIEW MID DNC TOP VIEW 20 19 18 17 MID 1 16 RESET DNC 2 15 DNC DNC 1 16 DUALPD 14 DUALPD DNC 2 15 LEGACY 13 LEGACY DNC 3 GATE 6 11 DNC OUT 7 10 VEE AGND 8 9 12 DNC SENSE 6 11 DNC 7 8 LED S PACKAGE 16-LEAD PLASTIC SO TJMAX = 125C, JA = 80C/W, JC = 30C/W ORDER INFORMATION 13 PWRMODE VSSK 5 9 10 LED 12 PWRMODE OUT SENSE 5 14 DNC 21 VEE VEE 4 AGND VSSK 4 GATE DNC 3 UFD PACKAGE 20-LEAD (4mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 43C/W, JC = 3.4C/W EXPOSED PAD (PIN 21) IS VEE http://www.linear.com/product/LTC4279#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4279IUFD#PBF LTC4279IUFD#TRPBF 4279 20-Lead (4mm x 5mm) Plastic QFN -40C to 85C LTC4279IS#PBF LTC4279IS#TRPBF LTC4279S 16-Lead Plastic SO -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 4279fa For more information www.linear.com/LTC4279 LTC4279 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3 and 4) SYMBOL PARAMETER CONDITIONS VEE Main PoE Supply Voltage AGND - VEE For IEEE Type 1 Compliant Output For IEEE Type 2, DUALPD, LTPoE++ 38.7W and LTPoE++ 52.7W Compliant Output For LTPoE++ 70W and LTPoE++ 90W Compliant Output For UltraPWR Output VUVLO_VEE Undervoltage Lockout AGND - VEE MIN TYP MAX UNITS l l 45 51 57 57 V V l 54.75 57 V 65 V 30 V l 51 l 20 IEE VEE Supply Current AGND - VEE = 55V REE VEE Supply Resistance VEE < VUVLO_VEE l Detection Current - Forced Current First Point, AGND - VOUT = 10V Second Point, AGND - VOUT = 3.5V l l 220 143 Detection Voltage - Forced Voltage AGND - VOUT, 5A IOUT 500A First Point Second Point l l 7 3 Detection Current Compliance AGND - VOUT = 0V Detection Voltage Compliance Detection Voltage Slew Rate 25 -1.7 mA 12 k 240 160 260 180 A A 8 4 9 5 V V l 0.8 0.9 mA AGND - VOUT, Open Port l 10.4 12 V AGND - VOUT, CPORT = 0.15F (Note 6) l Detection VOC 0.01 V/s Min. Valid Signature Resistance l 15.5 17 18.5 k Max. Valid Signature Resistance l 27.5 29.7 32 k Classification VCLASS VMARK Classification Voltage AGND - VOUT, 0mV VSENSE 8.8mV l 16 Classification Current Compliance SENSE - VSSK, VOUT = AGND l 8.8 Mark State Voltage AGND - VOUT, 0.1mV VSENSE 0.5mV l 7.5 Mark State Current Compliance SENSE - VSSK, VOUT = AGND l 8.8 Classification Threshold Voltage SENSE - VSSK Class 0 to 1 Class 1 to 2 Class 2 to 3 Class 3 to 4 Class 4 to Overcurrent l l l l l GATE Pin Pull-Down Current Port Off, VGATE = VEE + 5V Port Off, VGATE = VEE + 1V GATE Pin Fast Pull-Down Current VGATE = VEE + 5V GATE Pin On Voltage 20.5 9.4 V 10 mV 10 V 9.4 10 mV 0.5 1.3 2.1 3.1 4.5 0.65 1.45 2.3 3.3 4.8 0.8 1.6 2.5 3.5 5.1 mV mV mV mV mV l l 0.4 0.08 0.12 VGATE - VEE, IGATE = 1A l 8 Power Good Threshold Voltage VOUT - VEE l 2 2.4 2.8 V OUT Pin Pull-Up Resistance to AGND 0V (AGND - VOUT) 5V l 300 500 700 k Gate Driver mA mA 30 mA 14 V Output Voltage Sense 4279fa For more information www.linear.com/LTC4279 3 LTC4279 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3 and 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Current Sense VCUT VLIM Overcurrent Sense Active Current Limit Inrush Active Current Limit SENSE - VSSK Class 0, Class 3 Class 1 Class 2 Class 4 LTPoE++ 38.7W LTPoE++ 52.7W, Dual-Signature PD LTPoE++ 70W LTPoE++ 90W l l l l l l l l 35.6 10.0 19.6 60.8 89.0 130 160 225 37.5 11.2 20.8 63.6 91.9 135 165 232 39.6 12.0 22.0 67.2 95.0 140 170 240 mV mV mV mV mV mV mV mV SENSE - VSSK, VEE OUT VEE + 10V Class 0 to 3 Class 4 LTPoE++ 38.7W LTPoE++ 52.7W, Dual-Signature PD LTPoE++ 70W LTPoE++ 90W UltraPWR l l l l l l l 40.8 81.6 120 140 180 240 280 42.5 85.0 127 148 191 255 295 44.2 88.4 135 160 200 270 310 mV mV mV mV mV mV mV SENSE - VSSK, VEE OUT AGND - 29V, Class 0 to 4, LTPoE++ Dual-Signature PD UltraPWR l l l 40.8 81.6 140 42.5 85.0 148 44.2 88.4 160 mV mV mV VMIN DC Disconnect Sense Voltage SENSE - VSSK (Note 10) l 0.5 0.75 1 mV VSC Short-Circuit Sense SENSE - VSSK - VLIM l 30 60 90 mV Digital Input Low Voltage MID, LEGACY, DUALPD, RESET (Note 9) l Digital Input High Voltage MID, LEGACY, DUALPD, RESET (Note 9) l Internal Pull-Down to VEE MID, LEGACY, DUALPD 10 A Digital Interface VROC 0.8 2.1 V V Internal Pull-Up to VROC RESET -10 A Input Open Circuit Voltage RESET (Note 9) 3.6 V Output Low VLED - VEE, ILED = 1mA LED Pin LED Pin Current Limit 0.4 l l 10 V mA PSE Timing Characteristics tDET Detection Time Beginning to End of Detection (Note 6) l 380 410 440 ms tCLE1 Class Event Duration, Single Class Event (Note 6) l 12 15 18 ms 9.6 12 14.4 ms 0.1 ms tCLE Class Event Duration (Note 6) l tCLEON Class Event Turn-On Duration CPORT = 0.6F (Note 6) l tME Mark Event Duration (Note 6, Note 8) l 6.8 8.6 10.8 ms tMEL Last Mark Event Duration (Note 6, Note 8) l 16 20 24 ms tPON Power-On Delay From End of Valid Detect to Application of Power to Port (Note 6) l 82 ms Turn-On Rise Time (AGND - VOUT): 10% to 90% of (AGND - VEE), CPORT = 0.15F (Note 6) l Turn-On Ramp Rate CPORT = 0.15F (Note 6) l 4 15 24 s 10 V/s 4279fa For more information www.linear.com/LTC4279 LTC4279 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3 and 4) SYMBOL PARAMETER CONDITIONS tTOCL Turn-On Class Transition CPORT = 0.15F (Note 6) l MIN tED Fault Delay From ICUT or ILIM Fault to Next Detect (Note 6) l 1 TYP MAX 0.1 UNITS ms 1.3 s LEGACY Mode Detection Backoff LEGACY Enabled, RPORT = 150 (Note 6) l 2.7 3 3.3 s Midspan Mode Detection Backoff LEGACY Disabled, MID Enabled, RPORT = 15.5k (Note 6) l 2.3 2.5 2.7 s Power Removal Detection Delay From Power Removal after tDIS to Next Detect (Note 6) l 1 1.3 2.5 s tSTART Maximum Current Limit Duration During Port Start-Up (Note 6) l 52 59 66 ms tCUT Maximum Overcurrent Duration after Port Start-Up (Note 6) l 52 59 66 ms Maximum Overcurrent Duty Cycle (Note 6) l 5.8 6.3 6.7 % tLIM Maximum Current Limit Duration after Port Start-Up LTPoE++ PD, Dual-Signature PD or UltraPWR Mode Enabled (Note 6) l 10 12 14 ms (Legacy or IEEE PD) and UltraPWR Mode Disabled (Note 6) l 52 59 66 ms Current Pulse Width to Reset Disconnect Timer (Notes 6 and 7) l 1.6 3.6 ms 380 ms tMPS Maintain Power Signature (MPS) Pulse Width Sensitivity tDIS Maintain Power Signature (MPS) Dropout Time (Notes 5 and 6) l 320 Minimum Pulse Width for RESET l 4.5 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 140C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: All currents into device pins are positive; all currents out of device pins are negative. Note 4: The LTC4279 operates with a negative supply voltage (with respect to AGND). To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. 350 s Note 5: tDIS is the same as tMPDO defined by IEEE 802.3. Note 6: Guaranteed by design, not subject to test. Note 7: The IEEE 802.3at specification allows a PD to present its Maintain Power Signature (MPS) on an intermittent basis without being disconnected. In order to stay powered, the PD must present the MPS for tMPS within any tMPDO time window. Note 8: Load characteristics of the LTC4279 during Mark: 7V < (AGND - VOUT) < 10V or IOUT < 50A. Note 9: The LTC4279 Digital Interface operates with respect to VEE. All logic levels are measured with respect to VEE. Note 10: See Main PoE Power Supply section for DC disconnect related power supply requirements. 4279fa For more information www.linear.com/LTC4279 5 LTC4279 TYPICAL PERFORMANCE CHARACTERISTICS Type 1 Power On Sequence FORCED VOLTAGE DETECTION FORCED CURRENT DETECTION FORCED CURRENT AGND - OUT DETECTION 10V/DIV VEE = -55V CLASS 3 PD VEE VEE VEE = -55V CLASS 4 PD POWER ON 100ms/DIV 3.0 250 2.5 2.0 200 2.0 200 1.5 150 1.5 150 1.0 100 1.0 100 0.5 50 0.5 50 0 11 22 33 VOUT - VEE (V) 0 55 44 2.0 200 1.5 150 1.0 100 0.5 50 44 0 55 4279 G06 CLASSIFICATION VOLTAGE (V) ILIM (A) 22 33 VOUT - VEE (V) GATE VOLTAGE 10V/DIV -8 PORT VOLTAGE 20V/DIV -12 -16 -20 55 0 4279 G05 10 FAULT APPLIED PORT CURRENT 10A/DIV -4 44 250 MOSFET Gate Drive with Fast Pull-Down 0 VLIM (mV) 2.5 6 11 Classification Current Compliance 300 ULTRAPWR DUALPD 802.3/LTPoE++ 250 33 VOUT - VEE (V) 0 4279 G04 Inrush Current Limits 3.0 0 300 ULTRAPWR DUALPD CLASS 4 CLASS 0 TO 3 VLIM (mV) ILIM (A) 2.5 ILIM (A) 90.0W 70.0W 52.7W 38.7W VLIM (mV) 300 0 4279 G03 100ms/DIV UltraPWR, DUALPD, 802.3 Current Limits 3.0 22 VEE = -55V LTPoE++ 70W PD 4279 G02 LTPoE++ Current Limits 11 FORCED CURRENT DETECTION POWER ON 4279 G01 100ms/DIV 0 AGND - OUT 10V/DIV VEE POWER ON 0 FORCED VOLTAGE DETECTION LTPoE++ CLASSIFICATION FORCED VOLTAGE DETECTION TYPE 2 CLASSIFICATION TYPE 1 CLASSIFICATION AGND - OUT 10V/DIV LTPoE++ Power-On Sequence Type 2 Power On Sequence CURRENT LIMIT FAST PULLDOWN 50s/DIV 0 2 4 6 VSENSE (mV) 8 FAULT REMOVED 4279 G08 10 4279 G07 4279fa For more information www.linear.com/LTC4279 LTC4279 TYPICAL PERFORMANCE CHARACTERISTICS 4.0 VEE Supply Current vs Voltage LED Current vs Voltage 20 85C 25C -40C 3.5 16 3.0 I LED (mA) IEE (mA) 2.5 2.0 1.5 1.0 12 8 4 OUTPUT LOW OUT = VEE 0.5 0 0 10 20 30 40 VEE (V) 50 60 0 0.1 70 4279 G09 16 0 14 -2 12 PIN CURRENT (A) IRESET (A) 80 4279 G10 DUALPD, MID and LEGACY Current vs Voltage 2 -4 -6 -8 10 8 6 -10 4 -12 2 1 10 VLED (V) RESET Current vs Voltage -14 0.1 1 10 0 0.1 80 VRESET (V) 1 10 VPIN (V) 4279 G11 80 4279 G13 TEST TIMING DIAGRAMS CLASSIFICATION tDET FORCED-CURRENT VPORT FORCEDVOLTAGE 0V VOC 15.5V VCLASS 20.5V tCLE1 PD CONNECTED tPON VEE 4279 F01 Figure 1. Detect, Single Event Class and Turn-On Timing 4279fa For more information www.linear.com/LTC4279 7 LTC4279 TEST TIMING DIAGRAMS CLASSIFICATION tDET FORCED-CURRENT FORCEDVOLTAGE tME 0V VPORT tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE PD CONNECTED tCLEON tPON VEE 4279 F02 Figure 2. Detect, Two Event Class and Turn-On Timing CLASSIFICATION tDET FORCED-CURRENT VPORT FORCEDVOLTAGE tME 0V tME tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE tCLE PD CONNECTED tCLEON tPON VEE 4279 F03 Figure 3. Detect, Three Event Class and Turn-On Timing VLIM VSENSE TO VEE VCUT 0V VSENSE TO VEE VMIN tSTART, tCUT LED LED tMPS tDIS 4279 F05 4279 F04 Figure 4. Current Limit Timing 8 Figure 5. DC Disconnect Timing 4279fa For more information www.linear.com/LTC4279 LTC4279 PIN FUNCTIONS RESET: Reset Input, Active Low. When logic low, the LTC4279 is held inactive with the port off. When logic high, the LTC4279 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 4.5s wide from resetting the LTC4279. Internally pulled up to VROC. See Configuration Pin Protection section for proper connection. MID: Midspan Mode Input. When logic high, midspan mode is enabled and the LTC4279 acts as a midspan device. When logic low, midspan mode is disabled and the LTC4279 acts as an endpoint device. Internally pulled down to VEE. See Configuration Pin Protection section for proper connection. LEGACY: LEGACY Mode Input. When logic high, LEGACY mode is enabled. With LEGACY mode enabled, valid detection results include RSIG too Low, Detect Good, RSIG too High, and CPD too High as defined in Table 2; all Class 0, 1, 2 and 3 PDs presenting a valid detection signature are allocated 13W to ensure pre-802.3af PDs receive sufficient power; IEEE PoE PDs and LTPoE++ PDs are detected and classified as normal. When logic low, LEGACY mode is disabled. With LEGACY mode disabled only Detect Good is considered a valid detection result. Warning: LEGACY mode is, by definition, not IEEE compliant. Internally pulled down to VEE. See Configuration Pin Protection section for proper connection. DUALPD: Dual-Signature PD Mode Input. When logic high, DUALPD mode is enabled and the LTC4279 detects, classifies and powers dual-signature PDs. Valid dual-signature PDs are present when two Type 2 PD signatures are detected and classified in parallel. PWRMODE must be set to 52.7W or greater. When logic low, dual-signature PD support is disabled. Internally pulled down to VEE. See Configuration Pin Protection section for proper connection. PWRMODE: Maximum Power Mode. A single resistor from the PWRMODE pin to VEE sets the LTC4279 maximum deliverable power. See Applications Information for the resistor value to desired maximum power mappings. The resistor tolerance must be 1% or better. The PWRMODE pin can be set to 13W (Type 1), 25.5W (Type 2), LTPoE++ 38.7W, 52.7W, 70W, 90W or UltraPWR maximum power levels. LED: Port Powered LED. This pin is an open drain output that pulls down to VEE when the port is powered. See the LED Drive section for details on this circuit. AGND: Analog Ground. AGND pin should be connected to the return for the VEE supply through a 10 resistor. VEE: Supply Input. Connect to a negative voltage of between -45V and -57V for Type 1 PSEs, -51V to -57V for Type 2 PSEs and LTPoE++ 38.7W/52.7W PSEs, -54.75V to -57V for LTPoE++ 70W/90W PSEs or -51V to -65V for UltraPWR PSEs, relative to AGND. VSSK: Kelvin Sense to VEE. Connect to sense resistor common node. Do not connect directly to VEE plane. See Kelvin Sense section for proper connection. SENSE: Current Sense Input. SENSE monitors the external MOSFET current via a 0.1 sense resistor between SENSE and VEE. Whenever the voltage across the sense resistor exceeds the overcurrent detection threshold VCUT, the current limit fault timer counts up. If the voltage across the sense resistor reaches the current limit threshold VLIM, the GATE pin voltage is lowered to maintain constant current in the external MOSFET. See Applications Information for further details. See Kelvin Sense section for proper connection. GATE: Gate Drive. GATE should be connected to the gate of the external MOSFET through the RGATE resistor. When the MOSFET is turned on, the gate voltage is driven to 12V (typ) above VEE. During a current limit condition, the voltage at GATE will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE is pulled down, turning the MOSFET off. OUT: Output Voltage Monitor. OUT should be connected to the output port. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source voltage exceeds 10V. A 500k resistor is connected internally from OUT to AGND when the port is idle. DNC: Do Not Connect. All pins identified with DNC must be left unconnected. 4279fa For more information www.linear.com/LTC4279 9 LTC4279 APPLICATIONS INFORMATION OVERVIEW Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power at up to 13W. This initial specification was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.3at or PoE+, increasing the voltage and current requirements to provide 25.5W of power. The IEEE standard also defines PoE terminology. A device that provides power to the network is known as a PSE, or power sourcing equipment, while a device that draws power from the network is known as a PD, or powered device. PSEs come in two types: Endpoints (typically network switches or routers), which provide data and power; and Midspans, which provide power but pass through data. Midspans are typically used to add PoE capability to existing non-PoE networks. PDs are typically IP phones, wireless access points, security cameras, and similar devices. LTPoE++ Evolution Even during the process of creating the IEEE PoE+ 25.5W specification it became clear that there was a significant PSE RJ45 4 CAT 5 20 MAX ROUNDTRIP 0.05F MAX 5 GND and increasing need for more than 25.5W of delivered power. The LTC4279 responds to this market by allowing a reliable means of providing up to 90W of delivered power to an LTPoE++ PD. The LTPoE++ specification provides reliable detection and classification extensions to the existing IEEE PoE protocols that are backward compatible and interoperable with existing Type 1 and Type 2 PDs. Unlike other proprietary PoE++ solutions, Linear's LTPoE++ provides mutual identification between the PSE and PD. This ensures the LTPoE++ PD knows it may use the requested power at start-up because it has detected an LTPoE++ PSE. Dual-Signature PD Systems There exist proprietary solutions in which the data and spare pairs present two separate and individually valid PD signatures. Such systems provide roughly 51W at the PD interface. Each PD power channel, viewed in isolation, is fully compatible with IEEE 802.3at. One example of a dual-signature PD system is shown in Figure 7. As shown, the PSE controller simultaneously detects and classifies both PDs. Once successfully identified, the lumped PD channel is provided twice the Class 4 Current Inrush, twice the Class 4 Current Cutoff, twice the Class 4 Current Limit, and normal Class 4 DC Disconnect allocations. PD RJ45 4 5 SPARE PAIR 1 AGND 1 Tx Rx 2 PSE DATA PAIR 3 VEE GATE 2 3 Rx 0.1F Tx 6 DATA PAIR 6 -54V 7 7 8 8 GND PWRGD PD CONTROLLER -54VIN -54VOUT DC/DC CONVERTER + VOUT - SPARE PAIR 4279 F06 Figure 6. Power over Ethernet System Diagram 10 4279fa For more information www.linear.com/LTC4279 LTC4279 APPLICATIONS INFORMATION PSE PD GND RJ45 AGND PSE CONTROLLER VEE GATE OUT -54V RJ45 1 1 2 2 3 3 6 6 4 4 5 5 7 7 8 8 + GND PWRGD PD CONTROLLER -VIN DC/DC CONVERTER VOUT DC/DC CONVERTER VOUT + GND PWRGD PD CONTROLLER -VIN - -VOUT - -VOUT 4279 F07 Figure 7. Dual-Signature PD Power over Ethernet System Diagram LTC4279 Single Port PSE The LTC4279 is a fourth-generation single port PSE controller. Virtually all necessary circuitry is included to implement an IEEE 802.3at compliant PSE design, requiring only an external power MOSFET and sense resistor; these minimize power loss compared to alternative designs with an on-board MOSFET and sense resistor. The LTC4279 supports seven PD power levels. The mode is set by the PWRMODE resistor, as sampled during reset exit. When in LTPoE++ mode, the LTC4279 extends PoE power delivery capabilities to one of four LTPoE++ levels. LTPoE++ is a Linear Technology proprietary specification allowing for the delivery of up to 90W to LTPoE++ compliant PDs. The LTPoE++ architecture extends the 802.3at physical power negotiation to include 38.7W, 52.7W, 70W and 90W power levels. When DUALPD is enabled, the LTC4279 supports dualsignature PD topologies. Dual-signature PDs are defined as two PDs whose signature appears at the PD Power Interface (PI) as the parallel combination of two Type 2 PDs. Dual-signature PDs are autonomously detected, clas- sified and powered on by the LTC4279. Current inrush, cutoff, and limit are doubled to support dual-signature PD topologies. When in LTPoE++ or Type 2 mode, the LTC4279 is a fully IEEE-compliant Type 2 PSE supporting autonomous detection, classification and powering of Type 1 and Type 2 PDs. When in Type 1 mode, the LTC4279 is a fully autonomous 802.3af Type 1 PSE solution. Two-event classification is prohibited and Class 4 PDs are automatically treated as Class 0 PDs. UltraPWR mode enables the PSE to power all PDs presenting a valid detection and classification signature with enhanced inrush and operational current limits, regardless of classification result. This mode aggressively powers nonstandard PDs. PoE BASICS Common Ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as CAT-5 cable), transformer-coupled at each end to avoid ground 4279fa For more information www.linear.com/LTC4279 11 LTC4279 APPLICATIONS INFORMATION loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps of the data transformers to transmit power from the PSE to the PD without affecting data transmission. Figure 6 shows a high-level PoE system schematic. To avoid damaging legacy data equipment that does not expect to see DC voltage, the PoE specification defines a protocol that determines when the PSE may apply and remove power. Valid PDs are required to have a specific 25k common mode resistance at their input. When such a PD is connected to the cable, the PSE detects this signature resistance and turns on the power. When the PD is later disconnected, the PSE senses the open circuit and turns power off. The PSE also turns off power in the event of a current fault or short-circuit. When a PD is detected, the PSE looks for a classification signature that tells the PSE the maximum power the PD will draw. The PSE can use this information to reject a PD that will draw more power than the PSE has available. OPERATING MODES Table 1. PWRMODE Encodings PWRMODE RPM ( 1%) Type 1 (13W) 2.37k Type 2 (25.5W) LTPoE++ 38.7W 3.32k LTPoE++ 52.7W LTPoE++ 70W 5.90k LTPoE++ 90W 10.0k UltraPWR 13.0k 4.64k 7.87k The LEGACY pin determines whether pre-IEEE standard legacy PDs are powered. The MID pin determines whether midspan detection timing is enabled. The MID pin should be logic high if the standalone application is a midspan. DETECTION The LTC4279 is a fully autonomous PSE controller and provides a complete PSE solution for detection, classification and powering of PDs in an IEEE 802.3 or LTPoE++ compliant system. The LTC4279 will power all valid PDs with ICUT and ILIM values based on the PWRMODE pin and the PD classification result. The LTC4279 will remove power automatically if the port generates a current cutoff or limit fault. The LTC4279 senses removal of a PD and turns off power when the PD is disconnected. Internal control circuits comply with IEEE timing and electrical parameters. Power-On Reset and the Configuration Pins The initial LTC4279 configuration depends on the state of the MID, LEGACY, DUALPD and PWRMODE pins during reset exit. Reset occurs at power-up or whenever the RESET pin is pulled low. Changing any of the configuration pins after power-up will not change the behavior of the LTC4279 until a subsequent reset occurs. 12 Table 1 shows the PWRMODE encodings. The PWRMODE pin is configured by connecting RPM between the PWRMODE pin and VEE. The PWRMODE effect on PSE behavior is described in the Classification and Power Control sections. Detection Overview To avoid damaging network devices that were not designed to tolerate DC voltage, a PSE must determine whether the connected device is a valid PD before applying power. The IEEE specification requires that a valid PD have a common mode resistance of 25k 5% at any port voltage below 10V. The PSE must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in Figure 8). The PSE may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. In particular, the PSE must reject standard computer network ports, many of which have 150 common mode termination resistors that will be damaged if power is applied to them (the black region at the left of Figure 8). Table 2 shows the possible detection results. If a Detect Good result is acquired the LTC4279 will proceed to classification. 4279fa For more information www.linear.com/LTC4279 LTC4279 APPLICATIONS INFORMATION RESISTANCE 0 10k 20k 150 (NIC) PD PSE 15k sufficient power. When LEGACY is disabled, only PDs presenting Detect Good (including compliant IEEE PoE and LTPoE++ PDs) will be considered valid. 30k 23.75k 26.25k 19k 26.5k 33k 4279 F08 Figure 8. IEEE 802.3at Signature Resistance Ranges Table 2. Detection Status MEASURED PD SIGNATURE (TYPICAL) DETECTION RESULT Incomplete or Not Yet Tested Detect Status Unknown <2.4k Short-Circuit Capacitance > 2.7F CPD too High 2.4k < RPD < 17k RSIG too Low 17k < RPD < 29k Detect Good >29k RSIG too High >50k Open Circuit Voltage > 10V Port Voltage Outside Detect Range CURRENT (A) 275 25k SLOPE 165 0V-2V OFFSET Proprietary PDs that employ a dual-signature PD topology are detected in parallel. Such PDs will present a parallel resistance of one half of the Detect Good resistance. This parallel detection resistance is located in the RSIG too Low range as shown in Table 2. When DUALPD is enabled, dual-signature PDs (RSIG too Low detection results) will proceed to classification regardless of the LEGACY mode. CLASSIFICATION FIRST DETECTION POINT SECOND DETECTION POINT VALID PD Detection of Dual-Signature PDs VOLTAGE 4279 F09 Figure 9. PD Detection Detection of Legacy PDs Proprietary PDs that predate the original IEEE 802.3af standard are commonly referred to today as legacy PDs. One type of legacy PD uses a large common mode capacitance (>10F) as the detection signature. Note that PDs in this range of capacitance are defined as invalid, so a PSE that detects legacy PDs is technically noncompliant with the IEEE specification. The LTC4279 can be configured to detect this type of legacy PD when LEGACY is enabled. When LEGACY is enabled, valid detection results include CPD too High, RSIG too low, Detect Good, and RSIG too High. PDs presenting Class 0, 1, 2 or 3 are assigned Class 0 power allocation to ensure pre-802.3af PDs receive 802.3af Classification A PD must present a classification signature to the PSE to indicate the maximum power it will draw while operating. The IEEE specification defines this signature as a constant current draw when the PSE port voltage is in the VCLASS range (between 15.5V and 20.5V), with the current level indicating one of 5 possible PD classes. Figure 10 shows a typical PD load line, starting with the slope of the 25k signature resistor below 10V, then transitioning to the classification signature current (in this case, Class 3) in the VCLASS range. Table 3 shows the possible classification values. When LEGACY is enabled all Class 0, 1, 2 and 3 PDs are allocated 13W to ensure legacy PDs receive sufficient power. Legacy PDs may have an IEEE-like detection signature and do not support physical classification. Therefore, allocating 13W to all Type 1 and legacy PDs ensures full legacy PD support. Table 3. 802.3af and 802.3at Classification Values (LEGACY = Disabled) CLASS PWRMODE = TYPE 1 PWRMODE = TYPE 2 Class 0 No Class Signature Present; Treat Like Class 3 Class 1 3W Class 2 7W Class 3 Class 4 13W 13W (Demote to Class 0) 25.5W (Type 2) 4279fa For more information www.linear.com/LTC4279 13 LTC4279 APPLICATIONS INFORMATION The PSE will classify the PD immediately after a successful detection cycle. The PSE measures the PD classification signature by applying 18V for 12ms (both values typical) to the port via the OUT pin and measuring the resulting current. If a valid classification result is obtained, the LTC4279 will use the result to set the ICUT and ILIM thresholds. The LTC4279 supports 802.3af 1-event classification regardless of the PWRMODE setting. A Class 0 to 3 result during the first classification event will result in the PD receiving the appropriate amount of power as shown in Table 3. When a Class 4 result is obtained the LTC4279 response depends on PWRMODE, as shown in Table 3. If PWRMODE is set to Type 1 then the PD will be powered on after receiving only a single class event and will be allocated only 13W. If PWRMODE is set to Type 2 or higher, additional class events will be issued as described in the following sections. 100 90 OVER CURRENT CURRENT (mA) 70 60 PSE LOAD LINE 50 48mA 40 CLASS 4 30 CLASS 3 33mA Invalid Type 2 Class Combinations The 802.3at specification defines a Type 2 PD class signature as two consecutive Class 4 results; a Class 4 followed by a Class 0 to 3 is not a valid signature. If the PD presents an invalid Type 2 signature (Class 4 followed by Class 0 to 3), the LTC4279 will not provide power and will restart the detection process. TYPICAL CLASS 3 PD LOAD LINE 10 0 5 CLASS 2 CLASS 1 CLASS 0 10 15 VOLTAGE (VCLASS) The 802.3at 2-event physical classification method is extended using LTPoE++ 3-event classification signaling methods (Figure 3). 14.5mA 6.5mA 20 Dual-signature PDs are supported by performing a parallel classification. When a dual-signature PD is present, each PD will draw a nominal classification current of up to 40mA, for a total possible of 80mA. A dual-signature PD is validated when the LTC4279 observes both an RSIG too Low detection result and a multiple-event overcurrent classification result. Extended Power LTPoE++ Classification 23mA 20 25 4279 F10 Figure 10. PD Classification 802.3at 2-Event Classification The LTC4279 supports 802.3at 2-event physical classification when PWRMODE is set to Type 2 or higher. 14 Note that the LTC4279 only runs the second classification cycle when it detects a Class 4 device; if the first cycle returns Class 0 to 3, the port determines it is connected to a Type 1 PD and does not run the second classification cycle. Dual-Signature PD Classification 80 0 A Type 2 PD that is requesting more than 13W will indicate Class 4 during normal 802.3af classification. If the LTC4279 sees Class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9V), pauses briefly, and then re-runs classification to verify the Class 4 reading (Figure 2). The second cycle informs the PD that it is connected to a Type 2 PSE capable of supplying Type 2 power levels. LTPoE++ 3-event classification and power levels are enabled by setting PWRMODE to 38.7W or higher. The higher levels of LTPoE++ delivery impose additional layout and component selection constraints. LTPoE++ PDs requesting more than the available power limits are not powered. For example, if PWRMODE is set to 70W and an LTPoE++ 90W PD is detected and classified, the PD will not be powered. 4279fa For more information www.linear.com/LTC4279 LTC4279 APPLICATIONS INFORMATION Power Allocation UltraPWR MODE LTC4279 allocates power based on the PWRMODE setting as described in Table 1. The PWRMODE informs the PSE how much power is available. Based on the PD class result the PD is allocated power if sufficient power is available as shown in Figure 11. In some situations the PD will be denied power in accordance with the LTPoE++ protocol. A PSE in UltraPWR mode issues up to three class events and powers all valid PDs with maximum deliverable power, as determined by VPSE. Figure 12 shows PSE source power (at the PSE RJ45 jack) and PD delivered power (at the PD RJ45 jack) vs VPSE. The gray shaded area above 60V shows voltages exceeding SELV maximum; systems exceeding SELV maximum voltage may incur additional regulatory hurdles. DEVICE PSE PWRMODE SETTING 802.3at LTPoE++ STANDARD TYPE TYPE 1 TYPE 2 38.7W 52.7W 802.3at PD LTPoE++ TYPE 1 13W 13W 13W 13W 70W 90W 13W 13W TYPE 2 13W 25.5W 25.5W 25.5W 25.5W 25.5W 38.7W 13W 25.5W 38.7W 38.7W 38.7W 38.7W 52.7W 13W 25.5W - 52.7W 52.7W 52.7W 70W 13W 25.5W - - 70W 70W 90W 13W 25.5W - - - 90W Figure 11. PSE PWRMODE vs PD Class Power Allocation For example, an LTPoE++ 70W PSE will refuse power to an LTPoE++ 90W PD, but will power IEEE 802.3at PDs and LTPoE++ PDs requesting 70W and under with their full power allocation. In comparison, an IEEE Type 2 PSE will issue full power allocation to Type 1 and Type 2 PDs; all LTPoE++ PDs will be powered with a demoted allocation of 25.5W. An IEEE Type 1 PSE will issue full power allocation to IEEE Type 1 PDs; all Type 2 and LTPoE++ PDs will be powered with a demoted allocation of 13W. ABOVE SELV 180 160 PEAK POWER (W) 140 120 100 80 PSE SOURCE POWER PD DELIVERED POWER AT 50m PD DELIVERED POWER AT 100m 20 0 52 54 56 60 58 VPSE (V) 62 64 The primary function of the LTC4279 is to control the delivery of power to the PSE port. It does this by controlling the gate drive voltage of an external power MOSFET while monitoring the current via an external sense resistor and the output voltage at the OUT pin. This circuitry serves to couple the raw VEE input supply to the port in a controlled manner that satisfies the PD's power needs while minimizing both power dissipation in the MOSFET and disturbances on the VEE backplane. Inrush Control Once the decision has been made to turn on a port, the LTC4279 ramps up the GATE pin of the external MOSFET in a controlled manner. Under normal power-up circumstances, the MOSFET gate voltage will rise until the port current reaches the inrush current limit level, at which point the GATE pin will be servoed to maintain the specified IINRUSH current. During this inrush period, a timer (tSTART) runs. When output charging is complete, the port current will fall and the GATE pin will be allowed to continue rising to fully enhance the MOSFET and minimize its on-resistance. The final VGS is nominally 12V. If the tSTART timer expires and the PD is over the current limit level, the port will be turned off. Per the IEEE specification, the LTC4279 will normally set the inrush current limit (ILIM) to 425mA during inrush at port turn-on, and then switch to the classified ILIM setting once inrush has completed. 60 40 POWER CONTROL 66 4279 F12 Figure 12. UltraPWR Power vs VPSE When DUALPD is enabled and a dual-signature PD is successfully detected and classified, the inrush current will be doubled. This allows dual-signature PDs to be powered up in parallel. 4279fa For more information www.linear.com/LTC4279 15 LTC4279 APPLICATIONS INFORMATION When UltraPWR mode is enabled and a legacy, dualsignature, LTPoE++ or IEEE PD is detected and classified, ILIM will be set to 1.5A to provide more substantial inrush current for custom PDs. The ILIM current limiting circuit is always enabled and actively limits port current. ICUT is set to a lower value than ILIM to allow the port to tolerate minor faults without current limiting. Current Cutoff and Limit A second timer, tLIM, is enabled when a PD is allocated more than 25.5W to provide more aggressive MOSFET protection and turn off a port before MOSFET damage can occur. The tLIM timer starts when the ILIM threshold is exceeded. When the tLIM timer reaches 12ms (typical) the port is turned off. The LTC4279 automatically maintains two current thresholds (ICUT and ILIM), each with a corresponding timer (tCUT and tLIM). The ICUT and ILIM thresholds depend on several factors: the PD Class, the UltraPWR mode, and the DUALPD and LEGACY pin states. Table 4 shows the ICUT and ILIM values that will be automatically set depending on LEGACY pin, the UltraPWR state and the negotiated PD class. When UltraPWR is enabled, ICUT is disabled and ILIM is 2950mA (typical) regardless of classification result. Table 4. Typical ICUT and ILIM Values tLIM is not enabled when a PD is allocated 25.5W or less. Instead, tLIM behaviors are tracked by the tCUT timer, which counts up during both ILIM and ICUT events. ILIM Foldback The LTC4279 features a two-stage foldback circuit that reduces the port current if the port voltage falls below the normal operating voltage. This helps keep MOSFET power dissipation at safe levels. CLASS ULTRAPWR LEGACY ICUT ILIM Class 1 Disabled Disabled 112mA 425mA Class 2 Disabled Disabled 206mA 425mA Class 3, 0 Disabled Disabled 375mA 425mA Class 0, 1, 2, 3 Disabled Enabled 375mA 425mA Class 4 LTPoE++ 38.7W Disabled Don't Care 638mA 850mA Disabled Don't Care 919mA 1275mA Dual-Signature PD/ LTPoE++ 52.7W LTPoE++ 70W Disabled Don't Care 1350mA 1488mA Disabled Don't Care 1650mA 1913mA LTPoE++ 90W Disabled Don't Care 2325mA 2550mA MOSFET Fault Detection All Classes Enabled Don't Care Disabled 2950mA The LTC4279 is designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged. A failed MOSFET may short source to drain, which will make the port appear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the LTC4279 SENSE pin to rise to an abnormally high voltage. A failed MOSFET may also short from gate to drain, causing the LTC4279 GATE pin to rise to an abnormally high voltage. The LTC4279 OUT, SENSE and GATE pins are designed to tolerate up to 80V faults without damage. Per the IEEE specification, the LTC4279 will allow the port current to exceed ICUT for a limited period of time before removing power from the port, whereas it will actively control the MOSFET gate drive to keep the port current below ILIM. The port does not take any action to limit the current when only the ICUT threshold is exceeded, but does start the tCUT timer. If the current drops below the ICUT current threshold before its timer expires, the tCUT timer counts back down, but at 1/16 the rate that it counts up. If the tCUT timer reaches 60ms (typical) the port is turned off. This allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. 16 The LTC4279 will support current levels well beyond the maximum values in the 802.3at specification. High power PSE implementations require a larger external MOSFET and possibly additional heat sinking. Due to the high inrush current extra care is required during MOSFET selection. See the External Component Selection - External MOSFET section for more information. If the LTC4279 sees any of these conditions for more than 180s, it resets the entire chip. 4279fa For more information www.linear.com/LTC4279 LTC4279 APPLICATIONS INFORMATION Disconnect External MOSFET The LTC4279 monitors the powered port to ensure the PD continues to draw the minimum specified current. A disconnect timer counts up whenever port current is below 7.5mA (typ), indicating that the PD has been disconnected. If the tDIS timer expires, the port will be turned off. If the current returns before the tDIS timer runs out, the timer resets. As long as the PD exceeds the minimum current level for tMPS more often than tDIS, it will remain powered. Careful selection of the power MOSFET is critical to system reliability. LTC recommends the NXP PSMN075-100MSE for proven reliability in Type 1 and Type 2 PSE applications. LTC recommends the NXP PSMN040-100MSE for dual-signature PD and LTPoE++ PSE applications. SOA curves are not a reliable specification for MOSFET selection. Contact LTC Applications before using a MOSFET other than one of these recommended parts. RGATE (Figure 13) is an essential part of the current limit control loop. The RGATE value may depend upon MOSFET selection. An additional RC network across the MOSFET drain and gate is required for the UltraPWR MOSFET. See the UltraPWR Endpoint PSE application circuit for details. EXTERNAL COMPONENT SELECTION Main PoE Power Supply and Bypassing The LTC4279 requires one supply voltage to operate at VEE. VEE requires a negative voltage relative to AGND within the range specified in the Electrical Characteristics for each PSE Type. VEE is the main isolated PoE supply that provides power to the PD. Because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. For minimum IR loss and best system efficiency, set VEE near maximum amplitude (57V, or 65V for UltraPWR), leaving enough margin to account for transient over- or undershoot, temperature drift, and the line regulation specifications of the particular power supply used. Bypass capacitance between AGND and VEE is very important for reliable operation. If a short-circuit occurs at the port output, it can take as long as 1s for the LTC4279 to begin regulating the current. During this time the current is limited only by the small impedances in the circuit. A high current spike typically occurs, causing a voltage transient on the VEE supply and possibly causing the LTC4279 to reset due to a UVLO fault. A 1F, 100V X7R capacitor placed near the AGND and VEE pins along with an electrolytic bulk capacitor of at least 47F across the main supply is recommended to minimize spurious resets. To ensure compliance with DC disconnect, VEE supply ripple and noise must be less than 100mVP-P at frequencies above 150kHz. Note that supply ripple and noise is also limited by the IEEE 802.3at standard. For UltraPWR applications only, limit dV/dt on the VEE supply to less than 10V/ms when the supply is starting up. Sense Resistor The LTC4279 is designed to use a 0.1 current sense resistor to reduce power dissipation. In order to meet the ICUT and ILIM accuracy required by the IEEE specification, the sense resistor should have 1% tolerance or better, and no more than 200ppm/C temperature coefficient. The sense resistor must be sized according to power dissipation. See the Layout Guidelines section for proper Kelvin sensing. Port Output Capacitor The port requires a 0.22F capacitor across the LTC4279 OUT pin and AGND pin to keep the LTC4279 stable while in current limit during startup or overload. Common ceramic capacitors often have significant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this problem, X7R ceramic capacitors rated for at least 100V are recommended and must be located close to the OUT pin and AGND pin (see Layout Guidelines). Surge Protection Ethernet ports can be subject to significant cable surge events. To keep PoE voltages below a safe level and protect the application against damage, protection components (Figure 13) are required at the main supply, at the LTC4279 supply pins and at the output port. Bulk transient voltage suppression (TVSBULK) and bulk capacitance (CBULK) are required across the main PoE For more information www.linear.com/LTC4279 4279fa 17 LTC4279 APPLICATIONS INFORMATION R10 10 0805 C4 1F 100V X7R CBULK RPU RESET TVSBULK MID DUALPD LEGACY 100 100 100 100 D1 SMAJ58A VEE RESET AGND MID U1 LTC4279 DUALPD LEGACY VEE VSSK C6 0.22F 100V X7R SENSE GATE OUT RGATE RS1 VEE + D3 S1B OUT TO PORT - Q1 4279 F13 Figure 13. LTC4279 Surge Protection supply and should be sized to accommodate system level surge requirements. The LTC4279 (U1) requires a 10, 0805 resistor (R10) in series from supply AGND to the LTC4279 AGND pin. Across the LTC4279 AGND pin and VEE pin are an SMAJ58A, 58V TVS (D1) and a 1F, 100V bypass capacitor (C4). These components must be placed close to the LTC4279 pins. Finally, the port requires an S1B clamp diode (D3) from OUT to supply AGND. The diode protects the port from harmful surges that could cause OUT to go above AGND. This diode must have low impedance paths to the port. See Layout Guidelines for additional information on parts placement. Configuration Pin Protection The logic input pins (RESET, MID, LEGACY and DUALPD) may be hard tied to the AGND pin or to VEE. Alternatively, if a pull-up resistor (RPU) is implemented from a logic input pin to the LTC4279 supply, connect the resistor to the protected side of the 10 resistor at the AGND pin. For logic input pins configured off board through a connector, add a 100 resistor in series with the respective pin for protection during high voltage transients. LED Drive Connect an LED to the LTC4279 LED pin for a port on status indicator. The LED pin open drain pull-down output pulls down to VEE when the port is powered on and is high imped- 18 ance when the port is off. Pull the LED up to a supply with a current limiting resistor. Select the resistor value to provide enough LED current for adequate LED brightness and limit the current to below the LTC4279 LED pin current limit over the full supply range. The resistor must also have a power rating capable of the maximum supply voltage minus the LED drop and LED current. If the main PoE power supply is driving the LED, the pull-up resistor must connect to the LTC4279 AGND pin side of the surge protection 10 resistor. Refer to the Typical Application figure. LAYOUT GUIDELINES Strict adherence to parts placement and board layout is critical for optimal current reading accuracy, IEEE compliance, system robustness and thermal dissipation. Refer to the DC2541 demo board as a layout reference. Figure 14 is a cutout portion of the DC2541 that displays the focus topics in this section. The components are referenced in Figure 13. Kelvin Sense Proper connection of the port current Kelvin sense lines is important for current threshold accuracy and IEEE compliance. Refer to Figure 14 for an example layout of these Kelvin sense lines. The LTC4279 VSSK pin connects to a Kelvin sense trace to the sense resistor (VEE side) pad and is not connected directly to VEE copper areas. Similarly, the LTC4279 SENSE pin connects to a Kelvin sense trace that leads to the sense resistor (SENSE side) pad and is not 4279fa For more information www.linear.com/LTC4279 LTC4279 APPLICATIONS INFORMATION connected in the power path between the sense resistor and the MOSFET. Figure 14 shows the two Kelvin traces from the LTC42479 (U1) to the sense resistor (RS1). The LTC4249 VEE pins and the sense resistor VEE pad connect to the VEE copper areas. heat out away from the components. This is particularly important around the power MOSFET (Q1) during current limit conditions. R10 C6 Parts Placement Q1 The placement of key components around the LTC4279 is essential for application accuracy, stability and robustness. Figure 14 shows the port OUT capacitor (C6) and LTC4279 surge protection components located near the LTC4279. C4 D1 Thermal Considerations U1 RS1 The power paths from the main power supply to the port output will have high currents pass through at peak port power. Use wide traces and copper areas, along multiple vias to keep the power path resistance low. Use copper areas around power path components to help spread 4279 F14 Figure 14. Example LTC4279 Layout TYPICAL APPLICATIONS IEEE 802.3at, Type 1 or Type 2, Endpoint PSE T1 10 0805 CBULK TVSBULK 12k 1/2W SML-012P8T GREEN TR0+ T0C TR0- 1F 100V X7R VEE 100 RESET T1C DATA TO PHY VEE RESET TR1+ SMAJ58A AGND TR2+ T2C MID DUALPD PWRMODE VEE VSSK TR2- LED LTC4279 LEGACY SENSE GATE OUT 0.22F 100V X7R TR3+ T3C TR3- 200 RPM VEE TR1- * * * * * * * * * * * * * * * * 75 75 DATA AND POWER OUT 1 2 3 4 5 6 7 8 RJ45 75 0.01F 200V x4 S1B 0.1 75 PSMN075-100MSE MAXIMUM PD INPUT POWER RPM VEE RANGE TYPE 1 (13W) 2.37k -45V to -57V 749023015 TYPE 2 (25.5W) 3.32k -51V to -57V 749022017 T1 1000pF 2kV 4279 TA02 4279fa For more information www.linear.com/LTC4279 19 LTC4279 TYPICAL APPLICATIONS IEEE 802.3at, Type 1 or Type 2, Midspan PSE 10 0805 1F 100V X7R SMAJ58A 12k 1/2W VEE RESET TVSBULK 100 RESET AGND SML-012P8T GREEN MID DUALPD CBULK S1B LED LTC4279 0.22F 100V X7R LEGACY PWRMODE VEE VSSK SENSE GATE OUT 200 RPM 0.1 VEE PSMN075-100MSE ETH1-230L DATA IN RJ45 * * * * * * * * DATA AND POWER OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 75 75 75 75 0.01F 200V 1000pF 2kV RJ45 4279 TA03 0.01F 200V 1000pF 2kV 20 MAXIMUM PD INPUT POWER RPM VEE RANGE TYPE 1 (13W) 2.37k -45V to -57V TYPE 2 (25.5W) 3.32k -51V to -57V 4279fa For more information www.linear.com/LTC4279 LTC4279 TYPICAL APPLICATIONS LTPoE++ or Dual-Signature PD, Midspan or Endpoint, 4-Pair PSE Options 10 0805 1F 100V X7R CBULK SMAJ58A 12k 1/2W VEE TVSBULK RESET MID DUALPD 100 AGND RESET 100 SML-012P8T GREEN MID 100 LED DUALPD LTC4279 0.22F 100V X7R LEGACY PWRMODE VEE VSSK S1B SENSE GATE OUT 200 RSENSE 0.1 RPM VEE PSMN040-100MSE WURTH 749022016 COILCRAFT ETH1-460L TR0+ T0C TR0- TR1+ T1C DATA SOURCE TR1- TR2+ T2C TR2- TR3+ T3C TR3- * * * * * * * * * * * * * * * * 75 0.01F, 200V 75 0.01F, 200V 75 0.01F, 200V 75 0.01F, 200V DATA AND POWER OUT 1 2 3 4 5 6 7 8 RJ45 1000pF 2kV MAXIMUM PD INPUT POWER VEE RANGE RPM DUALPD PIN RSENSE POWER RATING LTPoE++ 38.7W -51V to -57V 4.64k LOW 1/4W LTPoE++ 52.7W -51V to -57V 5.90k LOW 1/2W DUALPD (52.7W) -51V to -57V 5.90k HIGH 1/2W LTPoE++ 70W -54.75V to -57V 7.87k LOW 1/2W LTPoE++ 90W -54.75V to -57V 10.0k LOW 1W DEVICE TYPE DATA SOURCE MID PIN ENDPOINT SWITCH PHY LOW MIDSPAN POWER INJECTOR DATA IN RJ45 HIGH 4279 TA04 4279fa For more information www.linear.com/LTC4279 21 LTC4279 TYPICAL APPLICATIONS UltraPWR Endpoint PSE 10 0805 1F 100V X7R CBULK SMAJ70A 12k 1/2W VEE RESET 100 SML-012P8T GREEN AGND RESET MID LED DUALPD LEGACY PWRMODE TVSBULK VEE S1B LTC4279 VSSK SENSE GATE OUT 0.22F 100V X7R RGATE 200 13.0k VEE -51V to -65V CGD 47nF 100V 0.1 2W RGD 400 PSMN4R8-100BSE 7490220123 TR0+ T0C 75 0.01F, 200V TR0- TR1+ T1C DATA TO PHY 75 0.01F, 200V TR1- TR2+ T2C 75 0.01F, 200V 75 0.01F, 200V TR2- TR3+ T3C TR3- POWER and DATA OUT 1 2 3 4 5 6 7 8 RJ45 1000pF 2kV 4279 TA05 22 4279fa For more information www.linear.com/LTC4279 LTC4279 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4279#packaging for the most recent package drawings. S Package 16-Lead Plastic Small Outline (Narrow .150 Inch) S Package (Reference LTC DWG # 05-08-1610 G) Inch) 16-Lead Plastic Small Outline (NarrowRev .150 (Reference LTC DWG # 05-08-1610 Rev G) .386 - .394 (9.804 - 10.008) NOTE 3 .045 .005 .050 BSC 16 N 14 13 12 11 10 9 N .245 MIN .160 .005 .150 - .157 (3.810 - 3.988) NOTE 3 .228 - .244 (5.791 - 6.197) 1 .030 .005 TYP 15 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 1 2 3 4 5 .053 - .069 (1.346 - 1.752) NOTE: 1. DIMENSIONS IN .014 - .019 (0.355 - 0.483) TYP 7 8 .004 - .010 (0.101 - 0.254) 0 - 8 TYP .016 - .050 (0.406 - 1.270) 6 .050 (1.270) BSC S16 REV G 0212 INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 4279fa For more information www.linear.com/LTC4279 23 LTC4279 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC4279#packaging for the most recent package drawings. UFD Package 20-Lead Plastic QFN (4mm x 5mm) UFD Package (ReferencePlastic LTC DWG # 05-08-1711 Rev B) 20-Lead QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 0.05 4.50 0.05 1.50 REF 3.10 0.05 2.65 0.05 3.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) 0.75 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 1.50 REF R = 0.05 TYP 19 20 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 0.10 (2 SIDES) 2.50 REF 3.65 0.10 2.65 0.10 (UFD20) QFN 0506 REV B 0.200 REF 0.00 - 0.05 R = 0.115 TYP 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 24 4279fa For more information www.linear.com/LTC4279 LTC4279 REVISION HISTORY REV DATE DESCRIPTION A 08/17 Changed minimum/maximum limits for t CLE1, t CLE and t ME . PAGE NUMBER Corrected transformer P/Ns. 4 21, 22 4279fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4279 25 LTC4279 TYPICAL APPLICATION IEEE 802.3at, Type 2, Endpoint PSE 749022017 10 0805 CBULK TVSBULK 12k 1/2W SML-012P8T GREEN TR0+ T0C TR0- 1F 100V X7R VEE RESET AGND RESET LED 0.22F 100V X7R VSSK SENSE GATE OUT 200 3.32k TR2+ TR2- LTC4279 PWRMODE VEE -51V to -57V TR1- T2C MID DUALPD LEGACY VEE T1C DATA TO PHY VEE 100 TR1+ SMAJ58A TR3+ T3C TR3- * * * * * * * * * * * * * * * * 75 DATA AND POWER OUT 75 1 2 3 4 5 6 7 8 75 75 S1B 0.1 1000pF 2kV PSMN075-100MSE RJ45 0.01F 200V x4 4279 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT4321 PoE Ideal Diode Bridge Controller Replaces 8 Diodes with 8 N-Channel MOSFETs, Reduces Heat, Maximizes Efficiency LTC4257-1 IEEE 802.3af PD Interface Controller 100V, 400mA Internal Switch, Dual Current Limit, Programmable Class LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch LTC4265 IEEE 802.3at PD Interface Controller 100V, 1A Internal Switch, 2-Event Classification Recognition Quad IEEE 802.3at/LTPoE++/af PoE PSE Controller With Programmable CUT/LIM, PD Classification, and Port Current and Voltage LTC4266/ LTC4266A/LTC4266C Monitoring. LTPoE++ Provides up to 90W LTC4267-3 IEEE 802.3af PD Interface with Integrated Switching Regulator 100V, 400mA Internal Switch, Programmable Class, 300kHz Constant Frequency PWM LTC4269-1 IEEE 802.3at PD Interface with Integrated Switching Regulator 2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback Controller, 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3at PD Interface with Integrated Switching Regulator 12-port PoE/PoE+/LTPoE++ PSE Controller 2-Event Classification, Programmable Classification, Synchronous Forward Controller, 100kHz to 500kHz, Aux Support Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs Single IEEE 802.3at/LTPoE++/af PoE PSE Controller PoE/PoE+/LTPoE++ PD Interface Controller With Programmable CUT/LIM, PD Classification, and Port Current and Voltage Monitoring. LTPoE++ Provides up to 90W LTC4270/LTC4271 LTC4274/LTC4274A/ LTC4274C LT4275 LT4276A/LT4276B/ LT4276C LTC4290/LTC4271 LT4295 26 100V, External Low RDS(ON) MOSFET, and 1/2/3-Event Classification Recognition, Aux Support, LTPoE++ Provides up to 90W LTPoE++/PoE+/PoE PD Interface Controller with Forward/Flyback Controller 8-port PoE/PoE+/LTPoE++ PSE Controller 100V, External Low RDS(ON) MOSFET, Forward or Flyback Topology, Aux Support, LTPoE++ Provides up to 90W Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs IEEE 802.3bt PD with Forward/Flyback Switching Regulator Controller External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation 4279fa LT 0817 REV A * PRINTED IN USA For more information www.linear.com/LTC4279 www.linear.com/LTC4279 LINEAR TECHNOLOGY CORPORATION 2017