LTC4279
9
4279fa
For more information www.linear.com/LTC4279
PIN FUNCTIONS
RESET: Reset Input, Active Low. When logic low, the
LTC4279 is held inactive with the port off. When logic
high, the LTC4279 begins normal operation. RESET can
be connected to an external capacitor or RC network to
provide a power turn-on delay. Internal filtering of the
RESET pin prevents glitches less than 4.5μs wide from
resetting the LTC4279. Internally pulled up to VROC. See
Configuration Pin Protection section for proper connection.
MID: Midspan Mode Input. When logic high, midspan
mode is enabled and the LTC4279 acts as a midspan
device. When logic low, midspan mode is disabled and
the LTC4279 acts as an endpoint device. Internally pulled
down to VEE. See Configuration Pin Protection section for
proper connection.
LEGACY: LEGACY Mode Input. When logic high, LEGACY
mode is enabled. With LEGACY mode enabled, valid detec-
tion results include RSIG too Low, Detect Good, RSIG too
High, and CPD too High as defined in Table 2; all Class 0,
1, 2 and 3 PDs presenting a valid detection signature are
allocated 13W to ensure pre-802.3af PDs receive sufficient
power; IEEE PoE PDs and LTPoE++ PDs are detected and
classified as normal. When logic low, LEGACY mode is
disabled. With LEGACY mode disabled only Detect Good
is considered a valid detection result. Warning: LEGACY
mode is, by definition, not IEEE compliant. Internally pulled
down to VEE. See Configuration Pin Protection section for
proper connection.
DUALPD: Dual-Signature PD Mode Input. When logic high,
DUALPD mode is enabled and the LTC4279 detects, clas-
sifies and powers dual-signature PDs. Valid dual-signature
PDs are present when two Type 2 PD signatures are detected
and classified in parallel. PWRMODE must be set to 52.7W
or greater. When logic low, dual-signature PD support is
disabled. Internally pulled down to VEE. See Configuration
Pin Protection section for proper connection.
PWRMODE: Maximum Power Mode. A single resistor
from the PWRMODE pin to VEE sets the LTC4279 maxi-
mum deliverable power. See Applications Information for
the resistor value to desired maximum power mappings.
The resistor tolerance must be 1% or better. The PWR-
MODE pin can be set to 13W (Type 1), 25.5W (Type 2),
LTPoE++ 38.7W, 52.7W, 70W, 90W or UltraPWR maximum
power levels.
LED: Port Powered LED. This pin is an open drain output
that pulls down to VEE when the port is powered. See the
LED Drive section for details on this circuit.
AGND: Analog Ground. AGND pin should be connected
to the return for the VEE supply through a 10Ω resistor.
VEE: Supply Input. Connect to a negative voltage of be-
tween –45V and –57V for Type 1 PSEs, –51V to –57V for
Type 2 PSEs and LTPoE++ 38.7W/52.7W PSEs, –54.75V
to –57V for LTPoE++ 70W/90W PSEs or –51V to –65V for
UltraPWR PSEs, relative to AGND.
VSSK: Kelvin Sense to VEE. Connect to sense resistor
common node. Do not connect directly to VEE plane. See
Kelvin Sense section for proper connection.
SENSE: Current Sense Input. SENSE monitors the external
MOSFET current via a 0.1Ω sense resistor between SENSE
and VEE. Whenever the voltage across the sense resistor
exceeds the overcurrent detection threshold VCUT, the
current limit fault timer counts up. If the voltage across
the sense resistor reaches the current limit threshold
VLIM, the GATE pin voltage is lowered to maintain con-
stant current in the external MOSFET. See Applications
Information for further details. See Kelvin Sense section
for proper connection.
GATE: Gate Drive. GATE should be connected to the gate
of the external MOSFET through the RGATE resistor. When
the MOSFET is turned on, the gate voltage is driven to 12V
(typ) above VEE. During a current limit condition, the volt-
age at GATE will be reduced to maintain constant current
through the external MOSFET. If the fault timer expires,
GATE is pulled down, turning the MOSFET off.
OUT: Output Voltage Monitor. OUT should be connected to
the output port. A current limit foldback circuit limits the
power dissipation in the external MOSFET by reducing the
current limit threshold when the drain-to-source voltage
exceeds 10V. A 500k resistor is connected internally from
OUT to AGND when the port is idle.
DNC: Do Not Connect. All pins identified with DNC must
be left unconnected.