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M9999-033105
MIC2592B
MIC2592B
Dual-Slot PCI Express Hot-Plug Controller
General Description
The MIC2592B is a dual-slot power controller supporting the
power distribution requirements for Peripheral Component
Interconnect Express (PCI Express) Hot-Plug compliant
systems. The MIC2592B provides complete power control
support for two PCI Express slots, including the 3.3VAUX
defi ned by the PCI Express standards. Support for 12V, 3.3V,
and 3.3VAUX supplies is provided including programmable
constant-current inrush limiting, voltage supervision, pro-
grammable current limit, and circuit breaker functions. These
features provide comprehensive system protection and fault
isolation. The MIC2592B also incorporates an SMBus interface
via which complete status of each slot is provided.
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Features
• Supports two independent PCI Express slots
• SMBus interface for slot power control and status
• Voltage-tolerant I/O for compatibility with SMBus 2.0
systems
• 12V, 3.3V, and 3.3VAUX supplies supported per PCI
Express Specifi cation v1.0a
- Intergrated power MOSFETs for 3.3V
AUX
- Intergrated power MOSFETs for 3.3VAUX - Intergrated power MOSFETs for 3.3V
rails
- Standby operation for Wake-on-LAN applications with
low backfeed on Main +12V and +3.3V rails.
• Programmable inrush current limiting
• Active current regulation controls inrush current
• Electronic circuit breaker for each supply to each slot
• High accuracies for both circuit breaker trip points and
nuisance trip prevention timers
• Dual level fault detection for quick fault response without
nuisance tripping
• Thermal isolation between circuitry for Slot A and Slot B
• Two General Purpose Input pins suitable for interface to
logic and switches.
Ordering Information
Part Number 12V and 3V 3.3VAUX Package
Standard Pb-Free Fast-Trip Thresholds Current Limit
MIC2592B – 2BTQ MIC2592B – 2YTQ 100mV 0.375A 48 Pin TQFP
MIC2592B – 3BTQ* MIC2592B – 3YTQ* 150mV 0.375A 48 Pin TQFP
MIC2592B – 5BTQ* MIC2592B – 5YTQ* Disabled 0.375A 48 Pin TQFP
* Contact factory for availability
Standard Pb-Free Fast-Trip Thresholds Current Limit
MIC2592B – 2BTQ MIC2592B – 2YTQ 100mV 0.375A 48 Pin TQFP
MIC2592B – 3BTQ* MIC2592B – 3YTQ* 150mV 0.375A 48 Pin TQFP
MIC2592B – 5BTQ* MIC2592B – 5YTQ* Disabled 0.375A 48 Pin TQFP
Part Number 12V and 3V 3.3VAUX Package
Standard Pb-Free Fast-Trip Thresholds Current Limit
MIC2592B – 2BTQ MIC2592B – 2YTQ 100mV 0.375A 48 Pin TQFP
MIC2592B – 3BTQ* MIC2592B – 3YTQ* 150mV 0.375A 48 Pin TQFP
MIC2592B – 5BTQ* MIC2592B – 5YTQ* Disabled 0.375A 48 Pin TQFP
Part Number 12V and 3V 3.3VAUX Package
MIC2592B – 2BTQ MIC2592B – 2YTQ 100mV 0.375A 48 Pin TQFP
MIC2592B – 3BTQ* MIC2592B – 3YTQ* 150mV 0.375A 48 Pin TQFP
MIC2592B – 5BTQ* MIC2592B – 5YTQ* Disabled 0.375A 48 Pin TQFP
Part Number 12V and 3V 3.3VAUX Package
Standard Pb-Free Fast-Trip Thresholds Current Limit
MIC2592B – 2BTQ MIC2592B – 2YTQ 100mV 0.375A 48 Pin TQFP
MIC2592B – 3BTQ* MIC2592B – 3YTQ* 150mV 0.375A 48 Pin TQFP
MIC2592B – 5BTQ* MIC2592B – 5YTQ* Disabled 0.375A 48 Pin TQFP
Part Number 12V and 3V 3.3VAUX Package
Part Number 12V and 3V 3.3VAUX Package
MIC2592B Micrel
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M9999-033105
Typical Application
System
Power
Supply
PCI Express Connector
+12V
+3.3V
VSTBY
VSTBYBVSTBYA VAUXA
12VINA
12VSENSEA
3VINA
3VSENSEA
12VINB
12VSENSEB
3VINB
3VSENSEB
12VGATEA
12VOUTA
3VGATEA
3VOUTA
3VGATEB
3VOUTB
VAUXB
GND
GND
A1
A2
A0
ONB
ONA
GPI_B0
GPI_A0
/FORCE_ONB
/FORCE_ONA
AUXENB
AUXENA
/INT
SCL
SDA
12VGATEB
12VOUTB
RFILTER[A&B]
CFILTERA
CFILTERB
MIC2592B
#CGS
22nF *R12VGATEA
15
Si4435DY
Si4420DY
#CGATE
22nF
#CMILLER
6800pF
15
RSENSE
0.020
PCI
Express
Bus
3.3AUX
375mA
3.3V
3.0A
12V
2.1A (x4/x8)
RSENSE
0.020
#CGS
22nF *R12VGATEB
15
Si4435DY
#CMILLER
6800pF
RSENSE
0.013
Si4420DY
#CGATE
22nF
*R3VGATEB
RSENSE
0.013
PCI Express Connector
PCI
Express
Bus
3.3AUX
375mA
3.3V
3.0A
12V
2.1A (x4/x8)
* Values for R12VGATE[A/B] and R3VGATE[A/B] may vary
depending upon the CGS of the external MOSFETs.
# These components are not required for MIC2592B
operation but can be implemented for GATE output
slew rate control (application specific)
¥ Bold lines indicate high current paths
4
9
2
11 26
5
8
3
10
12
13
14
16
32
29
34
27
25
24
23
21
22
17
GND 33
46
15
15
*R3VGATEA
0.1µF 0.1µF
0.1F
0.1F
0.1F
0.1F
/FAULTB
/FAULTA
/PWRGDB
/PWRGDA
1
ONB
ONA
AUXENB
AUXENA
/INT
SCL
SDA
110k
1%
Hot-Plug
Controller
SMBus I/O Management
Controller
48
47
37
43
42
38
28
35
20
45
44
VSTBY
C1
C2
VSTBY
10k x 3
10k x 4
SDA
SCL
/INT
SMBus
Base
Address 39
40
41
GPI_B0
100k 100k100k100k
GPI_A0
VSTBY
/FORCE_ONB
/FORCE_ONA
/FAULTB
/FAULTA
/PWRGDB
/PWRGDA
36
31
6
VSTBY
10k x 4
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M9999-033105
MIC2592B Micrel
Pin Confi guration
48-Pin TQFP
GND
3VOUTA
VAUXA
3VGATEA
3VSENSEA
NC
NC
RFILTER[A&B]
/FAULTA
CFILTERA
12VGATEA
GPI_A0
12VINA
/PWRGDA
NC
12VSENSEA
13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
/FORCE_ONA
12VOUTA
VSTBYA
3VINA
9
10
11
12
3VOUTB
VAUXB
3VGATEB
3VSENSEB
21 22 23 24
/FAULTB
CFILTERB
12VGATEB
GND
12VINB
/PWRGDB
NC
12VSENSEB
36
35
34
33
32
31
30
29
/FORCE_ONB
12VOUTB
VSTBYB
3VINB
28
27
26
25
ONA
AUXENA
GND
SCL
SDA
ONB
AUXENB
A0
48 47 46 45 44 43 42 41
A1
A2
GPI_B0
/INT
40 39 38 37
Hot-Plug
Control
Interface
Slot A
Interface
Slot B
Interface
MIC2592B Micrel
March 2005 4
M9999-033105
Pin Description
Pin Number Pin Name Pin Function
5 12VINA 12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.
32 12VINB connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 12V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
12 3VINA 3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for
25 3VINB connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 3V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
16 3VOUTA 3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to
21 3VOUTB monitor the 3.3V output voltages for Power-is-Good status.
10 12VOUTA 12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to
27 12VOUTB monitor the 12V output voltages for Power-is-Good status.
8 12VSENSEA 12V Circuit Breaker Sense Inputs: The current limit thresholds are set
29 12VSENSEB by connecting sense resistors between these pins and 12VIN[A/B]. When
the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin
is modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
FLT
, the circuit breaker is tripped and the GATE pin for the affected 12V
FLT
, the circuit breaker is tripped and the GATE pin for the affected 12V
FLT
supply’s external MOSFET is immediately pulled high.
13 3VSENSEA 3V Circuit Breaker Sense Inputs: The current limit thresholds are set by
24 3VSENSEB connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
FLT
, the circuit breaker is tripped and the GATE pin for the affected 3V
FLT
, the circuit breaker is tripped and the GATE pin for the affected 3V
FLT
supply’s external MOSFET is immediately pulled low.
3 12VGATEA 12V Gate Drive Outputs: Each pin connects to the gate of an external
34 12VGATEB P-Channel MOSFET. During power-up, the C
GATE
and the C
GS
of the
MOSFETs are connected to a 25µA current sink. This controls the value of
dv/dt seen at the source of the MOSFETs.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
FLT
. Whenever an
FLT
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought high. These pins
are charged by an internal current source during power-down. Also, the 3V
supply for the affected slot is shut-down.
14 3VGATEA 3V Gate Drive Outputs: Each pin connects to the gate of an external
23 3VGATEB N-Channel MOSFET. During power-up, the C
GATE
and the C
GS
of the
MOSFETs are connected to a 25µA current source. This controls the value
of dv/dt seen at the source of the MOSFETs, and hence the current fl owing
into the load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
FLT
. Whenever an
FLT
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought low. During power-
down, these pins are discharged by an internal current source. Also, the 12V
supply for the affected slot is shut down.
Pin Number Pin Name Pin Function
32 12VINB connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 12V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
12 3VINA 3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for
25 3VINB connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 3V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
16 3VOUTA 3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to
21 3VOUTB monitor the 3.3V output voltages for Power-is-Good status.
10 12VOUTA 12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to
27 12VOUTB monitor the 12V output voltages for Power-is-Good status.
8 12VSENSEA 12V Circuit Breaker Sense Inputs: The current limit thresholds are set
29 12VSENSEB by connecting sense resistors between these pins and 12VIN[A/B]. When
the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin
is modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
supply’s external MOSFET is immediately pulled high.
13 3VSENSEA 3V Circuit Breaker Sense Inputs: The current limit thresholds are set by
24 3VSENSEB connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
supply’s external MOSFET is immediately pulled low.
3 12VGATEA 12V Gate Drive Outputs: Each pin connects to the gate of an external
34 12VGATEB P-Channel MOSFET. During power-up, the C
MOSFETs are connected to a 25µA current sink. This controls the value of
dv/dt seen at the source of the MOSFETs.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought high. These pins
are charged by an internal current source during power-down. Also, the 3V
supply for the affected slot is shut-down.
14 3VGATEA 3V Gate Drive Outputs: Each pin connects to the gate of an external
23 3VGATEB N-Channel MOSFET. During power-up, the C
MOSFETs are connected to a 25µA current source. This controls the value
of dv/dt seen at the source of the MOSFETs, and hence the current fl owing
into the load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought low. During power-
down, these pins are discharged by an internal current source. Also, the 12V
supply for the affected slot is shut down.
Pin Number Pin Name Pin Function
5 12VINA 12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.
32 12VINB connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 12V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
12 3VINA 3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for
25 3VINB connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 3V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
16 3VOUTA 3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to
21 3VOUTB monitor the 3.3V output voltages for Power-is-Good status.
10 12VOUTA 12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to
27 12VOUTB monitor the 12V output voltages for Power-is-Good status.
8 12VSENSEA 12V Circuit Breaker Sense Inputs: The current limit thresholds are set
29 12VSENSEB by connecting sense resistors between these pins and 12VIN[A/B]. When
the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin
is modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
supply’s external MOSFET is immediately pulled high.
13 3VSENSEA 3V Circuit Breaker Sense Inputs: The current limit thresholds are set by
24 3VSENSEB connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
supply’s external MOSFET is immediately pulled low.
3 12VGATEA 12V Gate Drive Outputs: Each pin connects to the gate of an external
34 12VGATEB P-Channel MOSFET. During power-up, the C
MOSFETs are connected to a 25µA current sink. This controls the value of
dv/dt seen at the source of the MOSFETs.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought high. These pins
are charged by an internal current source during power-down. Also, the 3V
supply for the affected slot is shut-down.
14 3VGATEA 3V Gate Drive Outputs: Each pin connects to the gate of an external
23 3VGATEB N-Channel MOSFET. During power-up, the C
MOSFETs are connected to a 25µA current source. This controls the value
of dv/dt seen at the source of the MOSFETs, and hence the current fl owing
into the load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought low. During power-
down, these pins are discharged by an internal current source. Also, the 12V
supply for the affected slot is shut down.
Pin Number Pin Name Pin Function
5 12VINA 12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.
32 12VINB connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 12V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
12 3VINA 3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for
25 3VINB connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 3V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
16 3VOUTA 3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to
21 3VOUTB monitor the 3.3V output voltages for Power-is-Good status.
10 12VOUTA 12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to
27 12VOUTB monitor the 12V output voltages for Power-is-Good status.
8 12VSENSEA 12V Circuit Breaker Sense Inputs: The current limit thresholds are set
29 12VSENSEB by connecting sense resistors between these pins and 12VIN[A/B]. When
the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin
is modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
supply’s external MOSFET is immediately pulled high.
13 3VSENSEA 3V Circuit Breaker Sense Inputs: The current limit thresholds are set by
24 3VSENSEB connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
supply’s external MOSFET is immediately pulled low.
3 12VGATEA 12V Gate Drive Outputs: Each pin connects to the gate of an external
34 12VGATEB P-Channel MOSFET. During power-up, the C
MOSFETs are connected to a 25µA current sink. This controls the value of
dv/dt seen at the source of the MOSFETs.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought high. These pins
are charged by an internal current source during power-down. Also, the 3V
supply for the affected slot is shut-down.
14 3VGATEA 3V Gate Drive Outputs: Each pin connects to the gate of an external
23 3VGATEB N-Channel MOSFET. During power-up, the C
MOSFETs are connected to a 25µA current source. This controls the value
of dv/dt seen at the source of the MOSFETs, and hence the current fl owing
into the load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought low. During power-
down, these pins are discharged by an internal current source. Also, the 12V
supply for the affected slot is shut down.
March 2005 5
M9999-033105
MIC2592B Micrel
Pin Description (continued)
Pin Number Pin Name Pin Function
11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be externally connected together at the MIC2592B
controller.
15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
STBY
input supply is valid and stabe (i.e., t
STBY input supply is valid and stabe (i.e., t
STBY
POR
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the
42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
STBY
input supply is valid and stabe (i.e., t
STBY input supply is valid and stabe (i.e., t
STBY
POR
elapses - See the
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power
c
ontrol. Also, see pin description for /FAULTA an
d /FAULTB.
2 CFILTERA Overcurrent Timers: Capacitors connected between these
35 CFILTERB pins and GND set the duration of t
FLT
for each slot. The overcurrent fi lter
delay (t
FLT
) is the amount of time for which a slot remains in current limit
before its circuit breaker is tripped.
6 /PWRGDA /PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
31 /PWRGDB been commanded to turn on and has successfully begun delivering power to
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
al
pull-up resistor to V
STBY
.
STBY
.
STBY
1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
STBY
.
STBY
.
STBY
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
VAUX output. If a fault condition occurred on both the MAIN and VAUX
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
brought low to deassert the /FAULT[A/B] output.
9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifi cally defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
thermal protection for the VAUX[A/B] supplies. Additionally included are the
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do
not
disable UVLO protection for the VAUX[A/B]
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to refl ect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by
38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each
pin to GND.
Pin Number Pin Name Pin Function
26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be externally connected together at the MIC2592B
controller.
15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the
42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power
2 CFILTERA Overcurrent Timers: Capacitors connected between these
35 CFILTERB pins and GND set the duration of t
delay (t
before its circuit breaker is tripped.
31 /PWRGDB been commanded to turn on and has successfully begun delivering power to
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
pull-up resistor to V
1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
VAUX output. If a fault condition occurred on both the MAIN and VAUX
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
brought low to deassert the /FAULT[A/B] output.
9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifi cally defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to refl ect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by
pin to GND.
Pin Number Pin Name Pin Function
11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be externally connected together at the MIC2592B
controller.
15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the
42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power
2 CFILTERA Overcurrent Timers: Capacitors connected between these
35 CFILTERB pins and GND set the duration of t
delay (t
before its circuit breaker is tripped.
6 /PWRGDA /PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
31 /PWRGDB been commanded to turn on and has successfully begun delivering power to
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
pull-up resistor to V
1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
VAUX output. If a fault condition occurred on both the MAIN and VAUX
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
brought low to deassert the /FAULT[A/B] output.
9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifi cally defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to refl ect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by
38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each
pin to GND.
Pin Number Pin Name Pin Function
11 VSTBYA 3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
26 VSTBYB Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be externally connected together at the MIC2592B
controller.
15 VAUXA 3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
22 VAUXB the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
44 ONA Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
43 ONB and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
45 AUXENA Enable Inputs: Rising-edge triggered. Used to enable or disable the
42 AUXENB VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power
2 CFILTERA Overcurrent Timers: Capacitors connected between these
35 CFILTERB pins and GND set the duration of t
delay (t
before its circuit breaker is tripped.
6 /PWRGDA /PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
31 /PWRGDB been commanded to turn on and has successfully begun delivering power to
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an extern
pull-up resistor to V
1 /FAULTA /FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
36 /FAULTB circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
VAUX output. If a fault condition occurred on both the MAIN and VAUX
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
brought low to deassert the /FAULT[A/B] output.
9 /FORCE_ONA Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
28 /FORCE_ONB input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifi cally defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to refl ect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
4 GPI_A0 General Purpose Inputs: The states of these two inputs are available by
38 GPI_B0 reading the Common Status Register, Bits [4:5]. If not used, connect each
pin to GND.
MIC2592B Micrel
March 2005 6
M9999-033105
Pin Description (continued)
Pin Number Pin Name Pin Function
39 A2 SMBus Address Select Pins: Connect to ground or leave open in order to
40 A1 program device SMBus base address. These inputs have internal pull-up
41 A0 resistors to VSTBY[A/B].
48 SDA SMBus Data: Bidirectional SMBus data line.
47 SCL SMBus Clock: Input.
37 /INT Interrupt Output: Open-drain, active-low. Asserted whenever a power fault
is detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This
output is cleared by performing an "echo reset" to the appropriate fault bit(s)
in the STAT[A/B] and/or CS registers. This pin requires an external pull-up
resistor to V
STBY
.
STBY
.
STBY
17 GND 3 Pins, IC Ground Connections: Tie directly to the system’s analog GND
33 plane directly at the device.
46
20 RFILTER[A&B] Connecting this pin to GND through a 110kΩ, 1% resistor will provide a
signifi cant improvement in timeout duration accuracy for slow overcurrent
faults on Slot A and Slot B. If left fl oating (NC), overcurrent timeout duration
accuracy is determined by the specifi cation for V
FILTER
and I
FILTER
. Please
see the “Circuit Breaker Function” text in the “Functional Description” section
for more detail.
7 NC Reserved: Make no external connections to these pins.
18
19
30
40 A1 program device SMBus base address. These inputs have internal pull-up
41 A0 resistors to VSTBY[A/B].
48 SDA SMBus Data: Bidirectional SMBus data line.
47 SCL SMBus Clock: Input.
37 /INT Interrupt Output: Open-drain, active-low. Asserted whenever a power fault
is detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This
output is cleared by performing an "echo reset" to the appropriate fault bit(s)
in the STAT[A/B] and/or CS registers. This pin requires an external pull-up
resistor to V
17 GND 3 Pins, IC Ground Connections: Tie directly to the system’s analog GND
33 plane directly at the device.
46
20 RFILTER[A&B] Connecting this pin to GND through a 110kΩ, 1% resistor will provide a
signifi cant improvement in timeout duration accuracy for slow overcurrent
faults on Slot A and Slot B. If left fl oating (NC), overcurrent timeout duration
accuracy is determined by the specifi cation for V
see the “Circuit Breaker Function” text in the “Functional Description” section
for more detail.
7 NC Reserved: Make no external connections to these pins.
18
19
30
Pin Number Pin Name Pin Function
39 A2 SMBus Address Select Pins: Connect to ground or leave open in order to
40 A1 program device SMBus base address. These inputs have internal pull-up
41 A0 resistors to VSTBY[A/B].
48 SDA SMBus Data: Bidirectional SMBus data line.
47 SCL SMBus Clock: Input.
37 /INT Interrupt Output: Open-drain, active-low. Asserted whenever a power fault
is detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This
output is cleared by performing an "echo reset" to the appropriate fault bit(s)
in the STAT[A/B] and/or CS registers. This pin requires an external pull-up
resistor to V
17 GND 3 Pins, IC Ground Connections: Tie directly to the system’s analog GND
33 plane directly at the device.
20 RFILTER[A&B] Connecting this pin to GND through a 110kΩ, 1% resistor will provide a
signifi cant improvement in timeout duration accuracy for slow overcurrent
faults on Slot A and Slot B. If left fl oating (NC), overcurrent timeout duration
accuracy is determined by the specifi cation for V
see the “Circuit Breaker Function” text in the “Functional Description” section
for more detail.
7 NC Reserved: Make no external connections to these pins.
Pin Number Pin Name Pin Function
39 A2 SMBus Address Select Pins: Connect to ground or leave open in order to
40 A1 program device SMBus base address. These inputs have internal pull-up
41 A0 resistors to VSTBY[A/B].
48 SDA SMBus Data: Bidirectional SMBus data line.
47 SCL SMBus Clock: Input.
37 /INT Interrupt Output: Open-drain, active-low. Asserted whenever a power fault
is detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This
output is cleared by performing an "echo reset" to the appropriate fault bit(s)
in the STAT[A/B] and/or CS registers. This pin requires an external pull-up
resistor to V
17 GND 3 Pins, IC Ground Connections: Tie directly to the system’s analog GND
33 plane directly at the device.
20 RFILTER[A&B] Connecting this pin to GND through a 110kΩ, 1% resistor will provide a
signifi cant improvement in timeout duration accuracy for slow overcurrent
faults on Slot A and Slot B. If left fl oating (NC), overcurrent timeout duration
accuracy is determined by the specifi cation for V
see the “Circuit Breaker Function” text in the “Functional Description” section
for more detail.
7 NC Reserved: Make no external connections to these pins.
March 2005 7
M9999-033105
MIC2592B Micrel
Absolute Maximum Ratings
(1)
Supply Voltages
12VIN[A/B]
...............................................................
14V
3VIN[A/B], VSTBY[A/B]
...............................................
7V
Any Logic Pin
.........................
–0.5V (min) to 3.6V (max)
Output Current (/FAULT[A/B], /INT, SDA)
...................
10mA
Power Dissipation
.....................................
Internally Limited
Lead Temperature
(IR Refl ow, Peak Temperature)
........
240°C +0°C/–5°C
Pb-Free Package (-xYTQ)
(IR Refl ow, Peak Temperature)
........
260°C +0°C/–5°C
Storage Temperature
................................
–65°C to +150°C
ESD Rating
(
3)
Operating Ratings
(2)
Supply Voltages
12VIN[A/B]
................................................
11.0V to 13.0V
3VIN[A/B]
......................................................
3.0V to 3.6V
VSTBY[A/B]
..................................................
3.0V to 3.6V
Ambient Temperature (T
A
Ambient Temperature (TA
Ambient Temperature (T
)
.............................
0°C to + 70°C
Junction Temperature (T
J
)
.........................................
125°C
Package Thermal Resistance
TQFP
(θ
JA
)
......................................................................
56.5°C/W
Electrical Characteristics
(4)
12V
IN[A/B]
= 12V, 3V
IN[A/B]
= 3.3V, V
STBY[A/B]
= 3.3V, T
A
= 3.3V, TA
= 3.3V, T
= 25°C, unless otherwise noted.
A = 25°C, unless otherwise noted.
A
Bold
indicates specifi cation applies over the
full operating temperature range from 0°C to +70°C.
Symbol Parameter Condition Min Typ Max Units
Power Control and Logic Sections
I
CC12
Supply Current 2.5
5
mA
I
CC3.3
0.5
1
mA
I
CCSTBY
2.5
CCSTBY 2.5
CCSTBY
5
mA
Undervoltage Lockout Thresholds
V
UVLO(12V)
12VIN[A/B] 12V
IN[A/B]
increasing
8
9
10
V
V
UVLO(3V)
3VIN[A/B] 3V
UVLO(12V)
3VIN[A/B] 3V
UVLO(12V)
IN[A/B]
increasing
2.2
2.5
2.75
V
V
UVLO(STBY)
VSTBY[A/B] V
STBY[A/B]
increasing
2.8
2.9
3.0
V
V
HYSUV
Undervoltage Lockout Hysteresis 180 mV
12V
IN
, 3V
IN
V
HYSSTBY
Undervoltage Lockout Hysteresis 50 mV
HYSSTBY Undervoltage Lockout Hysteresis 50 mV
HYSSTBY
V
STBY[A/B]
Power-Good Undervoltage Thresholds
V
UVTH(12V)
12VOUT[A/B] 12V
OUT[A/B]
decreasing
10.2
10.5
10.8
V
V
UVTH(3V)
3VOUT[A/B] 3V
UVTH(12V)
3VOUT[A/B] 3V
UVTH(12V)
OUT[A/B]
decreasing
2.7
2.8
2.9
V
V
UVTH(VAUX)
VAUX[A/B] V
AUX[A/B]
VAUX[A/B] VAUX[A/B]
VAUX[A/B] V
decreasing
2.7
2.8
2.9
V
V
HYSPG
Power-Good Detect Hysteresis 30 mV
V
GATE(12V)
12VGATE Voltage
0
1.5
V
I
GATE(12VSINK)
12VGATE
Sink Current Start Cycle
15
25
35
µA
I
GATE(12VPULLUP)
12VGATE Pull-up Current (Fault Off) Any fault condition
–20
mA
(V
GATE(12VPULLUP)
(V
GATE(12VPULLUP)
DD
–V
GATE
) = 2.5V
V
GATE(3V)
3VGATE Voltage
12V
IN
–1.5
12V
IN
V
I
GATE(3VCHARGE)
3VGATE Charge Current Start Cycle
15
25
35
µA
I
GATE(3VSINK)
3VGATE Sink Current (Fault Off) Any fault condition
40
mA
V
GATE
= 2.5V
CFILTER[A/B]
Overcurrent Delay Time, Pin 20 (RFILTER[A&B]) Floating or NC
V
FILTER
CFILTER[A/B] Threshold Voltage
1.20
1.25
1.30
V
I
FILTER
CFILTER[A/B]
Charging Current V
12VIN
– V
12VSENSE
> V
THILIMIT
1.80
2.5
5.0
µA
Delay ms C F V (V)
I A
FILTER FILTER
FILTER
103
and/or
Notes:
1. Exceeding measurements given within the “Absolute Maximum Ratings” section may damage the device.
2. The device is not guaranteed to function outside of the measurements given in the “Operating Ratings" section.
3. Devices are ESD sensitive. Employ proper handling precautions. The human body model is 1.5kΩ in series with 100pF.
4. Specifi cation for packaged product only.
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
CFILTER[A/B] Threshold Voltage
1.25
2.5
µA
CFILTER[A/B] Threshold Voltage
Charging Current V
Supply Current 2.5
0.5
2.5
Undervoltage Lockout Thresholds
12VIN[A/B] 12V
3VIN[A/B] 3V
Undervoltage Lockout Hysteresis 180 mV
12V
Undervoltage Lockout Hysteresis 50 mV
V
12VOUT[A/B] 12V
3VOUT[A/B] 3V
Power-Good Detect Hysteresis 30 mV
12VGATE Voltage
12VGATE
12VGATE Pull-up Current (Fault Off) Any fault condition
(V
3VGATE Voltage
3VGATE Charge Current Start Cycle
3VGATE Sink Current (Fault Off) Any fault condition
V
Supply Current 2.5
0.5
2.5
Undervoltage Lockout Thresholds
12VIN[A/B] 12V
3VIN[A/B] 3V
VSTBY[A/B] V
Undervoltage Lockout Hysteresis 180 mV
Undervoltage Lockout Hysteresis 50 mV
12VOUT[A/B] 12V
3VOUT[A/B] 3V
VAUX[A/B] V
Power-Good Detect Hysteresis 30 mV
12VGATE Voltage
Sink Current Start Cycle
12VGATE Pull-up Current (Fault Off) Any fault condition
(V
3VGATE Voltage
3VGATE Charge Current Start Cycle
3VGATE Sink Current (Fault Off) Any fault condition
V
Supply Current 2.5
0.5
2.5
Undervoltage Lockout Thresholds
Undervoltage Lockout Hysteresis 180 mV
Undervoltage Lockout Hysteresis 50 mV
Power-Good Detect Hysteresis 30 mV
Supply Current 2.5
0.5
2.5
Undervoltage Lockout Thresholds
9
2.5
2.9
Undervoltage Lockout Hysteresis 180 mV
Undervoltage Lockout Hysteresis 50 mV
10.5
2.8
2.8
Power-Good Detect Hysteresis 30 mV
25
mA
25
mA
Undervoltage Lockout Thresholds
Undervoltage Lockout Hysteresis 180 mV
Undervoltage Lockout Hysteresis 50 mV
Power-Good Detect Hysteresis 30 mV
mA
mA
mA
mA
mA
V
V
V
Undervoltage Lockout Hysteresis 180 mV
Undervoltage Lockout Hysteresis 50 mV
V
V
V
Power-Good Detect Hysteresis 30 mV
V
µA
mA
V
µA
mA
V
3VIN
– V
3VSENSE
> V
THILIMIT
MIC2592B Micrel
March 2005 8
M9999-033105
Electrical Characteristics (continued)
(5)
Symbol Parameter Condition Min Typ Max Units
C
FILTER
Overcurrent DelayTime, Pin 20 grounded through RFILTER[A&B] = 110 kΩ, 1%
SF C
FILTER
Overcurrent Delay V
12VIN
– V
12VSENSE
> V
THILIMIT
THILIMIT
THILIMIT
Scaling Factor and/or
4.4
5
5.6
Delay(ms)=C
FILTER
(µF)
×
R
FILTER
(kΩ)
×
SF
V
3VIN
–V
3VSENSE
> V
THILIMIT
V
THILIMIT
Current Limit Threshold Voltages
THILIMIT Current Limit Threshold Voltages
THILIMIT
12V[A/B] supplies
V
12VIN
– V
12VSENSE
45
50
55
mV
3.3V[A/B] supplies V
3VIN
– V
3VSENSE
45
50
55
mV
V
THFAST
12VOUT[A/B] and 3VOUT[A/B] V
THFAST 12VOUT[A/B] and 3VOUT[A/B] V
THFAST
12VIN
– V
12VSENSE
MIC2592B-2BTQ
90
100
110
mV
Fast-Trip Threshold Voltages V
3VIN
– V
3VSENSE
MIC2592B-3BTQ
135
150
165
mV
MIC2592B-5BTQ Disabled
I
12VSENSE[A/B]
12VSENSE[A/B] Input current 0.35 µA
I
3VSENSE[A/B]
3VSENSE[A/B] Input current 0.35 µA
V
IL
LOW-Level Input Voltage
IL LOW-Level Input Voltage
IL
–0.5
0.8
V
ON[A/B], AUXEN[A/B], GPI_[A0/B0],
/FORCE_ON[A/B]
V
OL
Output LOW Voltage I
OL Output LOW Voltage I
OL
OL
= 3mA
OL = 3mA
OL
0.4
V
/FAULT[A/B], /PWRGD[A/B],
/INT, SDA
V
IH
HIGH-Level Input Voltage
2.1
3.6
V
ON[A/B], AUXEN[A/B], GPI_[A0/B0],
/FORCE_ON[A/B], A[0-2], SCL, SDA
R
PULLUP(A0 - A2)
Internal Pull-ups from A[0-2] to
40 kΩ
V
STBY[A/B]
I
LKG,OFF(
12VIN[A/B])
12VIN[A/B] Input leakage current V
STBY
= VSTBY[A/B] = +3.3V, 1 µA
STBY = VSTBY[A/B] = +3.3V, 1 µA
STBY
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
LKG,OFF(
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
LKG,OFF(
12VIN[A/B])
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
12VIN[A/B])
I
LKG,OFF(
3VIN[A/B])
3VIN[A/B] Input leakage current V
STBY
= VSTBY[A/B] = +3.3V, 1 µA
STBY = VSTBY[A/B] = +3.3V, 1 µA
STBY
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
LKG,OFF(
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
LKG,OFF(
3VIN[A/B])
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
3VIN[A/B])
I
IL
Input Leakage Current
IL Input Leakage Current
IL
±5
µA
SCL, ON[A/B], AUXEN[A/B],
/FORCE_ON[A/B]
I
LKG(OFF)
Off-State Leakage Current GPI_[A0/B0]: I
LKG
for these two pins
±5
µA
/FAULT[A/B], /PWRGD[A/B], measured with V
LKG(OFF)
/FAULT[A/B], /PWRGD[A/B], measured with V
LKG(OFF)
AUX
/FAULT[A/B], /PWRGD[A/B], measured with VAUX
/FAULT[A/B], /PWRGD[A/B], measured with V
OFF
/INT, SDA, GPI_[A0/B0]
T
OV
Overtemperature Shutdown and T
J
increasing, each slot
(6)
(6)
140 °C
Reset
Thresholds, with overcurrent on slot T
J
decreasing, each slot
(6)
130 °C
Overtemperature Shutdown and T
J
increasing, both slots
(6)
(6)
160 °C
Reset Thresholds, all other conditions T
J
decreasing, both slots
(6)
150 °C
(all outputs will latch OFF)
R
DS(AUX)
Output MOSFET Resistance I
DS
= 375mA, T
J
= 125°C
400
mΩ
VAUX[A/B] MOSFET
V
OFF(VAUX)
Off-State Output Offset Voltage V
AUX[A/B]
Off-State Output Offset Voltage VAUX[A/B]
Off-State Output Offset Voltage V
= Off, T
J
= 125°C
50
mV
V
AUX[A/B]
VAUX[A/B]
V
Notes:
5. Specifi cation for packaged product only.
6. Parameters guaranteed by design. Not 100% production tested.
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
SF C
Scaling Factor and/or
Current Limit Threshold Voltages
12V[A/B] supplies
3.3V[A/B] supplies V
12VOUT[A/B] and 3VOUT[A/B] V
Fast-Trip Threshold Voltages V
MIC2592B-5BTQ Disabled
LOW-Level Input Voltage
ON[A/B], AUXEN[A/B], GPI_[A0/B0],
/FORCE_ON[A/B]
Output LOW Voltage I
/FAULT[A/B], /PWRGD[A/B],
/INT, SDA
HIGH-Level Input Voltage
ON[A/B], AUXEN[A/B], GPI_[A0/B0],
/FORCE_ON[A/B], A[0-2], SCL, SDA
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
Input Leakage Current
SCL, ON[A/B], AUXEN[A/B],
/FORCE_ON[A/B]
Off-State Leakage Current GPI_[A0/B0]: I
/FAULT[A/B], /PWRGD[A/B], measured with V
/INT, SDA, GPI_[A0/B0]
Overtemperature Shutdown and T
Reset
Thresholds, with overcurrent on slot T
Overtemperature Shutdown and T
Reset Thresholds, all other conditions T
(all outputs will latch OFF)
Output MOSFET Resistance I
VAUX[A/B] MOSFET
Off-State Output Offset Voltage V
V
Overcurrent Delay V
Scaling Factor and/or
V
3.3V[A/B] supplies V
12VOUT[A/B] and 3VOUT[A/B] V
Fast-Trip Threshold Voltages V
MIC2592B-5BTQ Disabled
12VSENSE[A/B] Input current 0.35 µA
3VSENSE[A/B] Input current 0.35 µA
LOW-Level Input Voltage
Output LOW Voltage I
HIGH-Level Input Voltage
ON[A/B], AUXEN[A/B], GPI_[A0/B0],
40 kΩ
12VIN[A/B] Input leakage current V
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
3VIN[A/B] Input leakage current V
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
Input Leakage Current
Off-State Leakage Current GPI_[A0/B0]: I
/FAULT[A/B], /PWRGD[A/B], measured with V
/INT, SDA, GPI_[A0/B0]
Overtemperature Shutdown and T
Thresholds, with overcurrent on slot T
Overtemperature Shutdown and T
Reset Thresholds, all other conditions T
Output MOSFET Resistance I
Off-State Output Offset Voltage V
MIC2592B-5BTQ Disabled
12VSENSE[A/B] Input current 0.35 µA
3VSENSE[A/B] Input current 0.35 µA
= 3mA
40 kΩ
= VSTBY[A/B] = +3.3V, 1 µA
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
= VSTBY[A/B] = +3.3V, 1 µA
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
Input Leakage Current
for these two pins
140 °C
130 °C
160 °C
150 °C
= 125°C
= 125°C
5
50
50
100
150
MIC2592B-5BTQ Disabled
12VSENSE[A/B] Input current 0.35 µA
3VSENSE[A/B] Input current 0.35 µA
= 3mA
40 kΩ
= VSTBY[A/B] = +3.3V, 1 µA
12VIN[A/B] = OFF; 3VIN[A/B] = OFF
= VSTBY[A/B] = +3.3V, 1 µA
3VIN[A/B] = OFF; 12VIN[A/B] = OFF
Input Leakage Current
for these two pins
140 °C
130 °C
160 °C
150 °C
= 125°C
= 125°C
MIC2592B-5BTQ Disabled
12VSENSE[A/B] Input current 0.35 µA
3VSENSE[A/B] Input current 0.35 µA
40 kΩ
= VSTBY[A/B] = +3.3V, 1 µA
= VSTBY[A/B] = +3.3V, 1 µA
140 °C
130 °C
160 °C
150 °C
mV
mV
mV
mV
12VSENSE[A/B] Input current 0.35 µA
3VSENSE[A/B] Input current 0.35 µA
V
V
V
40 kΩ
= VSTBY[A/B] = +3.3V, 1 µA
= VSTBY[A/B] = +3.3V, 1 µA
µA
µA
140 °C
130 °C
160 °C
150 °C
mΩ
mV
MIC2592B-2BTQ
MIC2592B-3BTQ
MIC2592B-5BTQ Disabled
March 2005 9
M9999-033105
MIC2592B Micrel
Electrical Characteristics (continued)
(7)
Symbol Parameter Condition Min Typ Max Units
I
AUX(THRESH)
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
Threshold (Figure 4) V
AUX(THRESH)
Threshold (Figure 4) V
AUX(THRESH)
AUX
Threshold (Figure 4) VAUX
Threshold (Figure 4) V
to register as a fault
I
SC(TRAN)
Maximum Transient Short Circuit V
AUX
Maximum Transient Short Circuit VAUX
Maximum Transient Short Circuit V
Enabled, then Grounded
Current
IV
R
MAX
STBY[A/B]
DS(AUX)
A
I
LIM(AUX)
Regulated Current after Transient From end of I
SC(TRAN)
to C
FILTER
time-out 0.375 0.7 1.35 A
Output Discharge Resistance
R
DIS(12V)
12VOUT[A/B] 12V
OUT[A/B]
= 6.0V 1600 Ω
R
DIS(3V)
3VOUT[A/B] 3V
DIS(12V)
3VOUT[A/B] 3V
DIS(12V)
OUT[A/B]
= 1.65V 150 Ω
R
DIS(VAUX)
3VAUX[A/B] 3V
AUX[A/B]
3VAUX[A/B] 3VAUX[A/B]
3VAUX[A/B] 3V
= 1.65V 430 Ω
t
OFF(12V)
12V Current Limit Response Time MIC2592B-2BTQ 1
2.0
µs
(Figure 2) C
OFF(12V)
(Figure 2) C
OFF(12V)
GATE
= 25pF
V
IN
–V
SENSE
= 140mV
t
OFF(3V)
3.3V Current Limit Response Time MIC2592B-2BTQ 1
2.0
µs
(Figure 3) C
OFF(3V)
(Figure 3) C
OFF(3V)
GATE
= 25pF
V
IN
–V
SENSE
= 140mV
(8)
t
SC(TRAN)
VAUX[A/B] Current Limit Response V
AUX[A/B]
VAUX[A/B] Current Limit Response VAUX[A/B]
VAUX[A/B] Current Limit Response V
= 0V, V
STBYA
= V
STBYA = V
STBYA
STBYB
= +3.3V 2.5
5
µs
Time (Figure 5)
SC(TRAN)
Time (Figure 5)
SC(TRAN)
t
PROP(12VFAULT)
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Limit to /FAULT output C
PROP(12VFAULT)
Limit to /FAULT output C
PROP(12VFAULT)
FILTER
= 0
V
IN
–V
SENSE
= 140mV
(8)
t
PROP(3VFAULT)
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Limit to /FAULT[A/B] Output C
PROP(3VFAULT)
Limit to /FAULT[A/B] Output C
PROP(3VFAULT)
FILTER
= 0
V
IN
–V
SENSE
= 140mV
(8)
t
PROP(VAUXFAULT)
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
limit to /FAULT[A/B] output
PROP(VAUXFAULT)
limit to /FAULT[A/B] output
PROP(VAUXFAULT)
C
FILTER
= 0
V
AUX
VAUX
V
Output Grounded
(8)
t
W
ON[A/B], AUXEN[A/B] Pulse Width
Note 8
100
ns
t
POR
MIC2592B Power-On Reset Time
Note 8
250 µs
after VSTBY[A/B] becomes valid
SMBus Timing
t
1
SCL (clock) period Figure 1
2.5
µs
t
2
Data In setup time to SCL HIGH Figure 1
100
ns
t
3
Data Out stable after SCL LOW Figure 1
300
ns
t
4
Data LOW setup time to SCL LOW Start condition, Figure 1
100
ns
t
5
Data HIGH hold time after SCL HIGH Stop condition, Figure 1
100
ns
Notes:
7. Specifi cation for packaged product only.
8. Parameters guaranteed by design. Not 100% production tested.
Symbol Parameter Condition Min Typ Max Units
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
Threshold (Figure 4) V
Maximum Transient Short Circuit V
Current
Regulated Current after Transient From end of I
Output Discharge Resistance
12VOUT[A/B] 12V
3VOUT[A/B] 3V
3VAUX[A/B] 3V
12V Current Limit Response Time MIC2592B-2BTQ 1
(Figure 2) C
V
3.3V Current Limit Response Time MIC2592B-2BTQ 1
(Figure 3) C
V
VAUX[A/B] Current Limit Response V
Time (Figure 5)
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Limit to /FAULT output C
V
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Limit to /FAULT[A/B] Output C
V
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
limit to /FAULT[A/B] output
C
V
ON[A/B], AUXEN[A/B] Pulse Width
after VSTBY[A/B] becomes valid
Symbol Parameter Condition Min Typ Max Units
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
Threshold (Figure 4) V
Maximum Transient Short Circuit V
Current
Regulated Current after Transient From end of I
12VOUT[A/B] 12V
3VOUT[A/B] 3V
3VAUX[A/B] 3V
12V Current Limit Response Time MIC2592B-2BTQ 1
(Figure 2) C
V
3.3V Current Limit Response Time MIC2592B-2BTQ 1
(Figure 3) C
V
VAUX[A/B] Current Limit Response V
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Limit to /FAULT output C
V
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Limit to /FAULT[A/B] Output C
V
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
limit to /FAULT[A/B] output
C
V
Symbol Parameter Condition Min Typ Max Units
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
time-out 0.375 0.7 1.35 A
= 6.0V 1600 Ω
= 1.65V 150 Ω
= 1.65V 430 Ω
12V Current Limit Response Time MIC2592B-2BTQ 1
3.3V Current Limit Response Time MIC2592B-2BTQ 1
= +3.3V 2.5
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Note 8
250 µs
time-out 0.375 0.7 1.35 A
= 6.0V 1600 Ω
= 1.65V 150 Ω
= 1.65V 430 Ω
12V Current Limit Response Time MIC2592B-2BTQ 1
3.3V Current Limit Response Time MIC2592B-2BTQ 1
= +3.3V 2.5
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
250 µs
time-out 0.375 0.7 1.35 A
= 6.0V 1600 Ω
= 1.65V 150 Ω
= 1.65V 430 Ω
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
250 µs
Symbol Parameter Condition Min Typ Max Units
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
time-out 0.375 0.7 1.35 A
= 6.0V 1600 Ω
= 1.65V 150 Ω
= 1.65V 430 Ω
µs
µs
µs
Delay from 12V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from 3V[A/B] Overcurrent MIC2592B-2BTQ 1 µs
Delay from VAUX[A/B] Overcurrent MIC2592B-2BTQ 1 µs
250 µs
Symbol Parameter Condition Min Typ Max Units
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
Symbol Parameter Condition Min Typ Max Units
Auxiliary Output Current Limit Current which must be drawn from 0.84 A
SCL (clock) period Figure 1
Data In setup time to SCL HIGH Figure 1
Data Out stable after SCL LOW Figure 1
Data LOW setup time to SCL LOW Start condition, Figure 1
Data HIGH hold time after SCL HIGH Stop condition, Figure 1
SCL (clock) period Figure 1
Data In setup time to SCL HIGH Figure 1
Data Out stable after SCL LOW Figure 1
Data LOW setup time to SCL LOW Start condition, Figure 1
Data HIGH hold time after SCL HIGH Stop condition, Figure 1
µs
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
ns
ns
MIC2592B Micrel
March 2005 10
M9999-033105
Timing Diagrams
t1
t4
SCL
SDA
Data In
SDA
Data Out
t2t5
t3
Figure 1. SMBus Timing
6V
12VGATE
VTHFAST
VTHILIMIT
tOFF(12V)
VIN – VSENSE
t
0V
Figure 2. 12V Current Limit Response Timing
1V
3VGATE
VTHFAST
VTHILIMIT
tOFF(3V)
VIN – VSENSE
0V t
Figure 3. 3V Current Limit Response Timing
IOUT(AUX) IOUT(AUX)
ILIM(AUX)
Must Trip
May Not Trip
IAUX(THRESH)
I
0t
Figure 4. VAUX Current Limit Threshold
IOUT(AUX)
tSC(TRAN)
ILIM(AUX)
ISC(TRAN)
I
Ot
Figure 5. VAUX Current Limit Response Timing
March 2005 11
M9999-033105
MIC2592B Micrel
Typical Characteristics
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
0 1
1.20
0 1
1.20
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
CFILTER THRESHOLD (V)
TEMPERATURE (°C)
CFILTER Threshold
vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
IFILTER (A)
TEMPERATURE (°C)
CFILTER Charging Current
vs. Temperature
0
0.3
0.4
0.5
0.6
0.7
0.8
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
ILIM(AUX) (A)
TEMPERATURE (°C)
Auxiliary Regulated Current
vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
Supply Current
vs. Temperature
12V
STBY
3V
0
1
2
3
4
5
6
7
8
9
10
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
UVLO THRESHOLD (V)
TEMPERATURE (°C)
UVLO Threshold
vs. Temperature
12V
STBY
3V
0
2
4
6
8
10
12
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
UNDERVOLTAGE THRESHOLD (V)
TEMPERATURE (°C)
Power-Good Undervoltage
Threshold vs. Temperature
12V
STBY
3V
POWER-GOOD
10
15
20
25
30
35
40
0 1
10
0 1
10
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
GATE START-UP CURRENT (A)
TEMPERATURE (°C)
GATE Start-Up Curent
vs. Temperature
12V SINK
3V CHARGE
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
0 1
-0.50
0 1
-0.50
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
12V GATE VOLTAGE (V)
TEMPERATURE (°C)
12V GATE(ON)
vs. Temperature
10.00
10.25
10.50
10.75
11.00
11.25
11.50
11.75
12.00
0 1
10.00
0 1
10.00
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
3V GATE VOLTAGE (V)
TEMPERATURE (°C)
3V GATE
vs. Temperature
0
10
20
30
40
50
60
70
80
90
100
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
GATE SHUTDOWN CURRENT (mA)
TEMPERATURE (°C)
GATE Shutdown Current
vs. Temperature
12V PULLUP
3V SINK
45
46
47
48
49
50
51
52
53
54
55
0 1
45
0 1
45
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
CURRENT LIMIT (mV)
TEMPERATURE (°C)
Current Limit (Slow Threshold)
vs. Temperature
12V
3V
80
85
90
95
100
105
110
115
120
0 1
80
0 1
80
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
FAST THRESHOLD (mV)
TEMPERATURE (°C)
Current Limit (Fast Threshold)
vs. Temperature
MIC2592B-2BTQ
12V
3V
MIC2592B Micrel
March 2005 12
M9999-033105
Typical Characteristics (cont.)
0
100
200
300
400
500
600
700
800
900
1000
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
DISCHARGE RESISTANCE (Ω)
TEMPERATURE (°C)
Discharge Resistance
vs. Temperature
VAUX
3VOUT
12VOUT
4.4
4.6
4.8
5.0
5.2
5.4
5.6
0 1
4.4
0 1
4.4
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
SCALING FACTOR
TEMPERATURE (°C)
Overcurrent Delay Scaling
Factor vs. Temperature
0
50
100
150
200
250
300
350
400
0 1
0
0 1
0
0 2
0 3
0 4
0 5
0 6
0 50 60 5
0 7
0
RDS(ON)(Ω)
TEMPERATURE (°C)
VAUX On-Resistance
(RDS(ON)) vs. Temperature
Test Circuit
M2
Si4435BDY
ONA
CFILTERA
GND
3VINA 3VSENSEA 3VGATEA
VAUXA
R1
10k
R3VSENSEA
0.010Ω
R5
15Ω
C3VGATE
22nF
M1
Si4410DY
0.1µF
0.1µF
CMILLER
22nF
+3.3VOUTA
+3.3V
CFILTER
0.047µF
(Additional pins omitted for clarity - Slot A shown only)
AUXENA
VSTBYA
/FAULTA
R2
10k
SIGNALS
UNDER
SOFTWARE
CONTROL
R3
10k
12VINA 12VSENSEA
12VGATEA
R6
15Ω
CIN2
220µF
+12V
R12VSENSEA
0.025Ω
CGS
10nF
0.1µF
CLOAD2
100µF
CLOAD1
100µF
+12VOUTA
+3.3AUXA
12VOUTA
3VOUTA
MIC2592B
/PWRGDA
VSTBY
R4
10k
CIN1
220µF
CLOAD3
1µF
MIC2592B Test Circuit
March 2005 13
M9999-033105
MIC2592B Micrel
TIME (5ms/div.)
12VOUT
(5V/div.)
/FAULT
(5V/div.)
IOUT(12V)
(1A/div.)
CFILTER
(1V/div.)
12V Overcurrent Fault Response
RLOAD = 3.3Ω
Slot A
TIME (5ms/div.)
IAUXB
(500mA/div.)
CFILTERB
(1V/div.)
/FAULTB
(5V/div.)
Auxiliary Overcurrent Fault Response
VAUXA
(2V/div.)
RLOAD = 3.3Ω
Overcurrent on Slot B
Functional Characteristics
TIME (5ms/div.)
3VOUT
(2V/div.)
/FAULT
(5V/div.)
IOUT(3V)
(2A/div.)
CFILTER
(1V/div.)
3V Overcurrent Fault Response
RLOAD = 0.4Ω
Slot A
TIME (5ms/div.)
IOUT(12V)
(1A/div.)
/FAULTA
(5V/div.)
CFILTERA
(1V/div.)
/FAULTB
(1V/div.)
Overcurrent Fault Response
Channel Independent
RLOAD = 3.3Ω
Overcurrent on Slot A, 12V Supply
TIME (2.5ms/div.)
12VOUT
(5V/div.)
/PWRGD
(5V/div.)
3VOUT
(2V/div.)
VAUX
(2V/div.)
Turn-On Response
Slot A
TIME (5ms/div.)
12VGATE
(5V/div.)
3VGATE
(5V/div.)
ON
(5V/div.)
GATE Output Turn-On Response
Slot A
MIC2592B Micrel
March 2005 14
M9999-033105
TIME (250ms/div.)
/PWRGD
(2V/div.)
12VOUT
(2V/div.)
12V Ouput Discharge Response
Output disabled by ON pin
CLOAD = 1000µF
IOUT = 0A
VUV(12V)
TIME (25ms/div.)
/PWRGD
(2V/div.)
3VOUT
(1V/div.)
3V Ouput Discharge Response
Output disabled by ON pin
CLOAD = 1000µF
IOUT = 0A
VUV(3V)
Functional Characteristics cont.
TIME (500µs/div.)
12VIN &VSTBY
(5V/div.)
/FAULT
(5V/div.)
3VIN
(1V/div.)
3V Undervoltage Fault Response
MAIN(12V and 3.3V) Supplies ENABLED
Slot A
VUVLO(3V)
+3VIN
/FAULT
+12VIN
VSTBY
TIME (500µs/div.)
VSTBY
(2V/div.)
3VIN
(2V/div.)
/FAULT
(5V/div.)
12VIN
(5V/div.)
12V Undervoltage Fault Response
MAIN(12V and 3.3V) Supplies ENABLED
Slot A
VUVLO(12V)
+12VIN
/FAULT
+12VIN
VSTBY
March 2005 15
M9999-033105
MIC2592B Micrel
Functional Block Diagram
Logic Circuits
VAUX
PWRGD
Thermal
Shutdown
ON/OFF
VAUX Charge
Pump &
MOSFET
VAUX
Overcurrent
Bandgap
Reference
3VIN[A/B]
VREF
VREF
DIGITAL CORE/SERIAL INTERFACE
12VIN[A/B]
VREF
12VBIAS
Power-on
Reset
250s
3V
UVLO
12V
UVLO
ON/OFF
ON/OFF
ON/OFF
ON/OFF
50mV
50mV
100mV*
100mV*
VSTBY(REF)
Current Mirror
Overcurrent Detection
RFILTER[A&B]
OPEN PIN
DETECTOR
VREF
IREF
VSTBY(REF)
40k 3
12VGATE[A/B]
VAUX[A/B]
3VGATE[A/B]
/PWRGD[A/B]
/FAULT[A/B]
3VOUT[A/B]
12VOUT[A/B]
3VPWRGD
12VPWRGD
/INT
GND
A0A1A2SDASCL
GPI_[A0/B0]
/FORCE_ON[A/B]
RFILTER[A&B]
CFILTER[A/B]
3VIN[A/B]
3VSENSE[A/B]
12VIN[A/B]
12VSENSE[A/B]
ON[A/B] AUX[A/B] VSTBY[A/B]
VSTBY
UVLO
* MIC2592B-3BTQ fast threshold is 150mV
MIC2592B-5BTQ fast threshold is disabled
Contact factory for availabilty
MIC2592B Block Diagram
MIC2592B Micrel
March 2005 16
M9999-033105
MIC2592B
A2
/INT
SDA
SCL
A0
VSTBY
VSTBY
A1
100k
47
48
37
39
40
41
100k
Disabling SMI when
HPI Control is used
Disabling HPI when
SMI Control is used
100k
/INT
/FORCE_ONB
100k 100k
/FORCE_ONA
AUXENA
AUXENB
ONA
ONB
MIC2592B
9
28
45
42
44
43
Figure 6. Input Pin Confi guration for Disabling HPI/SMI Control
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying live
supply voltages (“hot-plugged”), high inrush currents often
result due to the charging of bulk capacitance that resides
across the circuit board’s supply pins. This transient inrush
current can cause the system’s supply voltages to temporarily
go out of regulation, causing data loss or system lock-up. In
more extreme cases, the transients occurring during a hot-
plug event may cause permanent damage to connectors or
on-board components.
The MIC2592B addresses these issues by limiting the in-
rush currents to the load (PCI Express Board), and thereby
controlling the rate at which the load’s circuits turn-on. In
addition to this inrush current control, the MIC2592B offers
input and output voltage supervisory functions and current
limiting to provide robust protection for both the system and
circuit board.
System Interface
The MIC2592B employs two system interfaces: the hard-
ware Hot-Plug Interface (HPI) and the System Management
Interface (SMI). The HPI includes ON[A/B], AUXEN[A/B],
as well as /FAULT[A/B]; the SMI consists of SDA, SCL,
and /INT, whose signals conform to the levels and timing of
the SMBus specifi cation. The MIC2592B can be operated
exclusively from the SMI, or can employ the HPl for power
control while continuing to use the SMI for access to all but
the power control registers.
In addition to the basic power control features of the MIC2592B
accessible by the HPI, the SMI also gives the host access to
the following information from the part:
• Fault conditions occurring on each supply.
• GPI_[A0/B0] pin status
When using the System Management Interface for power
control, do not use the Hot-Plug Interface. Conversely, when
using the Hot-Plug Interface for power control, do not execute
power control commands over the System Management
Interface bus (all other register accesses via the SMI bus
remain permissible while in the HPI control mode). When
utilizing the SMI exclusively, the HPI input pins (ON[A/B],
AUXEN[A/B], and /FORCE_ON[A/B]) should be confi gured
as shown below in Figure 6 (Disabling HPI when SMI control
is used). This confi guration safeguards the power slots in the
event that the SMBus communication link is disconnected
for any reason.
Additionally, when utilizing the HPI exclusively, the SMBus
(or SMI) will be inactive if the input pins (SDA, SCL, A0, A1,
and A2) are confi gured as shown in Figure 6 below (Disabling
SMI when HPI Control is used).
Power Stability and Power-On Reset
The MIC2592B utilizes VSTBY[A/B] as the main supply input
source. VSTBY[A/B] is required for proper operation of the
MIC2592B’s SMBus and registers and must be applied at
all times. To ensure that the MIC2592B controller operates
properly, the V
STBY
input must be stable and remain above
STBY input must be stable and remain above
STBY
the undervoltage lockout (UVLO) threshold once applied.
Suffi cient input bulk capacitance should be used to prevent
the supply from "drooping", causing VSTBY[A/B] to fall below
the UVLO threshold. Also, decoupling capacitors should be
placed at each of the MIC2592B inputs in order to fi lter high
frequency noise transients.
V
STBY
must be the fi rst supply input applied followed by the
STBY must be the fi rst supply input applied followed by the
STBY
MAIN supply inputs of 12V
IN
and 3V
IN
. A Power-On Reset
(POR) cycle is initiated after VSTBY[A/B] rises above its
UVLO threshold and remains valid at that voltage for 250µs.
All internal registers are cleared after POR. If VSTBY[A/B] is
recycled, the MIC2592B enters a new power-on-reset cycle.
The SMBus is ready for access at the end of the POR cycle
(250µs after VSTBY[A/B] is valid). During t
POR
, all outputs
remain off. In most applications, the total POR interval will
consist of the time required to charge the V
STBY
input (by-
STBY input (by-
STBY
pass) capacitance to the UVLO threshold plus the internal
t
POR
. The following equation is used to approximate the total
POR interval:
tPOR_TOTAL(µS) =
CSTBY(µF) VULVO(STBY)
ICHARGE(STBY)(A)
tPOR(µS)
10 6
where C
STBY
is the V
STBY is the V
STBY
STBY
input bulk bypass capacitance and
STBY input bulk bypass capacitance and
STBY
I
CHARGE(STBY)
is the current supplied by the V
STBY
source
STBY source
STBY
to charge the capacitance.
CHARGE(STBY)
to charge the capacitance.
CHARGE(STBY)
Power-Up Cycle
Enabling the GATE output
When a slot's MAIN supplies are off, the 12VGATE pin is held
high with an internal pull-up. Similarly, the 3VGATE pin is
internally held low. When the MAIN supplies of the MIC2592B
are enabled by asserting ON[A/B], the 3VGATE[A/B] and
12VGATE[A/B] pins are each connected to a constant cur-
rent supply. These supplies are each nominally 25µA. For a
slot’s 3VGATE pin, this is a current source; for the 12VGATE
pin, this is a current sink.
March 2005 17
M9999-033105
MIC2592B Micrel
Inrush Current and Load Dominated Start-up
The expected maximum inrush current can be calculated by
using the following equation:
INRUSH I C
C25 AC
C
GATE LOAD
GATE
LOAD
GAT
E
where
I
GATE
is the GATE pin current, I
GATE(3VCHARGE)
or I
GATE(12VSINK)
, C
LOAD
is the load capacitance, and
GATE(3VCHARGE)
is the load capacitance, and
GATE(3VCHARGE)
C
GATE
is the total GATE capacitance (C
GATE(12VSINK)
is the total GATE capacitance (C
GATE(12VSINK)
ISS
of the external
MOSFET and any external capacitance connected from
the GATE output pin to the GATE reference – GND or
source).
For the 3.3V outputs and 12V outputs (if no external 12VGATE
output capacitors are implemented), the following equation
is used to determine the output slew rate.
dV dt I
C
OUT
LIM 3V 12V
LOAD 3V 12V
Consequently, the overcurrent timer delay must be pro-
grammed to exceed the time it will take to charge the output
load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate Control)
The 3.3V outputs act as source followers. In this mode of
operation,V
SOURCE
= [V
GATE
– V
TH(ON)
] until the associated
output reaches 3.3V. The voltage on the gate of the MOSFET
TH(ON)
output reaches 3.3V. The voltage on the gate of the MOSFET
TH(ON)
will then continue to rise until it reaches 12V, which ensures
minimum R
DS(ON)
. Note that a delay exists between the ON
command to a slot and the appearance of voltage at the slot’s
DS(ON)
command to a slot and the appearance of voltage at the slot’s
DS(ON)
3.3V output. This delay is the time required to charge the
3VGATE output up to the threshold voltage of the external
MOSFET (typically about 3V).
t
C V
I
3VDLY
GATE GS(TH)
GATE(3VCHARGE)
The source (output) side of the external MOSFET will reach
the drain voltage in a time given by:
t t
C V
I
3V(SOURCE_DRAIN) 3VDLY
LOAD DRAIN
LIM(3V)
For the 12V outputs, each MOSFET is confi gured as a Miller
integrator (by virtue of C
MILLER
, which is connected between
the MOSFET’s gate and drain). In this confi guration, the
feedback action from drain to gate of the MOSFET causes
the voltage at the drain of the MOSFET to slew in a linear
fashion at a rate which satisfi es the following equation:
dv / dt(12V) I
C
GATE
MILLER
A delay exists between the ON command to a slot and the
appearance of voltage at the slot’s 12V output. For a slot’s
12V output, that delay is given by the time required for the
capacitor from the gate of the MOSFET to its source (typically
fi ve times the value of C
MILLER
) to charge to the threshold
voltage of the MOSFET (typically about 3V). In this instance,
the delay before the output voltage starts ramping can be
approximated by:
t
C V
I
VDLY
GATE(TOTAL) GS(TH)
GATE
12
where C
GATE(TOTAL)
is the sum of the C
GS
of the external
MOSFET, any external capacitance from the GATE output of
GATE(TOTAL)
MOSFET, any external capacitance from the GATE output of
GATE(TOTAL)
the MIC2592B to the source of the MOSFET, and C
MILLER
(external, if used).
Table 1 approximates the output slew-rate for various values
of C
GATE
when start-up is dominated by GATE capacitance
(external C
GATE
from GATE pin to ground plus C
GS
of the ex-
ternal MOSFET for the 3.3V rail; C
MILLER
for the 12V rail).
|
I
GATE
|
= 25µA
C
GATE
or C
MILLER
dv/dt (load)
0.01µF* 2.5V/ms
0.022µF* 1.136V/ms
0.047µF 0.532 V/ms
0.1µF 0.250V/ms
* Values in this range will be affected by the internal parasitic capaci-
tances of the MOSFETs used, and should be verifi ed experimentally.
Table 1. 3.3V and 12V Output Slew-Rate Selection for
Gate Capacitance Dominated Start-up
Power-Down Cycle
When one or more PCI slots are disabled via the MIC2592B
output control pins, ON[A/B] or AUXEN[A/B], the output volt-
age for each supply will discharge as a function of the RC
time constant produced by the controller’s internal resistance
(R
DIS
) connected to the output and the load capacitance
(C
LOAD
). The typical value of R
DIS
for each supply is listed
in the Electrical Characteristics Table. The charts below in
Figure 7 display curves of the fall time (90% - 10%) as a
function of the output load capacitance for both the 3V and
12V MAIN outputs.
0
200
400
600
800
1000
1200
0 5
0
0 5
0
0
0 500 5
100
150
200
250
LOAD CAPACITANCE (µF)
FALL TIME (ms)
3V Output Discharge as a
Function of Load Capacitance
0
200
400
600
800
1000
1200
0
0
0
0
500
1000
1500
2000
2500
LOAD CAPACITANCE (µF)
FALL TIME (ms)
12V Output Discharge as a
Function of Load Capacitance
Figure 7. 3V and 12V Output Discharge vs. Load
Capacitance
Standby Mode
Standby mode is entered when one or more of the MAIN
supply inputs (12VIN and/or 3VIN) is below its respective
UVLO threshold or OFF. The MIC2592B also supplies
3.3V auxiliary outputs (VAUX[A/B]), satisfying PCI Express
specifi cations. These outputs are fed via the VSTBY[A/B]
input pins and controlled by the AUXEN[A/B] input pins
or via their respective bits in the Control Registers. These
0.01µF* 2.5V/ms
0.022µF* 1.136V/ms
0.047µF 0.532 V/ms
0.1µF 0.250V/ms
dv/dt (load)
0.01µF* 2.5V/ms
0.022µF* 1.136V/ms
0.047µF 0.532 V/ms
0.1µF 0.250V/ms
MIC2592B Micrel
March 2005 18
M9999-033105
VSTBY
4.99 k
/PWRGD[A/B]
AUXEN[A/B](1)
ON[A/B](1)
FORCE_ON[A/B](1)
(1) External pin
(2) CNTRL[A/B] Register Bit D[0]
(3) Internal flag
(4) CNTRL[A/B] Register Bit D[1]
(5) CNTRL[A/B] Register Bit D[2]
MAIN[A/B](4)
VAUX[A/B](2)
3VAUX_UV[A/B](3)
FORCE_EN[A/B](5)
12VOUT_UV[A/B](3)
3VOUT_UV[A/B](3)
Figure 8. /PWRGD[A/B] Logic Diagram
outputs are independent of the MAIN outputs (12VIN[A/B]
and 3VIN[A/B]). Should the MAIN supply inputs move
below their respective UVLO thresholds, VAUX[A/B] will
still function as long as VSTBY[A/B] is present. Prior to
standby mode, ONA and ONB (or the Control Registers'
MAINA and MAINB bits) inputs should be deasserted or
the MIC2592B will assert /FAULT[A/B] and /INT (if inter-
rupts are enabled) output signals, if an undervoltage condi-
tion on the MAIN supply inputs is detected.
Circuit Breaker Function
The MIC2592B provides an electronic circuit breaker func-
tion that protects against excessive loads, such as short
circuits, at each supply. When the current from one or more
of a slot’s MAIN outputs exceeds the current limit threshold
(I
LIM
= 50mV/R
SENSE
) for a duration greater than t
FLT
, the
FLT
, the
FLT
circuit breaker is tripped and both MAIN supplies (all outputs
except VAUX[A/B]) are shut off. Should the load current cause
a MAIN output’s V
SENSE
to exceed V
THFAST
, the outputs are
THFAST
, the outputs are
THFAST
immediately shut off with no delay. Undervoltage conditions
on the MAIN supply inputs also trip the circuit breaker, but
only when the MAIN outputs are enabled (to signal a supply
input brown-out condition).
The VAUX[A/B] outputs have a different circuit-breaker func-
tion. The VAUX[A/B] circuit breakers do not incorporate a
fast-trip detector, instead they regulate the output current into
a fault to avoid exceeding their operating current limit. The
circuit breaker will trip due to an overcurrent on VAUX[A/B]
when the fault timer expires. This use of the t
FLT
timer pre-
FLT timer pre-
FLT
vents the circuit breaker from tripping prematurely due to
brief current transients.
Following a fault condition, the outputs can be turned on
again via the ON inputs (if the fault occurred on one of the
MAIN outputs), via the AUXEN inputs (if the fault occurred
on the AUX outputs), or by cycling both ON and AUXEN (if
faults occurred on both the MAIN and AUX outputs). A fault
condition can alternatively be cleared under SMI control of
the ENABLE bits in the CNTRL[A/B] registers (see Register
Bits D[1:0]). When the circuit breaker trips, /FAULT[A/B] will
be asserted if the outputs were enabled through the Hot-Plug
Interface inputs. At the same time, /INT will be asserted (un-
less interrupts are masked). Note that /INT is deasserted by
writing a Logic 1 back into the respective fault bit position(s)
in the STAT[A/B] register or the Common Status Register.
The response time (t
FLT
) of the MIC2592B’s primary overcur-
rent detector is set by external capacitors at the CFILTER[A/B]
pins to GND. For Slot A, CFILTER[A] is located at Pin 2; for
Slot B, CFILTER[B] is located at Pin 35. For a given response
time, the value for C
FILTER[A/B]
is given by:
C F t ms I A
V V 10
FILTER[A/B]
FLT A B FILTER
FILTER 3
where t
FLT[A/B]
is the desired response time and quantities
I
FILTER
and V
FLT[A/B]
and V
FLT[A/B]
FILTER
are specifi ed in the MIC2592B’s “Electri-
cal Characteristics” table.
For applications that require a more accurate response
time for a given C
FILTER[A/B]
tolerance, the MIC2592B
employs a patent-pending technique that improves re-
FILTER[A/B]
employs a patent-pending technique that improves re-
FILTER[A/B]
sponse time accuracy by more than a factor of two. A
110kΩ, 1% resistor connected from the MIC2592B’s
RFILTER[A&B] pin (Pin 20) to GND can be used. In this
case, the value for C
FILTER[A/B]
for a desired response time
(t
FLT
) is given by:
C F t ms
R k SF
FILTER[A/B] FLT
FILTER[A&B]
where t
FLT
is the desired response time, R
FILTER[A&B]
is 110k
Ω
, and “SF” is the CFILTER[A/B] response time
FILTER[A&B]
, and “SF” is the CFILTER[A/B] response time
FILTER[A&B]
“Scaling Factor” in the “Electrical Characteristics” table.
March 2005 19
M9999-033105
MIC2592B Micrel
Thermal Shutdown
The internal VAUX[A/B] MOSFETs are protected against
damage not only by current limiting, but by dual-mode
overtemperature protection as well. Each slot controller on
the MIC2592B is thermally isolated from the other. Should
an overcurrent condition raise the junction temperature of
one slot’s controller and pass elements to 140°C, all of the
outputs for that slot (including VAUX) will be shut off and
the slot’s /FAULT output will be asserted. The other slot’s
operating condition will remain unaffected. However, should
the MIC2592B’s die temperature exceed 160°C, both slots
(all outputs, including VAUXA and VAUXB) will be shut off,
whether or not a current limit condition exists. A 160°C over-
temperature condition additionally sets the overtemperature
bit (OT_INT) in the Common Status Register.
/PWRGD[A/B] Outputs
The MIC2592B has two /PWRGD outputs, one for each slot.
These are open-drain, active-low outputs that require an
external pull-up resistor to V
STBY
. Each output is asserted
STBY
. Each output is asserted
STBY
when a slot has been enabled and has successfully begun
delivering power to its respective +12V, +3.3V, and VAUX
outputs. An equivalent logic diagram for /PWRGD[A/B] is
shown in Figure 8.
/FORCE_ON[A/B] Inputs
These level-sensitive, active-low inputs are provided to
facilitate designing systems using the MIC2592B. Asserting
/FORCE_ON[A/B] will turn on all three of the respective slot’s
outputs (+12V, +3.3V, and VAUX), while specifi cally defeating
all protections for those outputs. This explicitly includes all
overcurrent and short circuit protections, and on-chip thermal
protection for the VAUX supplies. Additionally, asserting a
slot’s /FORCE_ON[A/B] input will disable all of its input and
output UVLO protections, with the sole exception of that as-
serting either or both of the /FORCE_ON[A/B] inputs will
not
disable the VSTBY[A/B] input UVLO.
Asserting /FORCE_ON[A/B] will cause the respective slot’s
/PWRGD[A/B] and /FAULT[A/B] outputs to enter their open-
drain state. Additionally, there are two SMBus accessible
register bits (see CNTRL[A/B] Register Bit D[2]), which can
be set to disable the corresponding slot’s /FORCE_ON[A/B]
pins. This allows system software to prevent these hardware
overrides from being inadvertently activated during normal
use. If not used, each pin should be connected to V
STBY
using
STBY using
STBY
an external pull-up resistor. See Figure 6 for details.
General Purpose Input (GPI) Pins
Two pins on the MIC2592B are available for use as GPI
pins. The logic state of each of these pins can be determined
by polling Bits [4:5] of Common Status Register. Both of
these inputs are compliant to 3.3V. If unused, connect each
GPI_[A0/B0] pin to GND.
Hot-Plug Interface (HPI)
Once the input supplies are above their respective UVLO
thresholds, the Hot-Plug Interface can be utilized for power
control by enabling the control input pins (AUXEN[A/B] and
ON[A/B]) for each slot. In order for the MIC2592B to switch
on the VAUX supply for either slot, the AUXEN[A/B] control
must be enabled after the power-on-reset delay, t
POR
(typi-
cally, 250
µ
s), has elapsed. The timing response diagram of
Figure 9 illustrates a Hot-Plug Interface operation where an
overcurrent fault is detected by the MIC2592B controller
after initiating a power-up sequence. The MAIN (+12V &
+3.3V) and VAUX[A/B] supply rails, /FAULT, /PWRGD and
/INT output responses for both AUX and MAIN are shown
in the fi gure.
System Management Interface (SMI)
The MIC2592B’s System Management Interface uses the
Read_Byte and Write_Byte subset of the SMBus protocols
to communicate with its host via the System Management
Interface bus. The /INT output signals the controlling proces-
sor that one or more events need attention, if an interrupt-
driven architecture is used. Note that the MIC2592B does
not participate in the SMBus Alert Response Address (ARA)
portion of the SMBus protocol.
Fault Reporting and Interrupt Generation
SMI-only Control Applications
In applications where the MIC2592B is controlled only by
the SMI, ON[A/B] and AUXEN[A/B] are connected to GND
and the /FORCE_ON[A/B] pins are connected to V
STBY
as
STBY as
STBY
shown in Figure 6. In this case, the MIC2592B’s /FAULT[A/B]
outputs and STAT[A/B] Register Bit D[7] (FAULT[A/B])
are not activated as fault status is determined by polling
STAT[A/B] Register Bits D[4], D[2], D[0] and CS (Common
Status) Register Bits D[2:1]. Individual fault bits in STAT[A/B]
and CS registers are asserted after power-on-reset when:
• Either or both CNTRL[A/B] Register Bits D[1:0] are
asserted, AND
• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-
age is lower than its respective ULVO threshold,
OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its fi lter timeout has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature > 140°C, OR
• The MIC2592B’s global die temperature > 160°C
To clear any one or all STAT[A/B] Register Bits D[4], D[2], D[0]
and/or CS Register Bits D[2], D[1] once asserted, a software
subroutine can perform an “echo reset” where a Logical “1” is
written back to those register bit locations that have indicated
a fault. This method of “echo reset” allows data to be retained
in the STAT[A/B] and/or CS registers until such time as the
system is prepared to operate on that data.
The MIC2592B can operate in interrupt mode or polled mode.
For interrupt-mode operation, the open-drain, active-LOW
/INT output signal is activated after power-on-reset if the
INTMSK bit (CS Register Bit D[3]) has been reset to Logical
“0”. Once activated, the /INT output is asserted by any one
of the fault conditions listed above and deasserted when
one or all STAT[A/B] Register Bits D[4], D[2], D[0] and/or CS
Register Bits D[2], D[1] are reset upon the execution of an
SMBus “echo reset” WRITE_BYTE cycle. For polled-mode
operation, the INTMSK bit should be set to Logical “1,” thereby
inhibiting /INT output pin operation.
For those SMI-control applications where the /FORCE_ON[A/B]
MIC2592B Micrel
March 2005 20
M9999-033105
S 1 0 0 0
A2 A1 A0
0 A 0 0 0 0 0 0 X X A
D4D5D6 D3 D2 D1 D0D7
A P
MIC2592B Device Address
DATA
CLK
Command Byte to MIC2592B Data Byte to MIC2592B
START STOP
R/W = WRITE ACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE
Master to device transfer,
i.e., DATA driven by master.
Device to master transfer,
i.e., DATA driven by device.
Figure 10. WRITE_BYTE Protocol
S 1 0 0 0 A2 A1 A0 A2 A1 A00 A 0 0 0 0 0 0 X X A S 1 0 10 0
D4D5D6 D3 D2 D1 D0
A
D7
/A P
MIC2592B Device Address
DATA
CLK
Command Byte to MIC2592B MIC2592B Device Address Data Read From MIC2592B
START START STOP
R/W = WRITE R/W = READACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE NOT ACKNOWLEDGE
Master to device transfer,
i.e., DATA driven by master.
Device to master transfer,
i.e., DATA driven by device.
Figure 11. READ_BYTE Protocol
S 1 0 0 0
A2 A1 A0
1 A
D4D5D6 D3 D2 D1 D0D7
/A P
MIC2592B Device Address
DATA
CLK
Byte Read from MIC2592B
START STOP
R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE
Master to device transfer,
i.e., DATA driven by master.
Device to master transfer,
i.e., DATA driven by device.
Figure 12. RECEIVE_BYTE Protocol
/INT*
/FAULT_[A/B]
I3VOUT[A/B]
3VOUT[A/B]
IAUX_OUT[A/B]
VAUX_OUT[A/B]
AUXEN[A/B]
0
0
VIH VIH
VIL
VIH
ILIM(3V)
ISTEADY-STATE
ON[A/B]
0
0
0
0
0
0
0
VIH
VIL
+3.3V
tPOR
VSTBY
UVLO
tFLT
tFLT
ILIM(AUX)
ISTEADY-STATE
0
0
* *
* /INT de-asserted by software
12VOUT[A/B]
/PWRGD_[A/B]
Figure 9. Hot-Plug Interface Operation
March 2005 21
M9999-033105
MIC2592B Micrel
MIC2592B Register Set and Programmer’s Model
Target Register Command Byte Value Power-On
Default
Label Description Read Write
CNTRLA Control Register Slot A 02
h
02
h
00
h
CNTRLB Control Register Slot B 03
h
03
h
00
h
STATA Slot A Status 04
h
04
h
00
h
STATB Slot B Status 05
h
05
h
00
h
CS Common Status Register 06
h
06
h
xxxx 0000
b
Reserved Reserved / Do Not Use 07h - FF
h
07h - FF
h
Undefi ned
Table 2. MIC2592B Register Addresses
Label Description Read Write
CNTRLA Control Register Slot A 02
CNTRLB Control Register Slot B 03
STATA Slot A Status 04
STATB Slot B Status 05
CS Common Status Register 06
Reserved Reserved / Do Not Use 07h - FF
Target Register Command Byte Value Power-On
Default
Label Description Read Write
CNTRLA Control Register Slot A 02
CNTRLB Control Register Slot B 03
STATA Slot A Status 04
STATB Slot B Status 05
CS Common Status Register 06
Reserved Reserved / Do Not Use 07h - FF
Label Description Read Write
02
03
04
05
06
07h - FF
Target Register Command Byte Value Power-On
Default
00
00
00
00
xxxx 0000
Undefi ned
h
h
Default
Label Description Read Write
CNTRLA Control Register Slot A 02
CNTRLB Control Register Slot B 03
STATA Slot A Status 04
STATB Slot B Status 05
CS Common Status Register 06
Reserved Reserved / Do Not Use 07h - FF
Inputs MIC2592B Device Address
A2 A1 A0 Binary Hex
0 0 0 1000 000X*
b
80
h
0 0 1 1000 001X
b
82
h
0 1 0 1000 010X
b
84
h
0 1 1 1000 011X
b
86
h
1 0 0 1000 100X
b
88
h
1 0 1 1000 101X
b
8A
h
1 1 0 1000 110X
b
8C
h
1 1 1 1000 111X
b
8E
h
* Where X = "1" for READ and "0" for Write
Table 3. MIC2592B SMBus Addressing
Inputs MIC2592B Device Address
A2 A1 A0 Binary Hex
0 0 0 1000 000X*
0 0 1 1000 001X
0 1 0 1000 010X
0 1 1 1000 011X
1 0 0 1000 100X
1 0 1 1000 101X
1 1 0 1000 110X
1 1 1 1000 111X
A2 A1 A0 Binary Hex
0 0 0 1000 000X*
0 0 1 1000 001X
0 1 0 1000 010X
0 1 1 1000 011X
1 0 0 1000 100X
1 0 1 1000 101X
1 1 0 1000 110X
1 1 1 1000 111X
A2 A1 A0 Binary Hex
0 0 0 1000 000X*
0 0 1 1000 001X
0 1 0 1000 010X
0 1 1 1000 011X
1 0 0 1000 100X
1 0 1 1000 101X
1 1 0 1000 110X
1 1 1 1000 111X
A2 A1 A0 Binary Hex
80
82
84
86
88
8A
8C
8E
inputs are needed for diagnostic purposes, the
/FORCE_ON[A/B] inputs must be enabled; that is, CNTRL[A/B]
Register Bit D[2] should read Logical “0.” Once /FORCE_ON[A/B]
inputs are asserted, all output voltages are present with all
circuit protection features disabled, including overtemperature
protection on VAUX[A/B] outputs. To inhibit /FORCE_ON[A/B]
operation, a Logical “1” shall be written to the CNTRL[A/B]
Register Bit D[2] location(s).
HPI-only Control Applications
In applications where the MIC2592B is controlled only by the
HPI, SMBus signals SCL, SDA, and /INT signals are con-
nected to V
STBY
as shown in Figure 6. In this confi guration,
STBY as shown in Figure 6. In this confi guration,
STBY
the MIC2592B’s /FAULT[A/B] outputs are activated after
power-on-reset and become asserted when:
Either or both external ON[A/B] and AUXEN[A/B] input signals
are asserted, AND
• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-
age is lower than its respective ULVO threshold,
OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its fi lter timeout[A/B] has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature > 140°C, OR
• The MIC2592B’s global die temperature > 160°C
In order to clear /FAULT[A/B] outputs once asserted, either
or both ON[A/B] and AUXEN[A/B] input signals must be
deasserted. Please see /FAULT[A/B] pin description for ad-
ditional information.
If the /FORCE_ON[A/B] inputs are used for diagnostic pur-
poses, both /FAULT[A/B] and /PWRGD[A/B] outputs are
deasserted once /FORCE_ON[A/B] inputs are asserted.
Serial Port Operation
The MIC2592B uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host. The
SMBus Write_Byte operation involves sending the device’s
target address, with the R/W bit (LSB) set to the low (write)
state, followed by a command byte and a data byte. The SMBus
Read_Byte operation is similar, but is a composite write and
read operation: the host fi rst sends the device’s target address
followed by the command byte, as in a write operation. A new
“Start” bit must then be sent to the MIC2592B, followed by a
repeat of the device address with the R/W bit set to the high
(read) state. The data to be read from the part may then be
clocked out. There is one exception to this rule: If the location
latched in the pointer register from the last
write
operation is
known to be correct (i.e., points to the desired register within
the MIC2592B), then the “Receive_Byte” procedure may be
used. To perform a Receive_Byte operation, the host sends
an address byte to select the target MIC2592B, with the R/W
bit set to the high (read) state, and then retrieves the data
byte. Figures 10 through 12 show the formats for these data
read and data write procedures.
The Command Register is eight bits (one byte) wide. This
byte carries the address of the MIC2592B’s register to be
operated upon. The command byte values corresponding to
the various MIC2592B register addresses are shown in Table
2. Command byte values other than 0000 0XXX
b
= 00
h
– 07
h
are reserved and should not be used.
MIC2592B SMBus Address Confi guration
The MIC2592B responds to its own unique SMBus address,
which is assigned using A2, A1, and A0. These represent
the 3 LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power up of the
VSTBY[A/B] supply input. These address bits allow up to
eight MIC2592B devices in a single system. These pins are
either grounded or left unconnected to specify a logical 0 or
logical 1, respectively. A pin designated as a logical 1 may
also be pulled up to V
STBY
.
STBY
.
STBY
MIC2592B Micrel
March 2005 22
M9999-033105
Detailed Register Descriptions
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
Control Register, Slot A (CNTRLA)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
ENABLE
Bit(s) Function Operation
AUXAPG AUX output power-good status, Slot A 1 = Power-is-Good
(VAUXA Output is above its UVLO threshold)
MAINAPG MAIN output power-good status, Slot A 1 = Power-is-Good
(MAINA Outputs are above their UVLO
thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
/FORCE_A Allows or inhibits the operation of the /FORCE_ONA 0 = /FORCE_ONA is enabled
ENABLE input pin 1 = /FORCE_ONA is disabled
MAINA MAIN enable control, Slot A 0 = Off, 1 = On
VAUXA VAUX enable control, Slot A 0 = Off, 1 = On
Power-Up Default Value: 0000 0000b = 00h
Read Command_Byte Value (R/W): 0000 0010b = 02h
The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.
Notes:
1.
The state of the /PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when /FORCE_ONA is asserted. If
/FORCE_ONA is asserted (the pin is pulled low), and /FORCE_AENABLE is set to a logic zero, the /PWRGDA pin will be unconditionally forced to
its open-drain (“Power Not Good”) state.
Bit(s) Function Operation
AUXAPG AUX output power-good status, Slot A 1 = Power-is-Good
(VAUXA Output is above its UVLO threshold)
MAINAPG MAIN output power-good status, Slot A 1 = Power-is-Good
(MAINA Outputs are above their UVLO
thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
/FORCE_A Allows or inhibits the operation of the /FORCE_ONA 0 = /FORCE_ONA is enabled
ENABLE input pin 1 = /FORCE_ONA is disabled
MAINA MAIN enable control, Slot A 0 = Off, 1 = On
VAUXA VAUX enable control, Slot A 0 = Off, 1 = On
Bit(s) Function Operation
AUXAPG AUX output power-good status, Slot A 1 = Power-is-Good
(VAUXA Output is above its UVLO threshold)
MAINAPG MAIN output power-good status, Slot A 1 = Power-is-Good
(MAINA Outputs are above their UVLO
thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
/FORCE_A Allows or inhibits the operation of the /FORCE_ONA 0 = /FORCE_ONA is enabled
ENABLE input pin 1 = /FORCE_ONA is disabled
MAINA MAIN enable control, Slot A 0 = Off, 1 = On
VAUXA VAUX enable control, Slot A 0 = Off, 1 = On
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXAPG MAINAPG Reserved Reserved Reserved /FORCE_A MAINA VAUXA
March 2005 23
M9999-033105
MIC2592B Micrel
Control Register, Slot B (CNTRLB)
8-Bits, Read/Write
Control Register, Slot B (CNTRLB)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
ENABLE
Bit(s) Function Operation
AUXBPG AUX output power-good status, Slot B 1 = Power-is-Good
(VAUXB Output is above its UVLO threshold)
MAINBPG MAIN output power-good status, Slot B 1 = Power-is-Good
(MAINB Outputs are above their UVLO
thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
/FORCE_B Allows or inhibits the operation of the /FORCE_ONB 0 = /FORCE_ONB is enabled
ENABLE input pin 1 = /FORCE_ONB is disabled
MAINB MAIN enable control, Slot B 0 = Off, 1 = On
VAUXB VAUX enable control, Slot B 0 = Off, 1 = On
Power-Up Default Value: 0000 0000b = 00h
Command_Byte Value (R/W): 0000 0011b = 03h
The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.
Notes:
1. The state of the /PWRGDB pin is the logical AND of the values of the AUXBPG and the MAINBPG bits, except when /FORCE_ONB is asserted. If
/FORCE_ONB is asserted (the pin is pulled low), and /FORCE_BENABLE is set to a logic zero, the /PWRGDB pin will be unconditionally forced to
its open-drain (“Power Not Good”) state.
Bit(s) Function Operation
AUXBPG AUX output power-good status, Slot B 1 = Power-is-Good
(VAUXB Output is above its UVLO threshold)
MAINBPG MAIN output power-good status, Slot B 1 = Power-is-Good
(MAINB Outputs are above their UVLO
thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
/FORCE_B Allows or inhibits the operation of the /FORCE_ONB 0 = /FORCE_ONB is enabled
ENABLE input pin 1 = /FORCE_ONB is disabled
MAINB MAIN enable control, Slot B 0 = Off, 1 = On
VAUXB VAUX enable control, Slot B 0 = Off, 1 = On
Bit(s) Function Operation
AUXBPG AUX output power-good status, Slot B 1 = Power-is-Good
(VAUXB Output is above its UVLO threshold)
MAINBPG MAIN output power-good status, Slot B 1 = Power-is-Good
(MAINB Outputs are above their UVLO
thresholds)
D[5] Reserved Always read as zero
D[4] Reserved Always read as zero
D[3] Reserved Always read as zero
/FORCE_B Allows or inhibits the operation of the /FORCE_ONB 0 = /FORCE_ONB is enabled
ENABLE input pin 1 = /FORCE_ONB is disabled
MAINB MAIN enable control, Slot B 0 = Off, 1 = On
VAUXB VAUX enable control, Slot B 0 = Off, 1 = On
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
ENABLE
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read only read only read-only read/write read/write read/write
AUXBPG MAINBPG Reserved Reserved Reserved /FORCE_B MAINB VAUXB
MIC2592B Micrel
March 2005 24
M9999-033105
Status Register Slot A (STATA)
8-Bits, Read-Only
Status Register, Slot A (STATA)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
Bit(s) Function Operation
FAULTA FAULT Status - Slot A 1 = Fault pin asserted
(/FAULTA pin is LOW)
0 = Fault pin deasserted
(/FAULTA pin is HIGH)
See Notes 1, 2, and 3.
MAINA MAIN Enable Status - Slot A Represents the actual state (on/off) of the
two Main Power outputs for Slot A
(+12V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
VAUXA VAUX Enable Status - Slot A Represents the actual state (on/off) of the
Auxiliary Power output for Slot A
1 = AUX Power ON
0 = AUX Power OFF
VAUXAF Overcurrent Fault: VAUXA supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VAF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
D[1] Reserved Always read as zero
3VAF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault
Power-Up Default Value: 0000 0000b = 00h
Command_Byte Value (R/W): 0000 0100b = 04h
The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an
overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The
status of the /FAULTA pin is not affected by reading the Status Register or by clearing active status bits.
Notes:
1. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA.
If FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset
FAULTA.
2. Neither the FAULTA bits nor the /FAULTA pins are active when the MIC2592B power paths are controlled by the System Management Interface.
When using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.
Bit(s) Function Operation
FAULTA FAULT Status - Slot A 1 = Fault pin asserted
(/FAULTA pin is LOW)
0 = Fault pin deasserted
(/FAULTA pin is HIGH)
See Notes 1, 2, and 3.
MAINA MAIN Enable Status - Slot A Represents the actual state (on/off) of the
two Main Power outputs for Slot A
(+12V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
VAUXA VAUX Enable Status - Slot A Represents the actual state (on/off) of the
Auxiliary Power output for Slot A
1 = AUX Power ON
0 = AUX Power OFF
VAUXAF Overcurrent Fault: VAUXA supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VAF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
D[1] Reserved Always read as zero
3VAF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault
Bit(s) Function Operation
FAULTA FAULT Status - Slot A 1 = Fault pin asserted
(/FAULTA pin is LOW)
0 = Fault pin deasserted
(/FAULTA pin is HIGH)
See Notes 1, 2, and 3.
MAINA MAIN Enable Status - Slot A Represents the actual state (on/off) of the
(+12V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
VAUXA VAUX Enable Status - Slot A Represents the actual state (on/off) of the
1 = AUX Power ON
0 = AUX Power OFF
VAUXAF Overcurrent Fault: VAUXA supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VAF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
D[1] Reserved Always read as zero
3VAF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTA MAINA VAUXA VAUXAF Reserved 12VAF Reserved 3VAF
FAULTA FAULT Status - Slot A 1 = Fault pin asserted
(/FAULTA pin is LOW)
0 = Fault pin deasserted
(/FAULTA pin is HIGH)
See Notes 1, 2, and 3.
MAINA MAIN Enable Status - Slot A Represents the actual state (on/off) of the
two Main Power outputs for Slot A
(+12V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
VAUXA VAUX Enable Status - Slot A Represents the actual state (on/off) of the
Auxiliary Power output for Slot A
1 = AUX Power ON
0 = AUX Power OFF
VAUXAF Overcurrent Fault: VAUXA supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VAF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
MAINA MAIN Enable Status - Slot A Represents the actual state (on/off) of the
VAUXA VAUX Enable Status - Slot A Represents the actual state (on/off) of the
March 2005 25
M9999-033105
MIC2592B Micrel
Status Register Slot B (STATB)
8-Bits, Read-Only
Status Register, Slot B (STATB)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
Bit(s) Function Operation
FAULTB FAULT Pin Status - Slot B 1 = Fault pin asserted
(/FAULTB pin is LOW)
0 = Fault pin deasserted
(/FAULTB pin is HIGH)
See Notes 1, 2, and 3.
MAINB MAIN Enable Status - Slot B Represents the actual state (on/off) of the
four Main Power outputs for Slot B
(+12V and +3.3V)
1 = MAIN Power ON
0 = MAIN Power OFF
VAUXB VAUX Enable Status - Slot B Represents the actual state (on/off) of the
Auxiliary Power output for Slot B
1 = AUX Power ON
0 = AUX Power OFF
VAUXBF Overcurrent Fault: VAUXB supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VBF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
D[1] Reserved Always read as zero
3VBF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault
Power-Up Default Value: 0000 0000b = 00h
Command_Byte Value (R/W): 0000 0101b = 05h
The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an
overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /INT. The
status of the /FAULTB pin is not affected by reading the Status Register or by clearing active status bits.
Notes:
1. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB.
If FAULTB has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to reset
FAULTB.
2. Neither the FAULTB bits nor the /FAULTB pins are active when the MIC2592B power paths are controlled by the System Management Interface.
When using SMI power path control, the AUXENB and ONB pins for that slot must be tied to GND.
3:. If /FORCE_ONB is asserted (low), the /FAULTB pin will be unconditionally forced to its open-drain state. Note, though, that the value in the FAULTB
Bit(s) Function Operation
FAULTB FAULT Pin Status - Slot B 1 = Fault pin asserted
(/FAULTB pin is LOW)
0 = Fault pin deasserted
(/FAULTB pin is HIGH)
See Notes 1, 2, and 3.
MAINB MAIN Enable Status - Slot B Represents the actual state (on/off) of the
four Main Power outputs for Slot B
(+12V and +3.3V)
1 = MAIN Power ON
0 = MAIN Power OFF
VAUXB VAUX Enable Status - Slot B Represents the actual state (on/off) of the
Auxiliary Power output for Slot B
1 = AUX Power ON
0 = AUX Power OFF
VAUXBF Overcurrent Fault: VAUXB supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VBF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
D[1] Reserved Always read as zero
3VBF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault
Bit(s) Function Operation
FAULTB FAULT Pin Status - Slot B 1 = Fault pin asserted
(/FAULTB pin is LOW)
0 = Fault pin deasserted
(/FAULTB pin is HIGH)
See Notes 1, 2, and 3.
MAINB MAIN Enable Status - Slot B Represents the actual state (on/off) of the
four Main Power outputs for Slot B
(+12V and +3.3V)
1 = MAIN Power ON
0 = MAIN Power OFF
VAUXB VAUX Enable Status - Slot B Represents the actual state (on/off) of the
Auxiliary Power output for Slot B
1 = AUX Power ON
0 = AUX Power OFF
VAUXBF Overcurrent Fault: VAUXB supply 1 = Fault 0 = No fault
D[3] Reserved Always read as zero
12VBF Overcurrent Fault: +12V supply 1 = Fault 0 = No fault
D[1] Reserved Always read as zero
3VBF Overcurrent Fault: 3.3V supply 1 = Fault 0 = No fault
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read-only read/write read-only read/write
FAULTB MAINB VAUXB VAUXBF Reserved 12VBF Reserved 3VBF
MIC2592B Micrel
March 2005 26
M9999-033105
Common Status Register (CS)
8-Bits, Read/Write
Common Status Register (CS)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
Bit(s) Function Operation
D[7] Reserved Always read as zero
D[6] Reserved Always read as zero
GPI_B0 General Purpose Input 0, Slot B State of GPI_B0 pin
GPI_A0 General Purpose Input 0, Slot A State of GPI_A0 pin
INTMSK Interrupt Mask 0 = /INT generation is enabled
1 = /INT generation is disabled. The
MIC2592B does not participate in the SMBus
Alert Response Address (ARA) protocol
UV_INT Undervoltage Interrupt 0 = No UVLO fault
1 = UVLO fault
Set whenever a circuit breaker fault condition
occurs as a result of an undervoltage lockout
condition on one of the main supply inputs.
This bit is only set if a UVLO condition occurs
while the ON[A/B] pin is asserted or the
MAIN[A/B] control bits are set
OT_INT Overtemperature Interrupt 0 = Die Temp < 160°C.
1 = Fault: Die Temp > 160°C.
Set if a fault occurs as a result of the
MIC2592B’s die temperature exceeding
160°C
D[0] Reserved Undefi ned
Power-Up Default Value: 00000000b = 00h
Command_Byte Value (R/W): 00000110b = 06h
Bit(s) Function Operation
D[7] Reserved Always read as zero
D[6] Reserved Always read as zero
GPI_B0 General Purpose Input 0, Slot B State of GPI_B0 pin
GPI_A0 General Purpose Input 0, Slot A State of GPI_A0 pin
INTMSK Interrupt Mask 0 = /INT generation is enabled
1 = /INT generation is disabled. The
MIC2592B does not participate in the SMBus
Alert Response Address (ARA) protocol
UV_INT Undervoltage Interrupt 0 = No UVLO fault
1 = UVLO fault
Set whenever a circuit breaker fault condition
occurs as a result of an undervoltage lockout
condition on one of the main supply inputs.
This bit is only set if a UVLO condition occurs
while the ON[A/B] pin is asserted or the
MAIN[A/B] control bits are set
OT_INT Overtemperature Interrupt 0 = Die Temp < 160°C.
1 = Fault: Die Temp > 160°C.
Set if a fault occurs as a result of the
MIC2592B’s die temperature exceeding
160°C
D[0] Reserved Undefi ned
Bit(s) Function Operation
D[7] Reserved Always read as zero
D[6] Reserved Always read as zero
GPI_B0 General Purpose Input 0, Slot B State of GPI_B0 pin
GPI_A0 General Purpose Input 0, Slot A State of GPI_A0 pin
INTMSK Interrupt Mask 0 = /INT generation is enabled
1 = /INT generation is disabled. The
MIC2592B does not participate in the SMBus
Alert Response Address (ARA) protocol
UV_INT Undervoltage Interrupt 0 = No UVLO fault
1 = UVLO fault
Set whenever a circuit breaker fault condition
occurs as a result of an undervoltage lockout
condition on one of the main supply inputs.
This bit is only set if a UVLO condition occurs
while the ON[A/B] pin is asserted or the
MAIN[A/B] control bits are set
OT_INT Overtemperature Interrupt 0 = Die Temp < 160°C.
1 = Fault: Die Temp > 160°C.
Set if a fault occurs as a result of the
MIC2592B’s die temperature exceeding
160°C
D[0] Reserved Undefi ned
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved GPI_B0 GPI_A0 INTMSK UV_INT OT_INT Reserved
March 2005 27
M9999-033105
MIC2592B Micrel
Applications Information
Sense Resistor Selection
The 12V and the 3.3V supplies employ internal current sens-
ing circuitry to detect overcurrent conditions that may trip the
circuit breaker. An external sense resistor is used to monitor
the current that passes through the external MOSFET for
each slot of the 12V and 3.3V rails. The sense resistor is
nominally valued at:
RSENSE(NOM) =VTHILIMIT
ILIMIT
where V
THILIMIT
is the typical (or nominal) circuit breaker
THILIMIT is the typical (or nominal) circuit breaker
THILIMIT
threshold voltage (50mV) and I
LIMIT
is the nominal inrush
LIMIT is the nominal inrush
LIMIT
load current level to trip the internal circuit breaker.
To accommodate worse-case tolerances in the sense re-
sistor (for a ±1% initial tolerance, allow ±3% tolerance for
variations over time and temperature) and circuit breaker
threshold voltages, a slightly more detailed calculation must
be used to determine the minimum and maximum hot swap
load currents.
As the MIC2592B’s minimum current limit threshold voltage
is 45mV, the minimum hot swap load current is determined
where the sense resistor is 3% high:
ILIMIT(MIN) = =
45mV
(1.03 × RSENSE(NOM))
43.7mV
RSENSE(NOM)
Keep in mind that the minimum hot swap load current should
be greater than the application circuit’s upper steady-state
load current boundary. Once the lower value of R
SENSE
has
been calculated, it is good practice to check the maximum
hot swap load current (I
LIMIT(MAX)
) which the circuit may
let pass in the case of tolerance build-up in the opposite
LIMIT(MAX)
let pass in the case of tolerance build-up in the opposite
LIMIT(MAX)
direction. Here, the worse-case maximum is found using a
V
THILIMIT(MAX)
threshold of 55mV and a sense resistor 3%
low in value:
THILIMIT(MAX)
low in value:
THILIMIT(MAX)
ILIMIT(MAX) = =
55mV
(0.97 × RSENSE(NOM))
56.7mV
RSENSE(NOM)
In this case, the application circuits must be sturdy enough
to operate up to approximately 1.25x the steady-state hot
swap load currents. For example, if one of the 12V slots of the
MIC2592B circuit must pass a minimum hot swap load current
of 1.5A without nuisance trips, R
SENSE
should be set to:
RSENSE(NOM) = = 30mΩ
45mV
1.5A
where the nearest 1% standard value is 30.1mΩ. At the other
tolerance extremes, I
LIMIT(MAX)
for the circuit in question is
then simply:
ILIMIT(MAX) = = 1.88A
56.7mV
30.1mΩ
With a knowledge of the application circuit’s maximum hot
swap load current, the power dissipation rating of the sense
resistor can be determined using P = I
2
R. Here, the current
is I
LIMIT(MAX)
= 1.88A and the resistance R
SENSE(MAX)
=
(1.03)(R
LIMIT(MAX)
(1.03)(R
LIMIT(MAX)
SENSE(NOM)
) = 31.00mΩ. Thus, the sense resistor’s
SENSE(MAX)
) = 31.00mΩ. Thus, the sense resistor’s
SENSE(MAX)
maximum power dissipation is:
SENSE(NOM)
maximum power dissipation is:
SENSE(NOM)
P
MAX
= (1.88A)
2
X (31.00mΩ) = 0.110W
A 0.25W sense resistor is a good choice in this application.
PCB Layout Suggestions and Hints
4-Wire Kelvin Sensing
Because of the low value required for the sense resistor,
special care must be used to accurately measure the volt-
age drop across it. Specifi cally, the measurement technique
across R
SENSE
must employ 4-wire Kelvin sensing. This is
simply a means of ensuring that any voltage drops in the
power traces connected to the resistors are not picked up
by the signal conductors measuring the voltages across the
sense resistors.
Figure 13 illustrates how to implement 4-wire Kelvin sensing.
As the fi gure shows, all the high current in the circuit (from
V
IN
through R
SENSE
and then to the drain of the N-channel
power MOSFET) fl ows directly through the power PCB traces
and through R
SENSE
. The voltage drop across R
SENSE
is
sampled in such a way that the high currents through the
power traces will not introduce signifi cant parasitic voltage
drops in the sense leads. It is recommended to connect
the hot swap controller’s sense leads directly to the sense
resistor’s metalized contact pads. The Kelvin sense signal
traces should be symmetrical with equal length and width,
kept as short as possible, and isolated from any noisy signals
and planes.
Additionally, for designs that implement Kelvin sense con-
nections that exceed 1" in length and/or if the Kelvin (signal)
traces are vulnerable to noise possibly being injected onto
these signals, the example circuit shown in Figure 14 can
be implemented to combat noisy environments. This circuit
implements a 1.6 MHz low-pass fi lter to attenuate higher
frequency disturbances on the current sensing circuitry.
However, individual system analysis should be used to de-
termine if fi ltering is necessary and to select the appropriate
cutoff frequency for each specifi c application.
Other Layout Considerations
Figure 15 is a suggested PCB layout diagram for the MIC2592B
power traces, Kelvin sense connections, and capacitor com-
ponents. In this illustration, only the 12V Slot B is shown but
a similar approach is suggested for both slots of each Main
power rail (12V and 3.3V). Many hot swap applications will
require load currents of several amperes. Therefore, the
power (12VIN and Return, 3VIN and Return) trace widths
(W) need to be wide enough to allow the current to fl ow while
the rise in temperature for a given copper plate (e.g., 1oz.
or 2oz.) is kept to a maximum of 10°C to 25°C. The return
(or power ground) trace should be the same width as the
positive voltage power traces (input/load) and isolated from
any ground and signal planes so that the controller’s power
is common mode. Also, these traces should be as short as
possible in order to minimize the IR drops between the input
and the load. As indicated in the Pin Description section, an
external connection must be made that ties together both
channel inputs ((+) Kelvin sense) of each Main power rail (i.e.,
3VINA and 3VINB, 12VINA and 12VINB must be externally
connected). These connections should be implemented di-
rectly at the chip. Insure that the voltage drop between the
two (+) Kelvin sense inputs for each rail is no greater than
0.2mV by using a common power path for the two inputs
MIC2592B Micrel
March 2005 28
M9999-033105
(e.g., 12VINA, 12VINB). Finally, the use of plated-through
vias will be necessary to make circuit connection to the power,
ground, and signal planes on multi-layer PCBs.
RSENSE
Power Trace
From VIN
PCB Track Width:
0.03" per Ampere
using 1oz Cu
Power Trace
To MOSFET Drain
Signal Trace
to MIC2592B VIN Pin
Signal Trace
to MIC2592B SENSE Pin
Note: Each SENSE lead trace shall be
balanced for best performance & equal
length/equal aspect ratio.
RSENSE metalized
contact pads
Figure 13. 4-Wire Kelvin Sense Connections for
R
SENSE
SENSEVIN
1kΩ
RSENSE
MIC2592B
Controller
100pF
High-current
power traces To the external
MOSFET and load
To the input
power supply
Figure 14. Current Limit Sense Filter for Noisy Sys-
tems
March 2005 29
M9999-033105
MIC2592B Micrel
*POWER MOSFET
(SO-8)
*SENSE RESISTOR
W
W
Current Flow
to the Load
Current Flow
to the Load
W
Current Flow
from the Load
Via to GND Plane
Via to signal plane
(GATE pin connection)
**R4
15
**CGS
**CMILLER
- DRAWING IS NOT TO SCALE AND NOT ALL PINS SHOWN FOR CLARITY-
*See Table 4 for part numbers and vendors
**Optional components
***Recommended components (variable in value, see Functional Description and Applications Information)
Trace width (W) guidelines given in "PCB Layout Recommendations" section of the datasheet
12V(Slot B) is illustrated in this example. A similar layout is suggested for the 3V supply and both slots
MIC2592B
25
26
27
28
30
31
32
17
3VINB
CFILTERB
/PWRGD
/FAULTB
GND
GND
VSTBYB
12VOUTB
/FORCE_ONB
N/C
12VGATEB
12VSENSEB
12VINB
C1
0.1µF
33
36
34
35
29
D
D
D
D
Via to signal plane
(GATE pin connection)
Via to GND Plane
***CFILTER
S
S
S
G
Figure 15. Suggested PCB Layout for Sense Resistor, Power MOSFET, and Capacitors
MIC2592B Micrel
March 2005 30
M9999-033105
MOSFET and Sense Resistor Vendors
Device types, part numbers, and manufacturer contact infor-
mation for power MOSFETs and sense resistors are provided
in Table 4. Some of the recommended MOSFETs include
a metal (tab) heat sink on the bottom side of the package.
Contact the device manufacturer for package information.
Key Power MOSFET Type(s)
MOSFET Vendors N-Channel P-Channel Package Contact Information
Vishay - Siliconix Si4420DY Si4435BDY SO-8 www.siliconix.com
Si4442DY Si4427BDY SO-8 (203) 452-5664
Si3442DV Si4405DY SO-8
Si4410DY Si4425BDY SO-8
Si7860ADP Si7483ADP PowerPAK SO-8
Si7344DP Si7491DP PowerPAK SO-8
Si7844DP (Dual) Si7945DP (Dual) PowerPAK SO-8
Si7114DN Si7423DN 1212 SO-8
Si7806ADN Si7421DN 1212 SO-8
International Rectifi er
IRF7882
IRF7424 SO-8 www.irf.com
IRF7413
IRF7416 SO-8 (310) 322-3331
IRF7313 (Dual) IRF7328 (Dual) SO-8
Resistor Vendors Sense Resistors Contact Information
Vishay - Dale “WSL” and “WSR” Series www.vishay.com/docswsl_30100.pdf
(203) 452-5664
IRC “OARS” Series www.irctt.com/pdf_fi les/OARS.pdf
“LR” Series www.irctt.com/pdf_fi les/LRC.pdf
second source to “WSL” (828) 264-8861
Table 4. MOSFET and Sense Resistor Vendors
MOSFET Vendors N-Channel P-Channel Package Contact Information
Vishay - Siliconix Si4420DY Si4435BDY SO-8 www.siliconix.com
Si4442DY Si4427BDY SO-8 (203) 452-5664
Si3442DV Si4405DY SO-8
Si4410DY Si4425BDY SO-8
Si7860ADP Si7483ADP PowerPAK SO-8
Si7344DP Si7491DP PowerPAK SO-8
Si7844DP (Dual) Si7945DP (Dual) PowerPAK SO-8
Si7114DN Si7423DN 1212 SO-8
Si7806ADN Si7421DN 1212 SO-8
IRF7413
IRF7313 (Dual) IRF7328 (Dual) SO-8
MOSFET Vendors N-Channel P-Channel Package Contact Information
Vishay - Siliconix Si4420DY Si4435BDY SO-8 www.siliconix.com
Si4442DY Si4427BDY SO-8 (203) 452-5664
Si3442DV Si4405DY SO-8
Si4410DY Si4425BDY SO-8
Si7860ADP Si7483ADP PowerPAK SO-8
Si7344DP Si7491DP PowerPAK SO-8
Si7844DP (Dual) Si7945DP (Dual) PowerPAK SO-8
Si7114DN Si7423DN 1212 SO-8
Si7806ADN Si7421DN 1212 SO-8
IRF7424 SO-8 www.irf.com
IRF7416 SO-8 (310) 322-3331
IRF7313 (Dual) IRF7328 (Dual) SO-8
MOSFET Vendors N-Channel P-Channel Package Contact Information
Vishay - Siliconix Si4420DY Si4435BDY SO-8 www.siliconix.com
Si4442DY Si4427BDY SO-8 (203) 452-5664
Si3442DV Si4405DY SO-8
Si4410DY Si4425BDY SO-8
Si7860ADP Si7483ADP PowerPAK SO-8
Si7344DP Si7491DP PowerPAK SO-8
Si7844DP (Dual) Si7945DP (Dual) PowerPAK SO-8
Si7114DN Si7423DN 1212 SO-8
Si7806ADN Si7421DN 1212 SO-8
IRF7424 SO-8 www.irf.com
IRF7416 SO-8 (310) 322-3331
IRF7313 (Dual) IRF7328 (Dual) SO-8
MOSFET Vendors N-Channel P-Channel Package Contact Information
Vishay - Siliconix Si4420DY Si4435BDY SO-8 www.siliconix.com
Si4442DY Si4427BDY SO-8 (203) 452-5664
IRF7424 SO-8 www.irf.com
IRF7416 SO-8 (310) 322-3331
Resistor Vendors Sense Resistors Contact Information
(203) 452-5664
IRC “OARS” Series www.irctt.com/pdf_fi les/OARS.pdf
“LR” Series www.irctt.com/pdf_fi les/LRC.pdf
second source to “WSL” (828) 264-8861
Resistor Vendors Sense Resistors Contact Information
Vishay - Dale “WSL” and “WSR” Series www.vishay.com/docswsl_30100.pdf
(203) 452-5664
IRC “OARS” Series www.irctt.com/pdf_fi les/OARS.pdf
“LR” Series www.irctt.com/pdf_fi les/LRC.pdf
second source to “WSL” (828) 264-8861
Resistor Vendors Sense Resistors Contact Information
Vishay - Dale “WSL” and “WSR” Series www.vishay.com/docswsl_30100.pdf
(203) 452-5664
IRC “OARS” Series www.irctt.com/pdf_fi les/OARS.pdf
“LR” Series www.irctt.com/pdf_fi les/LRC.pdf
second source to “WSL” (828) 264-8861
MIC2592B Micrel
March 2005 31
M9999-033105
Package Information
48-Pin TQFP
MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifi cations at any time without notifi cation to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signifi cant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2004 Micrel, Incorporated.
