Rev. 4149N–AERO–04/07
1
Features
•
8032 Pin and Instruction Compatible
•
Four 8-bit I/O Ports
•
Three 16-bit Timer/Counters
•
256 bytes RAM
•
Full-duplex UART
•
Asynchronous Port Reset
•
6 Sources, 2 Level Interrupt Structure
•
64 Kbytes Program Memory Space
•
64 Kbytes Data Memory Space
•
Power Control Modes
•
Idle Mode
•
Power-down Mode
•
On-chip Oscillator
•
Operating Frequency: 30 MHz
•
Power Supply: 4.5V to 5.5V
•
Temperature Range: Military (-55
o
C to 125
o
C)
•
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
•
Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
•
Packages: Side Brazed 40-pin, MQFPJ 44-pin
•
Quality grades: QML Q and V with SMD 5962-00518 and ESCC with Specification
9521002
Description
The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit
microcontroller.
The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6-
source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters.
The fully static design of the 80C32E reduces system power consumption by bringing
the clock frequency down to any value, even DC, without loss of data.
The 80C32E has 2 software-selectable modes of reduced activity for further reduction
in power consumption. In the idle mode the CPU is frozen while the timers, the serial
port and the interrupt system are still operating. In the power-down mode the RAM is
saved and all other functions are inoperative.
Rad. Tolerant
8-bit ROMless
Microcontroller
80C32E
2
80C32E
4149N–AERO–04/07
Block Diagram
Pin Configuration
Note: NIC: No Internal Connection
Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA
PSEN
ALE
XTAL2
XTAL1
UART
CPU
INT1
Ctrl
INT0
C51
CORE
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
IB-bus
RST
Timer 1 Timer 2
T2
T2EX
5 4 3 2 1 6 44 43 42 41 40
P1.4
P1.0
P1.1
P1.3
P1.2
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
MQFPJ44
18 19 20 21 22 23 24 25 26 27 28
P1.7
RST
P3.0/RxD
P3.1/TxD
P1.3
1
P1.5
P3.2/INT0
P3.3/INT1
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P0.4/A4
P0.6/A6
P0.5/A5
P0.7/A7
ALE
PSEN
EA/VPP
P2.7/A15
P2.5/A13
P2.6/A14
P1.0/T2
P1.1/T2EX
VCC
P0.0/A0
P0.1/A1
P0.2/A2
P0.3/A3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SB40
P1.6
P1.4
P1.2
P3.4/T0
3
80C32E
4149N–AERO–04/07
Pin Description
Mnemonic Type Name and Function
V
SS
IGround: 0V reference
V
CC
IPower Supply: This is the power supply voltage for normal, idle and
power-down operation
P0.0-P0.7 I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 pins must be polarized to Vcc or Vss in order to prevent any
parasitic current consumption. Port 0 is also the multiplexed low-order
address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-up when emitting
1s.
P1.0-P1.7 I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups.
P2.0-P2.7 I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
P3.0-P3.7
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
IRXD (P3.0): Serial input port
OTXD (P3.1): Serial output port
IINT0 (P3.2): External interrupt 0
IINT1 (P3.3): External interrupt 1
IT0 (P3.4): Timer 0 external input
IT1 (P3.5): Timer 1 external input
OWR (P3.6): External data memory write strobe
ORD (P3.7): External data memory read strobe
RST I
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to V
SS
permits a
power-on reset using only an external capacitor to V
CC.
4
80C32E
4149N–AERO–04/07
ALE O (I)
Address Latch Enable: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 the oscillator frequency, and can be
used for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.
PSEN O
Program Store ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
EA I External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations.
XTAL1 I Crystal 1: Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
XTAL2 O Crystal 2: Output from the inverting oscillator amplifier
Mnemonic Type Name and Function
5
80C32E
4149N–AERO–04/07
Idle and Power-down
Operation
Idle mode allows the interrupt, serial port and timer blocks to continue to operate while
the clock of the CPU is gated off.
Power-down mode stops the oscillator.
Table 1. PCON Register
PCON – Power Control Register
Reset Value = 000X 0000
Not bit addressable
76543210
SMOD - - - GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD Double Baud Rate bit
Set to select double baud rate in mode 1, 2 or 3.
6 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 - Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 GF1
General-purpose Flag
Cleared by user for General-purpose usage.
Set by user for General-purpose usage.
2 GF0
General-purpose Flag
Cleared by user for General-purpose usage.
Set by user for General-purpose usage.
1 PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
6
80C32E
4149N–AERO–04/07
Idle Mode
An instruction that sets PCON.0 causes that to be the last instruction executed before
going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but
not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its
entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM
and all other registers maintain their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-
viced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during an Idle. For example, an instruction that activates Idle
can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a power-down mode can be invoked by software.
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. V
CC
can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed before V
CC
is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 1. When both interrupts are enabled, the oscillator restarts as soon as
one of the two inputs is held low and Power-down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is executed
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put 80C32E into power-down mode.
Figure 1. Power-down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
INT1
INT0
XTAL1
Power-down phase Oscillator restart phase Active phaseActive phase
7
80C32E
4149N–AERO–04/07
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 2. State of Ports During Idle and Power-down Modes
Mode
Program
Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle External 1 1 Floating Port Data Address Port Data
Power-
down External 0 0 Floating Port Data Port Data Port Data
8
80C32E
4149N–AERO–04/07
Hardware
Description
Refer to the C51 8-bit Microcontroller Hardware description manual for details on
80C32E functionality.
Electrical Characteristics
Absolute Maximum Ratings
(2)
Ambient Temperature Under Bias. M = Military-55°C to 125°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on V
CC
to V
SS
..........................................-0.5V to + 7V
Voltage on Any Pin to V
SS
..........................-0.5V to V
CC
+ 0.5V
Power Dissipation........................................................... 1 W
(2)
Notes: 1. Stresses at or above those listed under “ Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
2. This value is based on the maximum allowable
die temperature and the thermal resistance of the
package.
9
80C32E
4149N–AERO–04/07
DC Parameters
Notes: 1. I
CC
under reset is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 6), V
IL
=
V
SS
+ 0.5V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V
CC
. I
CC
would be slightly higher if a crystal oscillator is used.
2. Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
CC
-
0.5V; XTAL2 N.C; Port 0 = V
CC
; EA = RST = V
SS
(see Figure 4).
3. Power-down I
CC
is measured with all output pins disconnected; EA = V
SS
, PORT 0 = V
CC
; XTAL2 NC.; RST = V
SS
(see Fig-
ure 5).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
s of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
OL
peak 0.6V. The use of a Schmitt Trigger is not necessary.
5. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 10 mA
Maximum I
OL
per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL
for all output pins: 71 mA
Table 3. DC Parameters in Standard VoltageT
A
= -55°C to +125°C; V
SS
= 0V; V
CC
= 5V ± 10%; F = 0 to 30 MHz.
Symbol Parameter Min. Max Unit Test Conditions
V
IL
Input Low Voltage -0.5 0.2 V
CC
- 0.1 V
V
IH
Input High Voltage except XTAL1, RST 0.2 V
CC
+ 1.4 V
CC
+ 0.5 V
V
IH1
Input High Voltage, XTAL1, RST 0.7 V
CC
V
CC
+ 0.5 V
V
OL
Output Low Voltage, ports 1, 2, 3
(5)
0.45 V I
OL
= 1.6 mA
(4)
V
OL1
Output Low Voltage, port 0, ALE, PSEN
(5)
0.45 V I
OL
= 3.2 mA
(4)
V
OH
Output High Voltage, ports 1, 2, 3
2.4
0.75 V
CC
0.9 V
CC
V
V
V
I
OH
= -60 µA
I
OH
= -25 µA
I
OH
= -10 µA
V
OH1
Output High Voltage, port 0, ALE, PSEN
2.4
0.75 V
CC
0.9 V
CC
V
V
V
I
OH
= -400 µA
I
OH
= -150 µA
I
OH
= -40 µA
R
RST
RST Pull-down Resistor 50 200 kΩ
I
IL
Logical 0 Input Current ports 1, 2 and 3 -75 µA Vin = 0.45V
I
LI
Input Leakage Current ±10 µA 0.45 V < Vin < V
CC
I
TL
Logical 1 to 0 Transition Current, ports 1, 2, 3 -750 µA Vin = 2.0V
C
IO
Capacitance of I/O Buffer 10 pF Fc = 1 MHz
T
A
= 25°C
I
PD
Power-down Current
(3)
75 µA 2.0V < V
CC <
5.5V
I
CC
Power Supply Current
(1)(2)(6)
Freq = 1 MHz Icc Op
Freq = 1 MHz Icc Idle
Freq = 6 MHz Icc Op
Freq = 6 MHz Icc Idle
Freq >12 MHz Icc Op
Freq >12 MHz Icc Idle
1.8
1
10
4
1.25F + 5
0.36F + 2.7
mA
mA
mA
mA
mA
mA
V
CC
= 5.5V
F in MHz
10
80C32E
4149N–AERO–04/07
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
6. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; EA = Port 0 = V
CC
; RST = V
SS
. The internal ROM runs the code 80 FE (label: SJMP label). I
CC
would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is
the worst case.
Figure 2. I
CC
Test Condition, Under Reset
Figure 3. Operating I
CC
Test Condition
Figure 4. I
CC
Test Condition, Idle Mode
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
EA
V
CC
V
CC
I
CC
(NC)
CLOCK
SIGNAL All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0
Reset = Vss after a high pulse
during at least 24 clock cycles
RST EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
CLOCK
SIGNAL
Reset = Vss after a high pulse
during at least 24 clock cycles
11
80C32E
4149N–AERO–04/07
Figure 5. I
CC
Test Condition, Power-down Mode
Figure 6. Clock Signal Waveform for I
CC
Tests in Active and Idle Modes
RST EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
Reset = Vss after a high pulse
during at least 24 clock cycles
12
80C32E
4149N–AERO–04/07
AC Parameters
Each timing symbol has 5 characters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:
T
AVLL
= Time for Address Valid to ALE Low.
T
LLPL
= Time for ALE Low to PSEN Low.
T
A
= -55°C to +125°C (Military temperature range); V
SS
= 0V; V
CC
= 5V ± 10%;
Load capacitance for Port 0, ALE and PSEN = 100 pF; Load capacitance for all other
outputs = 80 pF.
Table 4. External Program Memory Characteristics (ns)
Figure 7. External Program Memory Read Cycle
Symbol Parameter
30 MHz
Min Max
T
LHLL
ALE Pulse Width 60
T
AVLL
Address Valid to ALE 15
T
LLAX
Address Hold After ALE 35
T
LLIV
ALE to Valid Instruction In 100
T
LLPL
ALE to PSEN 25
T
PLPH
PSEN Pulse Width 80
T
PLIV
PSEN to Valid Instruction In 65
T
PXIX
Input Instruction Hold After PSEN 0
T
PXIZ
Input Instruction Float After PSEN 30
T
PXAV
PSEN to Address Valid 35
T
AVIV
Address to Valid Instruction In 130
T
PLAZ
PSEN Low to Address Float 6
T
PLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 T
CLCL
T
AVIV
T
LHLL
T
AVLL
T
LLIV
T
LLPL
T
PLPH
T
PXAV
T
PXIX
T
PXIZ
T
LLAX
13
80C32E
4149N–AERO–04/07
Table 5. External Data Memory Characteristics (ns)
Figure 8. External Data Memory Write Cycle
Symbol Parameter
30 MHz
min max
T
RLRH
RD Pulse Width 180
T
WLWH
WR Pulse Width 180
T
RLDV
RD to Valid Data In 135
T
RHDX
Data Hold After RD 0
T
RHDZ
Data Float After RD 70
T
LLDV
ALE to Valid Data In 235
T
AVDV
Address to Valid Data In 260
T
LLWL
ALE to WR or RD 90 115
T
AVWL
Address to WR or RD 115
T
QVWX
Data Valid to WR Transition 20
T
QVWH
Data set-up to WR High 215
T
WHQX
Data Hold After WR 20
T
RLAZ
RD Low to Address Float 0
T
WHLH
RD or WR High to ALE high 20 40
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
RLAZ
ADDRESS A8-A15 OR SFR P2
T
RHDZ
T
WHLH
T
RLRH
T
LLDV
T
RHDX
T
AVDV
T
LLAX
T
RLDV
14
80C32E
4149N–AERO–04/07
Figure 9. External Data Memory Read Cycle
Table 6. Serial Port Timing – Shift Register Mode (ns)
Figure 10. Shift Register Timing Waveforms
T
QVWH
T
LLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
QVWX
ADDRESS A8-A15 OR SFR P2
T
WHQX
T
WHLH
T
WLWH
Symbol Parameter
30 MHz
Min Max
T
XLXL
Serial port clock cycle time 400
T
QVHX
Output data set-up to clock rising edge 300
T
XHQX
Output data hold after clock rising edge 50
T
XHDX
Input data hold after clock rising edge 0
T
XHDV
Clock rising edge to input data valid 300
VALID
0 1 2 3 4 5 6 87
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
CLEAR RI
T
XLXL
T
QVXH
T
XHQX
T
XHDV
T
XHDX
SET TI
SET RI
INSTRUCTION
0 1 2 3 4 5 6 7
VALID VALID VALID VALID
VALID VALID
INPUT DATA
VALID
15
80C32E
4149N–AERO–04/07
Table 7. External Clock Drive Characteristics (XTAL1)
Figure 11. External Clock Drive Waveforms
Figure 12. AC Testing Input/Output Waveforms
AC inputs during testing are driven at V
CC
- 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at V
IH
min for a logic “1” and V
IL
max for a logic “0”.
Figure 13. Float Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded V
OH
/V
OL
level
occurs. I
OL
/I
OH
≥ ± 20 mA.
Symbol Parameter
Min Max Unit
T
CLCL
Oscillator Period
33.33 ns
T
CHCX
High Time
5 ns
T
CLCX
Low Time
5 ns
T
CLCH
Rise Time
5 ns
T
CHCL
Fall Time
5 ns
V
CC
-0.5
V
0.45
V
0.7V
CC
0.2V
CC
-0.1V
T
CHCL
T
CLCX
T
CLCL
T
CLCH
T
CHCX
0.45V
V
CC
-0.5V 0.2V
CC
+0.9
0.2V
CC
-0.1
INPUT/OUTPUT
V
OL
+0.1V
V
OH
-0.1V
FLOAT
V
LOAD
V
LOAD
+0.1V
V
LOAD
-0.1V
16
80C32E
4149N–AERO–04/07
Figure 14. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-
tion also varies from output to output and component. Typically though (T
A
=25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
CLOCK
XTAL2
ALE
INTERNAL STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
EXTERNAL PROGRAM MEMORY FETCH
READ CYCLE
WRITE CYCLE
SERIAL PORT SHIFT CLOCK
PORT OPERATION
PSEN
P0
P2 (EXT)
RD
P0
P2
P0
P2
WR
TXD (MODE 0)
RXD SAMPLED RXD SAMPLED
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST PORT (P1, P2,
(INCLUDES INT0, INT1, TO, T1)
MOV DEST P0
OLD DATA NEW DATA
DPL OR Rt OUT
DATA OUT
PCL OUT (EVEN IF
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
DPL OR Rt OUT
FLOAT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
INDICATES ADDRESS
TRANSITIONS
FLOAT FLOAT FLOAT
PCL OUT PCL OUT PCL OUT
DATA
SAMPLED DATA
SAMPLED
DATA
SAMPLED
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
P1P2 P1P2 P1P2 P1P2 P1P2 P1P2 P1P2 P1P2
17
80C32E
4149N–AERO–04/07
Ordering Information
Note: 1. Please contact Atmel for availability.
Table 8. Possible Order Entries
Part Number Speed (MHz)
Temperature
Range Package Quality Flow
MC-80C32E-30-E 30 25°C Side Brazed 40-pin (.6) Engineering samples
MJ-80C32E-30-E 30 25°C MQFPJ 44-pin Engineering samples
5962-0051801QQC 30 -55°C to +125°C Side Brazed 40 pin (.6) QML-Q
5962-0051801QXC 30 -55°C to +125°C MQFPJ 44-pin QML-Q
5962-0051801VQC 30 -55°C to +125°C Side Brazed 40 pin (.6) QML-V
5962-0051801VXC 30 -55°C to +125°C MQFPJ 44-pin QML-V
952100201 30 -55°C to +125°C Side Brazed 40 pin (.6) ESCC
952100202 30 -55°C to +125°C MQFPJ 44-pin ESCC
MM0-80C32E-30-E
(1)
30 -55°C to +125°C Die Engineering samples
MM0-80C32E-30-SV 30 -55°C to +125°C Die QML-V
18
80C32E
4149N–AERO–04/07
Package Drawings
40-pin Side Braze (600 mils)
19
80C32E
4149N–AERO–04/07
44-pin Multilayer Quad Flat Pack
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