PCI 6154 Data Book v2.0
2003 PLX Technology, Inc. All rights reserved. 11
1 Register Index
When looking up registers, please also check registers below preceded with “Primary” or “Secondary”.
Arbiter Control Register .............................................................35
Bridge Control Register .............................................................33
Cache Line Size Register ..........................................................30
Capability Identifier
Non-transparent, Primary ..........................................50, 51, 52
Chip Control Register
Non-transparent, Primary ......................................................34
Class Code Register..................................................................30
Device ID Register.....................................................................29
Diagnostic Control Register .......................................................34
ECP Pointer...............................................................................32
EEPROM Address.....................................................................44
EEPROM Control ................................................................43, 44
GPIO Input Data Register..........................................................46
GPIO Output Data Register .......................................................46
GPIO Output Enable Register....................................................46
Header Type Register................................................................30
Hot Swap Register
Non-transparent, Primary ......................................................51
Hot Swap Switch
Non-transparent, Primary ......................................................49
I/O Base Address Upper 16 Bits Register ..................................32
I/O Base Register ......................................................................31
I/O Limit Address Upper 16 Bits Register...................................32
I/O Limit Register.......................................................................31
Internal Arbiter Control Register.................................................42
Interrupt Pin Register.................................................................32
Memory Base Register ..............................................................32
Memory Limit Register...............................................................32
Miscellaneous Options...............................................................37
Next Item Pointer
Non-transparent, Primary ..........................................50, 51, 52
P_SERR_L Event Disable Register ...........................................45
P_SERR_L Status Register .......................................................48
PMCSR Bridge Support
Non-transparent, Primary...................................................... 51
Power Management Capabilities
Non-transparent, Primary...................................................... 50
Power Management Control/ Status
Non-transparent, Primary...................................................... 51
Prefetchable Memory Base Register ......................................... 32
Prefetchable Memory Base Register Upper 32 Bits................... 32
Prefetchable Memory Limit Register.......................................... 32
Prefetchable Memory Limit Register Upper 32 Bits ................... 32
Primary Bus Number Register................................................... 30
Primary Command Register ...................................................... 29
Primary Flow Through Control Register..................................... 35
Primary Latency Timer Register ................................................ 30
Primary Side Incremental Prefetch Count.................................. 39
Primary Side Maximum Prefetch Count..................................... 40
Primary Side Prefetch Line Count ............................................. 39
Primary Status Register ............................................................ 30
Revision ID Register.................................................................. 30
Secondary Bus Number Register .............................................. 30
Secondary Clock Control Register............................................. 47
Secondary Flow Through Control Register................................ 41
Secondary Latency Timer.......................................................... 31
Secondary Side Incremental Prefetch Count ............................. 40
Secondary Side Maximum Prefetch Count ................................ 40
Secondary Side Prefetch Line Count......................................... 39
Secondary Status Register........................................................ 31
Subordinate Bus Number Register ............................................ 31
Timeout Control Register.......................................................... 36
Vendor ID Register.................................................................... 29
VPD Data Register
Non-transparent, Primary...................................................... 52
VPD Register
Non-transparent, Primary...................................................... 52