Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Li+ Charger Protection IC with Integrated P-MOSFET
• Input Over-Voltage Protection
• Input Over-Current Protection
• Battery Over-Voltage Protection
• High Immunity of False Triggering
• High Accuracy Protection Threshold
• A Built-In P-MOSFET
• Thermal Shutdown Protection
• Compliance to IEC61000-4-2 (Level 4)
± 8kV (Contact Discharge)
± 15kV (Air Discharge)
• Available in a TDFN2x2-8 and TSOT-23-6A
Packages
• Lead Free and Green Devices Available
(RoHS Compliant)
Features
Applications
• Cell Phones
General Description
Simplified Application Circuit
The APL3206/A/B provides complete Li+ charger protec-
tion against input over-voltage, input over-current, and
battery over-voltage. When any of the monitored param-
eters are over the threshold, the IC removes the power
from the charging system by turning off an internal switch.
All protections also have deglitch time against false trig-
gering due to voltage spikes or current transients.
The APL3206/A/B integrates a P-MOSFET with the body
diode reverse protection to replace the external P-MOSFET
and Schottky diode for charger function of cell phone’s
PMIC. When the CHRIN voltage drops below VBAT+20mV,
the internal power select circuit will reverse the body
diode’s terminal to prevent a reverse current flowing from
the battery back to CHRIN pin.
The APL3206/A/B provides complete Li+ charger protec-
tions and saves the external MOSFET and Schottky diode
for the charger of cell phone’s PMIC. The above features
and small package make the APL3206/A/B an ideal part
for cell phones applications.
Pin Configuration
ACIN 1
ACIN 2
VBAT 4 5 GATDRV
GND 3
8 OUT
7 OUT
6 CHRIN
TDFN2x2-8
(Top View)
EP
EP = Exposed Pad (connected to ground
plane for better heat dissipation)
4 VBAT
6 VIN
CHRIN 2 5 GND
GATDRV 3
OUT 1
TSOT-23-6A
(Top View)
ACIN CHRIN
VBAT
GND
APL3206/A/B
Li+
Battery
GATDRV
OUT
PMIC
VBAT
GATDRV
CHRIN
ISENS
5V Adapter or USB
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw2
Ordering and Marking Information
Absolute Maximum Ratings (Note 1)
Symbol Parameter Rating Unit
VACIN ACIN Input Voltage (ACIN to GND) -0.3 ~ 30 V
VCHRIN CHRIN to GND Voltage -0.3 ~ 7 V
VGATDRV GATDRV to GND Voltage -0.3 ~ VCHRIN V
VBAT VBAT to GND Voltage -0.3 ~ 7 V
VOUT OUT to GND Voltage -0.3 ~ 7 V
IOUT OUT Output Current 1.5 A
TJ Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2) TDFN2x2-8
TSOT-23-6A
80
235
oC/W
Thermal Characteristic
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN2x2-8 is soldered directly on the PCB.
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
APL3206
APL3206A
APL3206B
Package Code
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
Handling Code
Temperature Range
Package Code
X - Date Code
G : Halogen and Lead Free Device
Assembly Material QB : TDFN2x2-8 CT : TSOT-23-6A
APL3206 QB: L06
X
X - Date Code
APL3206A QB: L6A
X
X - Date Code
APL3206 CT: L06X
X - Date Code
APL3206A CT: L6AX
X - Date Code
APL3206B QB: L6B
X
X - Date Code
APL3206B CT: L6BX
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw3
Symbol
Parameter Range Unit
VACIN
ACIN Input Voltage 4.5 ~ 5.5 V
IOUT Output Current 0 ~ 700 mA
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
APL3206/A/B
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
ACIN INPUT CURRENT AND POWER-ON-RESET (POR)
IACIN ACIN Supply Current IOUT=0A, ICHRIN=0A - 250 350 µA
VACIN
ACIN POR Threshold VACIN rising 2.4 - 2.8 V
ACIN POR Hysteresis 200 250 300 mV
TB(ACIN)
ACIN Power-On Blanking Time - 8 - ms
INTERNAL SWITCH ON RESISTANCE
ACIN to OUT On Resistance IOUT=0.7A - 0.5 - Ω
CHRIN Discharge On Resistance
- 500 - Ω
INPUT OVER-VOLTAGE PROTECTION (OVP)
APL3206 6 6.17
6.35
APL3206A 6.6 6.8 7
VOVP
Input OVP Threshold VACIN rising
APL3206B 7.5 7.65
7.8
V
Input OVP Hysteresis 200 300 400 mV
Input OVP Propagation Delay - - 1 µs
TON(OVP)
Input OVP Recovery Time - 8 - ms
OVER-CURRENT PROTECTION (OCP)
IOCP OCP Threshold 1 - 1.55 A
TB(OCP)
OCP Blanking Time - 176 - µs
TON(OCP)
OCP Recovery Time - 64 - ms
BATTERY OVER-VOLTAGE PROTECTION
VBOVP
Battery OVP Threshold VBAT rising 4.32
4.35
4.38 V
Battery OVP Hysteresis 220 270 320 mV
IVBAT VBAT Pin Leakage Current VBAT = 4.4V - - 20 nA
TB(BOVP)
Battery OVP Blanking Time - 176 - µs
INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS)
VCHRIN from low to high, P-MOSFET is controlled
by GATDRV - 150 -
VCHRIN-VBAT Lockout Threshold VCHRIN from high to low, P-MOSFET is off - 20 - mV
OUT Input Current VCHRIN=0V, VOUT=4.2V, GATDRV=GND - - 1 µA
GATDRV Leakage Current VACIN=VCHRIN= VOUT=5V, VGATDRV=0V - - 1 µA
OUT Leakage Current VACIN=VCHRIN= VGATDRV =5V, VOUT=0V - - 1 µA
Electrical Characteristics
Recommended Operating Conditions (Note 3)
Note 3: Refer to the typical application circuit
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw4
APL3206/A/B
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
INTERNAL P-MOSFET (CHRIN, OUT, AND GATDRV PINS) (CONT.)
P-MOSFET Input Capacitance - 200 - pF
GATDRV Input Resistance - 15 - Ω
OVER-TEMPERATURE PROTECTION (OTP)
TOTP
Over-Temperature Threshold TJ rising - 160 - °C
Over-Temperature Hysteresis - 40 - °C
Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Electrical Characteristics (Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw5
Typical Operating Characteristics
OCP Threshold, IOCP (A)
Junction Temperature ( )
oC
OCP Threshold vs. Junction
Temperature
-50 -25 025 50 75 100 125
1.00
1.05
1.10
1.15
1.20
1.25
1.30
Input OVP Threshold, VOVP (V)
Junction Temperature (oC)
Input OVP Threshold vs. Junction
Temperature
-50 -25 0 25 50 75 100 125
5.65
5.75
5.85
5.95
6.05
6.15
6.25
VACIN Increasing
VACIN Decreasing
ACIN Supply Current vs.
Junction Temperature
ACIN Supply Current, IACIN (µA)
Junction Temperature (oC)
-50 -25 0 25 50 75 100 125
150
200
250
300
350
POR Threshold, VPOR (V)
POR Threshold vs. Junction
Temperature
Junction Temperature (oC)
-50 -25 025 50 75 100 125
VACIN Increasing
VACIN Decreasing
2.2
2.3
2.4
2.5
2.6
2.7
2.8
ACIN to OUT On Resistance, RDS,ON (mΩ)
Junction Temperature (oC)
ACIN to OUT On Resistance vs.
Junction Temperature
-50 -25 0 25 50 75 100 125
ACIN to OUT On Resistance
300
400
500
600
700
800
900
1000
Battery OVP Threshold vs.
Junction Temperature
Battery OVP Threshold, VBOVP (V)
Junction Temperature (oC)
-50 -25 025 50 75 100 125
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
VBAT Increasing
VBAT Decreasing
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw6
Operating Waveforms
The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified.
OVP at Power On
1
2
3
VOUT
CH1: VACIN, 10V/Div, DC
CH2: VCHRIN, 2V/Div, DC
VACIN = 0 to 12V, VGATDRV = VCHRIN
CH3: VOUT, 2V/Div, DC
TIME: 2ms/Div
VCHRIN
VACIN
CH1: VACIN, 5V/Div, AC
CH2: VCHRIN, 2V/Div, DC
TIME: 2ms/Div
Recovery from Input OVP
VCHRIN
VACIN
1
2
VACIN= 12V to 5V
Normal Power On
1
2,3
4
VACIN
VOUT
CH1: VACIN, 5V/Div, DC
CH2: VOUT, 2V/Div, DC
TIME: 2ms/Div
VGATDRV = VCHRIN
CH4: IOUT, 0.2A/Div, DC
IOUT
VCHRIN
CH3: VCHRIN, 2V/Div, DC
CH1: VACIN, 5V/Div, AC
CH2: VCHRIN, 2V/Div, DC
TIME:20µs/Div
Input Over-Voltage Protection
VACIN
1
VACIN =5V to 12V
VCHRIN
2
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw7
Operating Waveforms (Cont.)
The test condition is VACIN=5V, VBAT=3.8V, CACIN=1µF, CCHRIN=1µF, TA= 25oC unless otherwise specified.
Battery Over-Voltage Protection
VCHRIN
VBAT
1
2
CH1: VBAT, 2V/Div, AC
CH2: VCHRIN, 2V/Div, DC
TIME: 50ms/Div
VBAT = 3.6V to 4.4V to 3.6V
Over-Current Protection
IOUT
VCHRIN
VACIN
VOUT
CH2: VCHRIN, 5V/Div, DC
CH3: VOUT, 5V/Div, DC
TIME: 200ms/Div
CH4: IOUT, 1A/Div, DC
ROUT=2.5Ω, VBAT = 0V, VGATDRV=0V
CH1: VACIN, 5V/Div, DC
1
2
3
Note: OUT pin connected with a resistor to ground.
Over-Current Protection
3
2
1
IOUT
VOUT
VCHRIN
CH1: VCHRIN, 2V/Div, DC
CH2: VOUT, 2V/Div, DC
TIME: 100µs/Div
CH3: IOUT, 0.5A/Div, DC
ROUT=10Ω to 2.4Ω, VBAT = 0V, VGATDRV=0V
Note: OUT pin connected with a resistor to ground.
Battery Over-Voltage Protection
1
2
VBAT
VCHRIN
CH1: VBAT, 2V/Div, DC
CH2: VCHRIN, 2V/Div, DC
TIME: 200µs/Div
VBAT = 3.6V to 4.4V
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw8
PIN
NO. NAME FUNCTION
1,2 ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum)
ceramic capacitor.
3 GND Ground Terminal.
4 VBAT Battery Voltage Sense Input. Connect this pin to pack positive terminal through a resistor.
5 GATDRV
Internal P-MOSFET Gate Input.
6 CHRIN Output Pin. This pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum)
ceramic capacitor.
7,8 OUT Output Pins. These pins provide supply source current in series with a resistor to battery.
- EP Exposed Thermal Pad. Must be electrically connected to the GND pin.
Block Diagram
Gate Driver and
Control Logic
POR
ACIN
VBAT
OUT
Charge
Pump
0.5V
ACIN
OVP
OCP
CHRIN
GATDRV
GND
Thermal
Shutdown
1V
VBAT
OVP
Pin Description
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw9
Typical Application Circuit
Designation
Description
CACIN 1µF, 25V, X5R, 0603
Murata GRM188R61E105K
CCHRIN 1µF, 10V, X5R, 0603
Murata GRM188R61A105K
Murata website: www.murata.com
ACIN CHRIN
VBAT
GND
APL3206/A/B
Li+
Battery
GATDRV
OUT
5V Adapter/USB
0.2Ω
1, 2
34
5
6
7, 8
CACIN
1µFCCHRIN
1µF
RBAT
200kΩ
PMIC
VBAT
GATDRV
CHRIN
ISENS
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw10
Function Description
ACIN Power-On-Reset (POR)
The APL3206/A/B has a built-in power-on-reset circuit to
keep the output shutting off until internal circuitry is oper-
ating properly. The POR circuit has hysteresis and a de-
glitch feature so that it will typically ignore undershoot
transients on the input. When the input voltage exceeds
the POR threshold and after 8ms blanking time, the out-
put voltage starts a soft-start to reduce the inrush current.
ACIN Over-Voltage Protection (OVP)
The input voltage is monitored by the internal OVP circuit.
When the input voltage rises above the input OVP
threshold, the internal FET will be turned off within 1ms to
protect connected system on OUT pin. When the input
voltage returns below the input OVP threshold minus the
hysteresis, the FET is turned on again after 8ms recovery
time. The input OVP circuit has a 300mV hysteresis and
a recovery time of TON(OVP) to provide noise immunity against
transient conditions.
Over-Current Protection (OCP)
The output current is monitored by the internal OCP circuit.
When the output current reaches the OCP threshold, the
device limits the output current at OCP threshold level. If
the OCP condition continues for a blanking time of TB(OCP),
the internal power FET is turned off. After the recovery
time of TON(OCP), the FET will be turned on again. The
APL3206/A/B has a built-in counter. When the total count
of OCP fault reaches 16, the FET is turned off permanently,
requiring a VACIN POR again to restart.
Battery Over-Voltage Protection
The APL3206/A/B monitors the VBAT pin voltage for bat-
tery over-voltage protection. The battery OVP threshold is
internally set to 4.35V. When the VBAT pin voltage ex-
ceeds the battery OVP threshold for a blanking time of TB
(BOVP), the internal power FET is turned off. When the VBAT
voltage returns below the battery OVP threshold minus
the hysteresis, the FET is turned on again. The APL3206/
A/B has a built-in counter. When the total count of battery
OVP fault reaches 16, the FET is turned off permanently,
requiring a VACIN POR again to restart.
Over-Temperature Protection
When the junction temperature exceeds 160oC, the inter-
nal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
tion temperature cools by 40oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal pro-
tection is designed to protect the IC in the event of over
temperature conditions. For normal operation, the junc-
tion temperature cannot exceed TJ=+125oC.
Internal P-MOSFET
The APL3206/A/B integrates a P-channel MOSFET with
the body diode reverse protection to replace the external
P-MOSFET and Schottky diode for cell phone’s PMIC. The
body diode reverse protection prevents a reverse current
flowing from the battery back to CHRIN pin. During power-
on, when CHRIN voltage rises above the VBAT voltage by
more than 150mV, the body diode of the P-channel
MOSFET is forward biased from OUT to CHRIN, and P-
MOSFET is controlled by the external GATDRV voltage.
When the CHRIN voltage drops below VBAT+20mV, the
body diode of the P-channel MOSFET is forward biased
from CHRIN to OUT and P-channel MOSFET is turned
off. When any of input OVP, OCP, battery OVP, is detected,
the internal P-channel MOSFET is also turned off.
The APL3206/A/B VIN input pin fully supports the
IEC61000-4-2. That means the VIN pin has immunity of
±15kV ESD discharge in Air condition, and immunity of
±8kV ESD discharge in Contact condition.
ESD Tests
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw11
Function Description (Cont.)
Figure 1. OVP Timing Diagram
VPOR
VOVP
VACIN
ACIN OVP TON(OVP)
VCHRIN
VCHRIN -VBAT = 150mV
TB(ACIN)
P-MOS Gate
Control
VOUT
Turn Off Internal
P-MOSFET Controlled by
GATDRV
VCHRIN -VBAT = 150mV
Turn Off Internal P-MOSFET
GATDRV is pulled low
Controlled
by GATDRV
Figure 2. OCP Timing Diagram
Count 13
times
IOUT
Total count 16
times, IC is
latched off
VCHRIN
TB(OCP) TON(OCP)
P-MOS Gate
Control
TB(OCP) TB(OCP)
Turn Off Internal
P-MOSFET
Turn Off
Internal P-
MOSFET
Turn Off
Internal P-
MOSFET
IOCP
GATDRV is pulled low
Controlled by
GATDRV
Controlled
by
GATDRV
Controlled by
GATDRV
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw12
Function Description (Cont.)
Figure 3. Battery OVP Timing Diagram
VCHRIN
Count 13
times
VBAT
TB(BOVP)
Total count 16
times, IC is
latched off
P-MOS Gate
Control
VBOVP
TB(BOVP)
VBOVP
VCHRIN -VOUT =
150mV
TB(BOVP)
Turn Off Internal
P-MOSFET Turn Off Internal
P-MOSFET
Turn Off
Internal P-
MOSFET
Controlled by
GATDRV Controlled
by GATDRV
Controlled
by GATDRV
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw13
Application Information
RBAT Selection
Connect the VBAT pin to the positive terminal of battery
through a resistor RBAT for battery OVP function. The RBAT
limits the current flowing from VBAT to battery in case of
VBAT pin is shortened to ACIN pin under a failure mode.
The recommended value of RBAT is 200kΩ. In the worse
case of an IC failure, the current flowing from the VBAT
pin to the battery is:
(30V-3V) / 200kΩ =135µA
where the 30V is the maximum ACIN voltage and the 3V
is the minimum battery voltage. The current is so small
and can be absorbed by the charger system.
Capacitor Selection
The input capacitor is for decoupling and prevents the
input voltage from overshooting to dangerous levels. In
the AC adapter hot plug-in applications or load current
step-down transient, the input voltage has a transient
spike due to the parasitic inductance of the input cable. A
25V, X5R, dielectric ceramic capacitor with a value be-
tween 1µF and 4.7µF placed close to the ACIN pin is
recommended.
The output capacitor of CHRIN is for CHRIN voltage
decoupling. And also can be as the input capacitor of the
charging circuit. At least, a 1µF, 10V, X5R capacitor is
recommended. Layout Consideration
In some failure modes, a high voltage may be applied to
the device. Make sure the clearance constraint of the PCB
layout must satisfy the design rule for high voltage. The
exposed pad of the TDFN2x2-8 performs the function of
channeling heat away. It is recommended that connect
the exposed pad to a large copper ground plane on the
backside of the circuit board through several thermal vias
to improve heat dissipation. The input and output capaci-
tors should be placed close to the IC. The high current
traces like input trace and output trace must be wide and
short.
Thermal Considerations
The maximum power dissipation depends on the ther-
mal resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by the following formula:
PD(MAX) = (T J(MAX)-TA) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance. For recom-
mended operating conditions specification of APL3206/
A, where TJ(MAX) is 125oC and TA is the operated ambient
temperature. The junction to ambient thermal resistance
θJA for TDFN2x2-8 package is 165oC/W and TSOT-23-6A
package is 220oC/W on the standard JEDEC 51-3 single-
layer thermal test board. The maximum power dissipa-
tion at TA = 25oC can be calculated by following formula :
PD(MAX) = (125oC-25oC) / (165oC/W) = 0.606W
for TDFN2x2-8 packages
PD(MAX) = (125oC-25oC) / (220oC/W)= 0.455W
for TSOT-23-6A packages
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal resis-
tance θJA. For APL3206/A packages, the Figure 4 of derat-
ing curves allows the designer to see the effect of rising
ambient temperature on the maximum power allowed.
Figure 4. Derating Curves for APL3206/A Packages
Ambient Temperature ( oC)
Power Dissipation (W)
TSOT-23-6A
TDFN2x2-8
Signal Layer PCB
0 25 50 75 100 125
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw14
Package Information
TDFN2x2-8
MIN. MAX.
0.80
0.00
0.18 0.30
1.00 1.60
0.05
0.60
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TDFN2x2-8
0.30 0.45
1.00
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.039 0.063
0.024
0.012 0.018
0.70
0.039
0.028
0.002
0.50 BSC 0.020 BSC
S
Y
M
B
O
L
1.90 2.10 0.075 0.083
1.90 2.10 0.075 0.083
D
E
A
b
A1
A3
D2
E2
L
e
Pin 1 Corner
Note : 1. Follow from JEDEC MO-229 WCCD-3.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw15
Package Information
TSOT-23-6A
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
De
e1
b
E1
E
c
SEE VIEW A
A2A1
A
VIEW A
L
0.25
SEATING PLANE
GAUGE PLANE
0.020
0.008
0.004
0.024
0.035
0.039
MAX.
0.30L
00°
E
e
e1
E1
D
c
b
0.08
0.30
0.012
0.60
8° 0° 8°
0.95 BSC
1.90 BSC
0.50
0.20
0.075 BSC
0.037 BSC
0.012
0.003
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.01
0.70
TSOT-23-6A
MAX.
0.90
0.10
1.00
MIN.
0.000
0.028
INCHES
2.70 3.10 0.106 0.122
2.60 3.00 0.102 0.118
1.40 1.80 0.055 0.071
0.70 0.028
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw16
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.20
1.75±0.10
3.50±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN2x2-8
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.4 3.35 MIN
3.35 MIN
1.30±0.20
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TSOT-23-6A
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type Unit Quantity
TDFN2x2-8 Tape & Reel 3000
TSOT-23-6A Tape & Reel 3000
Carrier Tape & Reel Dimensions
H
T1
A
d
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw17
Taping Direction Information
TDFN2x2-8
USER DIRECTION OF FEED
TSOT-23-6A
AAAX AAAX AAAX AAAX AAAX AAAX AAAX
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw18
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Profile
Classification Reflow Profiles
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jan., 2010
APL3206/A/B
www.anpec.com.tw19
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Classification Reflow Profiles (Cont.)
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
