INTEGRATED CIRCUITS DATA SHEET PCF8576 Universal LCD driver for low multiplex rates Product specification Supersedes data of 1998 Feb 06 File under Integrated Circuits, IC12 2001 Oct 02 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Oscillator Internal clock External clock Timing Display latch Shift register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker 7 CHARACTERISTICS OF THE 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Bit transfer (see Fig.12) START and STOP conditions (see Fig.13) System configuration (see Fig.14) Acknowledge (see Fig.15) PCF8576 I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation 2001 Oct 02 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS 11 AC CHARACTERISTICS 11.1 11.2 Typical supply current characteristics Typical characteristics of LCD outputs 12 APPLICATION INFORMATION 12.1 Chip-on-glass cascadability in single plane 13 BONDING PAD INFORMATION 14 TRAY INFORMATION: PCF8576U 15 TRAY INFORMATION: PCF8576U/2 16 PACKAGE OUTLINES 17 SOLDERING 17.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 17.2 17.3 17.4 17.5 I2C-BUS 2 PCF8576 18 DATA SHEET STATUS 19 DEFINITIONS 20 DISCLAIMERS 21 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 1 PCF8576 FEATURES * Single-chip LCD controller/driver * Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing * Selectable display bias configuration: static, 12 or 13 * Internal LCD bias generation with voltage-follower buffers * May be cascaded for large LCD applications (up to 2560 segments possible) * 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements * Cascadable with 24-segment LCD driver PCF8566 * Optimized pinning for plane wiring in both single and multiple PCF8576 applications * 40 x 4-bit RAM for display data storage * Space-saving 56-lead plastic very small outline package (VSO56) * Auto-incremented display data loading across device subaddress boundaries * Very low external component count (at most one resistor, even in multiple device applications) * Display memory bank switching in static and duplex drive modes * Compatible with chip-on-glass technology * Versatile blinking modes * Manufactured in silicon gate CMOS process. * LCD and logic supplies may be separated * Wide power supply range: from 2 V for low-threshold LCDs and up to 9 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs 2 The PCF8576 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The PCF8576 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). * Low power consumption * Power-saving mode for extremely low power consumption in battery-operated and telephone applications * I2C-bus interface * TTL/CMOS compatible * Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers 3 GENERAL DESCRIPTION ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION plastic very small outline package; 56 leads SOT190-1 PCF8576T VSO56 PCF8576U - chip in tray - PCF8576U/2 - chip with bumps in tray - PCF8576U/5 - unsawn wafer - PCF8576U/10 FFC chip on film frame carrier (FFC) - PCF8576U/12 FFC chip with bumps on film frame carrier (FFC) - 2001 Oct 02 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 40 13 VDD 5 14 15 BACKPLANE OUTPUTS 16 17 to 56 DISPLAY SEGMENT OUTPUTS R LCD VOLTAGE SELECTOR R R VLCD 12 DISPLAY LATCH LCD BIAS GENERATOR SHIFT REGISTER 4 PCF8576 4 CLK SYNC 3 TIMING INPUT BANK SELECTOR BLINKER DISPLAY RAM 40 x 4 BITS OUTPUT BANK SELECTOR DISPLAY CONTROLLER V SS SCL SDA 6 OSCILLATOR POWERON RESET DATA POINTER COMMAND DECODER 11 2 1 INPUT FILTERS SUBADDRESS COUNTER I 2C - BUS CONTROLLER 10 7 A0 8 A1 9 A2 Fig.1 Block diagram (for VSO56 package; SOT190-1). PCF8576 MBK276 Product specification SA0 handbook, full pagewidth OSC Universal LCD driver for low multiplex rates BLOCK DIAGRAM S0 to S39 Philips Semiconductors 4 2001 Oct 02 BP0 BP2 BP1 BP3 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 5 PCF8576 PINNING SYMBOL PIN DESCRIPTION SDA 1 I2C-bus SCL 2 I2C-bus serial clock input SYNC 3 cascade synchronization input/output CLK 4 external clock input/output VDD 5 supply voltage OSC 6 oscillator input A0 to A2 7 to 9 serial data input/output I2C-bus subaddress inputs SA0 10 I2C-bus slave address input; bit 0 VSS 11 logic ground 12 LCD supply voltage VLCD BP0, BP2, BP1 and BP3 13 to 16 LCD backplane outputs S0 to S39 17 to 56 LCD segment outputs 2001 Oct 02 5 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates handbook, halfpage SDA 1 56 S39 SCL 2 55 S38 SYNC 3 54 S37 CLK 4 53 S36 VDD 5 52 S35 OSC 6 51 S34 A0 7 50 S33 A1 8 49 S32 A2 9 48 S31 SA0 10 47 S30 VSS 11 46 S29 VLCD 12 45 S28 BP0 13 44 S27 BP2 14 43 S26 PCF8576T BP1 15 42 S25 BP3 16 41 S24 S0 17 40 S23 S1 18 39 S22 S2 19 38 S21 S3 20 37 S20 S4 21 36 S19 S5 22 35 S18 S6 23 34 S17 S7 24 33 S16 S8 25 32 S15 S9 26 31 S14 S10 27 30 S13 S11 28 29 S12 MBK278 Fig.2 Pin configuration; SOT190-1. 2001 Oct 02 6 PCF8576 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6 FUNCTIONAL DESCRIPTION PCF8576 The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576. The internal oscillator is selected by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application. The PCF8576 is a versatile peripheral device designed to interface to any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The display configurations possible with the PCF8576 depend on the number of active backplane outputs required; a selection of display configurations is given in Table . All of the display configurations given in Table can be implemented in the typical system shown in Fig.3. Selection of display configurations NUMBER OF 14-SEGMENTS ALPHANUMERIC 7-SEGMENTS NUMERIC DOT MATRIX BACKPLANES SEGMENTS INDICATOR SYMBOLS DIGITS CHARACTERS INDICATOR SYMBOLS 4 160 20 20 10 20 160 dots (4 x 40) 3 120 15 15 8 8 120 dots (3 x 40) 2 80 10 10 5 10 80 dots (2 x 40) 1 40 5 5 2 12 40 dots (1 x 40) handbook, full pagewidth V DD R tr 2CB V DD V 5 SDA HOST MICROPROCESSOR/ MICROCONTROLLER SCL OSC 1 17 to 56 40 segment drives PCF8576 2 6 13 to 16 7 ROSC LCD 12 A0 8 9 A1 A2 10 4 backplanes Fig.3 Typical system configuration. 7 (up to 160 elements) 11 SA0 V SS V SS 2001 Oct 02 LCD PANEL MBK277 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.1 6.3 Power-on reset 1. All backplane outputs are set to VDD. 2. All segment outputs are set to VDD. 3. The drive mode `1 : 4 multiplex with 13bias' is selected. 4. Blinking is switched off. 5. Input and output bank selectors are reset (as defined in Table 4). 6. The LCD voltage selector The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of Vop = VDD - VLCD and the resulting discrimination ratios (D), are given in Table 1. At power-on the PCF8576 resets to a starting condition as follows: I2C-bus PCF8576 A practical value for Vop is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is Vop > 3Vth approximately. interface is initialized. 7. The data pointer and the subaddress counter are cleared. Multiplex drive ratios of 1 : 3 and 1 : 4 with 12bias are possible but the discrimination and hence the contrast Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or 6.2 LCD bias generator 21 ---------- = 1.528 for 1 : 4 multiplex). 3 The advantage of these modes is a reduction of the LCD full-scale voltage Vop as follows: The full-scale LCD voltage (Vop) is obtained from VDD - VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin 12. Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between VDD and VLCD. The centre resistor can be switched out of the circuit to provide a 12bias voltage level for the 1 : 2 multiplex configuration. * 1 : 3 multiplex (12bias): Vop = 6 x V off rms = 2.449 Voff(rms) * 1 : 4 multiplex (12bias): Vop = (4 x 3) ---------------------3 = 2.309 Voff(rms) These compare with Vop = 3 Voff(rms) when 13bias is used. Table 1 Preferred LCD drive modes: summary of characteristics NUMBER OF LCD DRIVE MODE BACKPLANES static 1 LEVELS 2 static 1 2 1 3 1 3 1 3 1:2 2 3 1:2 2 4 1:3 3 4 1:4 4 4 2001 Oct 02 LCD BIAS CONFIGURATION 8 V off(rms) --------------------V op V on(rms) --------------------V op V on(rms) D = --------------------V off(rms) 0 1 0.354 0.791 2.236 0.333 0.745 2.236 0.333 0.638 1.915 0.333 0.577 1.732 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4 PCF8576 When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.7. LCD drive mode waveforms The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.4. When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.8. When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8576 allows use of 1 bias or 1 bias in this mode as shown in Figs 5 and 6. 2 3 T frame LCD segments V DD BP0 V LCD state 1 (on) V DD state 2 (off) Sn V LCD VDD Sn 1 V LCD (a) waveforms at driver V op state 1 0 Vop V op state 2 0 Vop (b) resultant waveforms at LCD segment MBE539 V state1(t) = V S (t) - V BP0(t) n V on(rms) = V op V state2(t) = V S n+1 (t) - V BP0(t) V off(rms) = 0 V Fig.4 Static drive mode waveforms (Vop = VDD - VLCD). 2001 Oct 02 9 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 T frame VDD BP0 (VDD LCD segments V LCD )/2 V LCD state 1 VDD BP1 (VDD state 2 V LCD )/2 V LCD VDD Sn V LCD VDD Sn 1 V LCD (a) waveforms at driver Vop V op /2 state 1 0 V op /2 Vop Vop V op /2 state 2 0 V op /2 Vop (b) resultant waveforms at LCD segment MBE540 V state1(t) = V S (t) - V BP0(t) n V on(rms) = 0.791V op V state2(t) = V S (t) - V BP1(t) n V off(rms) = 0.354V op Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 12bias (Vop = VDD - VLCD). 2001 Oct 02 10 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 T frame BP0 VDD V DD Vop /3 VDD 2Vop /3 VLCD BP1 VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn 1 VDD V DD Vop /3 VDD 2Vop /3 VLCD LCD segments state 1 state 2 (a) waveforms at driver Vop 2Vop /3 state 1 Vop /3 0 Vop /3 2Vop /3 Vop state 2 Vop 2Vop /3 Vop /3 0 Vop /3 2Vop /3 Vop (b) resultant waveforms at LCD segment MBE541 V state1(t) = V S (t) - V BP0(t) n V on(rms) = 0.745V op V state2(t) = V S (t) - V BP1(t) n V off(rms) = 0.333V op Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 13bias (Vop = VDD - VLCD). 2001 Oct 02 11 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 T frame BP0 VDD V DD Vop /3 VDD 2Vop /3 VLCD BP1 VDD V DD Vop /3 VDD 2Vop /3 VLCD BP2/S23 VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn 1 VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn 2 VDD V DD Vop /3 VDD 2Vop /3 VLCD LCD segments state 1 state 2 (a) waveforms at driver state 1 Vop 2V op /3 Vop /3 0 Vop /3 2V op /3 Vop state 2 Vop 2V op /3 Vop /3 0 Vop /3 2V op /3 Vop (b) resultant waveforms at LCD segment MBE542 V state1(t) = V S (t) - V BP0(t) n V on(rms) = 0.638V op V state2(t) = V S (t) - V BP1(t) n V off(rms) = 0.333V op Fig.7 Waveforms for the 1 : 3 multiplex drive mode (Vop = VDD - VLCD). 2001 Oct 02 12 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 T frame BP0 VDD V DD Vop /3 VDD 2Vop /3 VLCD BP1 VDD V DD Vop /3 VDD 2Vop /3 VLCD BP2 VDD V DD Vop /3 VDD 2Vop /3 VLCD BP3 VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn 1 VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn 2 VDD V DD Vop /3 VDD 2Vop /3 VLCD Sn 3 VDD V DD Vop /3 VDD 2Vop /3 VLCD LCD segments state 1 state 2 (a) waveforms at driver state 1 Vop 2Vop /3 V op /3 0 V op /3 2Vop /3 Vop state 2 Vop 2Vop /3 V op /3 0 V op /3 2Vop /3 Vop V state1(t) = V S (t) - V BP0(t) n V on(rms) = 0.577V op (b) resultant waveforms at LCD segment MBE543 V state2(t) = V S (t) - V BP1(t) n V off(rms) = 0.333V op Fig.8 Waveforms for the 1 : 4 multiplex drive mode (Vop = VDD - VLCD). 2001 Oct 02 13 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.5 6.6 Oscillator 6.5.1 The internal logic and the LCD drive signals of the PCF8576 are timed either by the internal oscillator or from an external clock. When the internal oscillator is used, pin OSC should be connected to pin VSS. In this event, the output from pin CLK provides the clock signal for cascaded PCF8566s in the system. Where resistor Rosc to VSS is present, the internal oscillator is selected. The relationship between the oscillator frequency on pin CLK (fclk) and Rosc is shown in Fig.9. The ratio between the clock frequency and the LCD frame frequency depends on the mode in which the device is operating. In the power-saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power dissipation. The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus. MBE531 f clk (kHz) 102 Timing The timing of the PCF8576 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal SYNC maintains the correct timing relationship between the PCF8576s in the system. The timing also generates the LCD frame frequency which it derives as an integer multiple of the clock frequency (see Table 2). The frame frequency is set by the MODE SET commands when internal clock is used, or by the frequency applied to pin CLK when external clock is used. INTERNAL CLOCK 10 3 PCF8576 When a device is unable to digest a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs. max min Table 2 10 10 2 103 R osc (k) 10 4 LCD frame frequencies PCF8576 MODE FRAME FREQUENCY NOMINAL FRAME FREQUENCY (Hz) 3.4 x 10 7 f clk ------------------------ ( kHz ) R osc Normal mode f clk ------------2880 64 Fig.9 Oscillator frequency as a function of Rosc. Power-saving mode f clk ---------480 64 6.5.2 EXTERNAL CLOCK 6.7 The condition for external clock is made by connecting pin OSC to pin VDD; pin CLK then becomes the external clock input. The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM. The clock frequency (fclk) determines the LCD frame frequency and the maximum rate for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data rate of 100 kHz, fclk should be chosen to be above 125 kHz. 6.8 Shift register The shift register serves to transfer display information from the display RAM to the display latch while previous data is displayed. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 2001 Oct 02 Display latch 14 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.9 correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 40 segments operated with respect to backplane BP0 (see Fig.10). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. Segment outputs The LCD drive section includes 40 segment outputs pins S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. When less than 40 segment outputs are required the unused segment outputs should be left open-circuit. 6.10 When display data is transmitted to the PCF8576 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.11; the RAM filling organization depicted applies equally to other LCD types. Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be connected together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.11 PCF8576 With reference to Fig.11, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. Display RAM The display RAM is a static 40 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on state of the corresponding LCD segment; similarly, a logic 0 indicates the off state. There is a one-to-one display RAM addresses (rows) / segment outputs (S) 0 1 2 3 4 35 36 37 38 39 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3 MBE525 Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs. 2001 Oct 02 15 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.12 Data pointer 6.14 The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Fig.11. The data pointer is automatically incremented in accordance with the chosen LCD configuration. That is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode) or by two (1 : 4 multiplex drive mode). 6.13 Output bank selector This selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to be selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. The PCF8576 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of bit 0 contents. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. Subaddress counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. 6.15 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using the BANK SELECT command. The input bank selector functions independent of the output bank selector. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1 : 3 multiplex mode). 2001 Oct 02 PCF8576 16 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.16 Blinker bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. The display blinking capabilities of the PCF8576 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, as shown in Table 3. In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command. An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By means of the output Table 3 PCF8576 Blinking frequencies BLINKING MODE NORMAL OPERATING MODE RATIO POWER-SAVING MODE RATIO NOMINAL BLINKING FREQUENCY Off - - blinking off 2 Hz f clk ---------------92160 f clk ---------------15360 2 Hz 1 Hz f clk -------------------184320 f clk ---------------30720 1 Hz 0.5 Hz f clk -------------------368640 f clk ---------------61440 0.5 Hz 2001 Oct 02 17 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... static a 2 Sn 3 Sn 4 Sn 5 Sn 6 b f g e 1 Sn 2 Sn 3 18 1:3 Sn 1 Sn 2 Sn 7 DP BP1 e c d DP b f BP1 c 0 1 2 3 BP2 DP a b BP0 n 5 n 6 n 7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x n n 1 n 2 n 3 a b x x f g x x e c x x d DP x x n n 1 n 2 b DP c x a d g x f e x x n n 1 a c b DP f e g d LSB c b a f g e d DP e 0 1 2 3 bit/ BP BP1 c d MSB a b f LSB g e c d DP MSB LSB b DP c a d g f e BP2 g BP3 MSB a c b DP f LSB e g d DP Product specification Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus. MBK389 PCF8576 x = data bit unchanged. n 4 Sn bit/ BP f 1 n 3 BP0 a Sn Sn 0 1 2 3 bit/ BP d multiplex n 2 b f e 1:4 n 1 BP0 a g multiplex n MSB 0 1 2 3 bit/ BP g multiplex transmitted display byte 1 Sn c Sn Sn BP0 Sn d 1:2 display RAM filling order handbook, full pagewidth Sn LCD backplanes Philips Semiconductors LCD segments Universal LCD driver for low multiplex rates 2001 Oct 02 drive mode Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7 CHARACTERISTICS OF THE I2C-BUS 7.5 The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 In single device application, the hardware subaddress inputs A0, A1 and A2 are normally connected to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are connected to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. Bit transfer (see Fig.12) START and STOP conditions (see Fig.13) In the power-saving mode it is possible that the PCF8576 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8576 forces the SCL line to LOW until its internal operations are completed. This is known as the `clock synchronization feature' of the I2C-bus and serves to slow down fast transmitters. Data loss does not occur. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 7.3 System configuration (see Fig.14) A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. 7.4 PCF8576 I2C-bus controller The PCF8576 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 7.2 PCF8576 7.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. Acknowledge (see Fig.15) 7.7 The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 2001 Oct 02 I2C-bus protocol Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576. The least significant bit of the slave address that a PCF8576 will respond to is defined by the level connected at its input pin SA0. Therefore, two types of PCF8576 can be distinguished on the same I2C-bus which allows: * Up to 16 PCF8576s on the same I2C-bus for very large LCD applications * The use of two types of LCD multiplex on the same I2C-bus. The I2C-bus protocol is shown in Fig.16. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8576 slave addresses available. All PCF8576s with the corresponding SA0 level acknowledge in parallel with the slave address but all PCF8576s with the alternative SA0 level ignore the whole I2C-bus transfer. 19 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates After acknowledgement, one or more command bytes (m) follow which define the status of the addressed PCF8576s. 7.8 PCF8576 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position (Fig.17). When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates the last command byte of the transfer. Further bytes will be regarded as display data. The last command byte is tagged with a cleared most significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCF8576s on the bus. After the last command byte, a series of display data bytes (n) may follow. These display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8576 device. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8576. After the last display byte, the I2C-bus master issues a STOP condition (P). The five commands available to the PCF8576 are defined in Table 4. SDA SCL data line stable; data valid change of data allowed MBA607 Fig.12 Bit transfer. handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition Fig.13 Definition of START and STOP conditions. 2001 Oct 02 20 MBC622 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER PCF8576 MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL MGA807 Fig.14 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.15 Acknowledgement on the I2C-bus. 2001 Oct 02 21 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 acknowledge by A0, A1 and A2 selected PCF8576 only acknowledge by all addressed PCF8576s handbook, full pagewidth R/ W slave address S S 0 1 1 1 0 0 A 0 A C COMMAND 0 1 byte n A DISPLAY DATA 1 byte(s) n Fig.16 I2C-bus protocol. C LSB REST OF OPCODE MSA833 C = 0; last command. C = 1; commands continue. Fig.17 General format of command byte. 2001 Oct 02 22 P 0 byte(s) MBK279 MSB A update data pointers and if necessary, subaddress counter Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 4 PCF8576 Definition of PCF8576 commands COMMAND MODE SET OPCODE C 1 0 LP E B OPTIONS M1 M0 DESCRIPTION Table 5 Defines LCD drive mode. Table 6 Defines LCD bias configuration. Table 7 Defines display status. The possibility to disable the display allows implementation of blinking under external control. Table 8 Defines power dissipation mode. LOAD DATA C 0 P5 P4 P3 P2 POINTER P1 P0 Table 9 Six bits of immediate data, bits P5 to P0, are transferred to the data pointer to define one of forty display RAM addresses. DEVICE SELECT C 1 1 0 0 A2 A1 A0 Table 10 Three bits of immediate data, bits A2 to A0, are transferred to the subaddress counter to define one of eight hardware subaddresses. BANK SELECT C 1 1 1 1 0 I O Table 11 Defines input bank selection (storage of arriving display data). Table 12 Defines output bank selection (retrieval of LCD display data). The BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes. Table 13 Defines the blinking frequency. Table 14 Selects the blinking mode; normal operation with frequency set by BF1, BF0 or blinking by alternation of display RAM banks. Alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes. BLINK C 1 Table 5 1 1 0 A BF1 BF0 MODE SET option 1 Table 8 LCD DRIVE MODE DRIVE MODE BACKPLANE MODE SET option 4 MODE BITS M1 M0 Static 1 BP 0 1 1:2 MUX (2 BP) 1 0 1:3 MUX (3 BP) 1 1 1:4 MUX (4 BP) 0 0 BIT LP Normal mode 0 Power-saving mode 1 Table 9 LOAD DATA POINTER option 1 DESCRIPTION BITS 6-bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0 Table 6 MODE SET option 2 LCD BIAS Table 10 DEVICE SELECT option 1 BIT B 1 3bias 0 DESCRIPTION 1 2bias 1 3-bit binary value of 0 to 7 Table 7 A2 A1 A0 Table 11 BANK SELECT option 1 MODE SET option 3 DISPLAY STATUS BITS STATIC BIT E 1 : 2 MUX BIT I Disabled (blank) 0 RAM bit 0 RAM bits 0 and 1 0 Enabled 1 RAM bit 2 RAM bits 2 and 3 1 2001 Oct 02 23 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 12 BANK SELECT option 2 STATIC 7.10 1 : 2 MUX BIT O RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 BITS BLINK FREQUENCY BF0 Off 0 0 2 Hz 0 1 1 Hz 1 0 0.5 Hz 1 1 The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8576s. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when PCF8576s with differing SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8576 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8576 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8576 are shown in Fig.19. Table 14 BLINK option 2 BLINK MODE BIT A Normal blinking 0 Alternation blinking 1 7.9 Cascaded operation In large display configurations, up to 16 PCF8576s can be distinguished on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). When cascaded PCF8576s are synchronized so that they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8576s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.18). Table 13 BLINK option 1 BF1 PCF8576 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8576 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. For single plane wiring of packaged PCF8576s and chip-on-glass cascading, see Chapter 12. 2001 Oct 02 24 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 handbook, full pagewidth VDD SDA 1 SCL 2 SYNC VLCD 12 5 17 to 56 40 segment drives LCD PANEL 3 PCF8576 CLK 4 OSC 6 (up to 2560 elements) 13, 15 14, 16 7 8 A0 9 A1 10 A2 BP0 to BP3 (open-circuit) 11 SA0 VSS V LCD VDD R tr 2CB V DD V 5 HOST MICROPROCESSOR/ MICROCONTROLLER SDA SCL SYNC CLK OSC 1 17 to 56 40 segment drives 2 PCF8576 3 13, 15 14, 16 4 6 4 backplanes BP0 to BP3 MBK280 7 VSS LCD 12 A0 8 A1 9 A2 10 11 SA0 V SS Fig.18 Cascaded PCF8576 configuration. 2001 Oct 02 25 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 1 Tframe = f frame handbook, full pagewidth BP0 SYNC (a) static drive mode. BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1 : 2 multiplex drive mode. BP2 SYNC (c) 1 : 3 multiplex drive mode. BP3 SYNC MBE535 (d) 1 : 4 multiplex drive mode. Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance of the SYNC line should be increased (e.g. by an external capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may be countered by an external pull-up resistor. Fig.19 Synchronization of the cascade for the various PCF8576 drive modes. 2001 Oct 02 26 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage -0.5 +11.0 V VLCD LCD supply voltage VDD - 11.0 VDD V VI input voltage SDA, SCL, CLK, SYNC, SA0, OSC, A0 to A2 VSS - 0.5 VDD + 0.5 V VO output voltage S0 to S39, BP0 to BP3 VLCD - 0.5 VDD + 0.5 V II DC input current - 20 mA IO DC output current - 25 mA IDD, ISS, ILCD VDD, VSS or VLCD current - 50 mA Ptot total power dissipation - 400 mW PO power dissipation per output - 100 mW Tstg storage temperature -65 +150 C 9 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices" ). 2001 Oct 02 27 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 10 DC CHARACTERISTICS VDD = 2 to 9 V; VSS = 0 V; VLCD = VDD - 2 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage VLCD LCD supply voltage note 1 IDD supply current note 2 2 - 9 VDD - 9 - VDD - 2 V V normal mode fclk = 200 kHz - - 180 A power-saving mode fclk = 35 kHz; VDD = 3.5 V; VLCD = 0 V; A0, A1 and A2 connected to VSS - - 60 A VSS - 0.3VDD V Logic VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDD - VDD V VOL LOW-level output voltage IOL = 0 mA - - 0.05 V VOH HIGH-level output voltage IOH = 0 mA VDD - 0.05 - - V IOL1 LOW-level output current CLK, SYNC VOL = 1 V; VDD = 5 V 1 - - mA IOH1 HIGH-level output current CLK VOH = 4 V; VDD = 5 V 1 - - mA IOL2 LOW-level output current SDA and SCL VOL = 0.4 V; VDD = 5 V 3 - - mA IL1 leakage current SA0, A0 to A2, CLK, SDA and SCL VI = VDD or VSS - - 1 A IL2 leakage current OSC VI = VDD - - 1 A Ipd A0, A1, A2 and OSC pull-down current VI = 1 V; VDD = 5 V 20 50 150 A RSYNC pull-up resistor (SYNC) 20 50 150 k VPOR Power-on reset voltage level note 3 - 1.0 1.6 V CI input capacitance note 4 - - 7 pF LCD outputs VBP DC voltage component BP0 to BP3 CBP = 35 nF - 20 - mV VS DC voltage component S0 to S39 CS = 5 nF - 20 - mV RBP output resistance BP0 to BP3 note 5; VLCD = VDD - 5 V - - 5 k RS output resistance S0 to S39 note 5; VLCD = VDD - 5 V - - 7.5 k Notes 1. VLCD VDD - 3 V for 13bias. 2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 3. Resets all logic when VDD < VPOR. 4. Periodically sampled, not 100% tested. 5. Outputs measured one at a time. 2001 Oct 02 28 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 11 AC CHARACTERISTICS VDD = 2 to 9 V; VSS = 0 V; VLCD = VDD - 2 V to VDD - 9 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fclk PARAMETER CONDITIONS MIN. TYP. MAX. UNIT oscillator frequency on pin CLK normal mode VDD = 5 V; note 1 125 200 288 kHz power-saving mode VDD = 3.5 V 21 31 48 kHz tclkH CLK HIGH time 1 - - s tclkL CLK LOW time 1 - - s tPSYNC SYNC propagation delay time - - 400 ns tSYNCL SYNC LOW time tPLCD driver delays with test loads see Fig.21 1 - - s VLCD = VDD - 5 V; see Fig.20 - - 30 s Timing characteristics: I2C-bus; note 2; see Fig.22 tSW tolerable spike width on bus - - 100 ns tBUF bus free time 4.7 - - s tHD;STA START condition hold time 4.0 - - s tSU;STA set-up time for a repeated START condition 4.7 - - s tLOW SCL LOW time 4.7 - - s tHIGH SCL HIGH time 4.0 - - s tr SCL and SDA rise time - - 1 s tf SCL and SDA fall time - - 0.3 s CB capacitive bus line load - - 400 pF tSU;DAT data set-up time 250 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 4.0 - - s Notes 1. At fclk < 125 kHz, I2C-bus maximum transmission speed is derated. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SYNC 6.8 V DD (2%) CLK 3.3 k 0.5VDD (2%) BP0 to BP3, and S0 to S39 SDA, SCL 1.5 k VDD (2%) 1 nF VDD MBE544 Fig.20 Test loads. 2001 Oct 02 29 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 1/ f clk handbook, full pagewidth t clkL t clkH 0.7VDD 0.3VDD CLK 0.7VDD SYNC 0.3VDD t PSYNC t PSYNC t SYNCL 0.5 V BP0 to BP3, and S0 to S39 (VDD = 5 V) 0.5 V t PLCD MBE545 Fig.21 Driver timing waveforms. handbook, full pagewidth SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t HIGH t SU;DAT SDA MGA728 t SU;STA Fig.22 I2C-bus timing waveforms. 2001 Oct 02 30 t SU;STO Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 11.1 PCF8576 Typical supply current characteristics MBE529 MBE530 50 50 I SS (A) I LCD (A) 40 normal mode 40 30 30 20 20 power-saving mode 10 10 0 100 0 f frame (Hz) 0 200 100 0 VDD = 5 V; VLCD = 0 V; Tamb = 25 C. f frame (Hz) VDD = 5 V; VLCD = 0 V; Tamb = 25 C. Fig.23 -ISS as a function of fframe. Fig.24 -ILCD as a function of fframe. MBE528 - 1 50 MBE527 - 1 50 handbook, halfpage handbook, halfpage I LCD I SS (A) (A) 40 normal mode f clk = 200 kHz 40 200 o 85 C 30 30 20 20 o 25 C o power-saving mode f clk = 35 kHz 10 40 C 10 0 0 0 5 V DD (V) 10 0 VLCD = 0 V; external clock; Tamb = 25 C. V DD (V) VLCD = 0 V; external clock; fclk = nominal frequency. Fig.25 ISS as a function of VDD. 2001 Oct 02 5 Fig.26 ILCD as a function of VDD. 31 10 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 11.2 PCF8576 Typical characteristics of LCD outputs MBE532 - 1 R MBE526 2.5 10 handbook, halfpage R O(max) (k) RS O(max) (k) 2.0 RS 1.5 1 R BP R BP 1.0 0.5 -1 10 0 3 VDD (V) 0 40 6 VLCD = 0 V; Tamb = 25 C. 40 80 120 o Tamb( C) VDD = 5 V; VLCD = 0 V. Fig.27 RO(max) as a function of VDD. 2001 Oct 02 0 Fig.28 RO(max) as a function of Tamb. 32 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... CLK V DD VSS V LCD SDA 1 56 S39 1 56 S79 SCL 2 55 S38 2 55 S78 SYNC 3 54 S37 3 54 S77 CLK 4 53 S36 4 53 S76 V DD 5 52 S35 5 52 S75 OSC 6 51 S34 6 51 S74 A0 7 50 S33 7 50 S73 A1 8 49 S32 8 49 S72 33 A2 9 48 S31 9 48 S71 SA0 10 47 S30 10 47 S70 V SS 11 46 S29 11 46 S69 V LCD 12 45 S28 12 45 S68 BP0 13 44 S27 BP0 13 44 S67 BP2 14 43 S26 BP2 14 43 S66 BP1 15 42 S25 BP1 15 42 S65 BP3 16 41 S24 BP3 16 41 S64 S0 17 40 S23 S40 17 40 S63 S1 18 39 S22 S41 18 39 S62 S2 19 38 S21 S42 19 38 S61 S3 20 S43 20 34 S17 34 S57 open PCF8576T S7 24 33 S16 S47 24 33 S56 S8 25 32 S15 S48 25 32 S55 S9 26 31 S14 S49 26 31 S54 S10 27 30 S13 S50 27 30 S53 S11 28 29 S12 S51 28 29 S52 S11 S12 S13 S39 S40 S50 S51 segments Fig.29 Single plane wiring of packaged PCF8576Ts. S52 S53 S79 MBK281 Product specification backplanes S10 PCF8576T PCF8576 S0 Philips Semiconductors SCL SYNC Universal LCD driver for low multiplex rates 12 APPLICATION INFORMATION andbook, full pagewidth 2001 Oct 02 SDA Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 12.1 Chip-on-glass cascadability in single plane PCF8576 and the backplane output pads. The only bus line that does not require a second opening to lead through to the next PCF8576 is VLCD, being the cascade centre. The placing of VLCD adjacent to VSS allows the two supplies to be connected together. In chip-on-glass technology, where driver devices are bonded directly onto glass of the LCD, it is important that the devices may be cascaded without the crossing of conductors, but the paths of conductors can be continued on the glass under the chip. All of this is facilitated by the PCF8576 bonding pad layout (see Fig.30). Pads needing bus interconnection between all PCF8576s of the cascade are VDD, VSS, VLCD, CLK, SCL, SDA and SYNC. These lines may be led to the corresponding pads of the next PCF8576 through the wide opening between VLCD pad When an external clocking source is to be used, OSC of all devices should be connected to VDD. The pads OSC, A0, A1, A2 and SA0 have been placed between VSS and VDD to facilitate wiring of oscillator, hardware subaddress and slave address. S18 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 handbook, full pagewidth S17 13 BONDING PAD INFORMATION 34 33 32 31 30 29 28 27 26 25 24 23 22 21 35 S19 36 S20 37 S21 38 S22 39 S23 40 S24 41 S25 20 S3 19 S2 18 S1 17 S0 16 BP3 15 BP1 14 BP2 13 BP0 42 x 4.12 mm 0 S33 50 VSS 10 SA0 9 51 52 53 54 55 56 1 2 3 4 5 6 7 8 3.07 mm MBK282 Bonding pad dimensions: 120 x 120 m. Gold bump dimensions: 94 x 94 x 25 m. Fig.30 Bonding pad locations. 2001 Oct 02 34 VLCD 11 A1 49 A0 S32 cascade centre 12 OSC 48 VDD S31 CLK 47 SYNC S30 PCF8576 SCL 46 SDA S29 S39 45 S38 S28 0 y S37 44 S36 S27 S35 43 S34 S26 A2 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 15 Bonding pad locations (dimensions in m) All x and y coordinates are referenced to centre of chip (see Fig.30). COORDINATES SYMBOL COORDINATES SYMBOL PAD x y PCF8576 PAD x y S13 30 -555 1900 S14 31 -755 1900 S15 32 -955 1900 S16 33 -1155 1900 S17 34 -1375 1900 S18 35 -1375 1660 S19 36 -1375 1420 S20 37 -1375 1200 S21 38 -1375 1000 S22 39 -1375 800 S23 40 -1375 600 S24 41 -1375 400 S25 42 -1375 200 S26 43 -1375 -200 S27 44 -1375 -400 S28 45 -1375 -600 S29 46 -1375 -800 S30 47 -1375 -1000 S31 48 -1375 -1200 S32 49 -1375 -1420 S33 50 -1375 -1660 S34 51 -1375 -1900 S35 52 -1155 -1900 S36 53 -955 -1900 S37 54 -755 -1900 S38 55 -555 -1900 S39 56 -355 -900 SDA 1 -155 -1900 SCL 2 45 -1900 SYNC 3 245 -1900 CLK 4 445 -1900 VDD 5 645 -1900 OSC 6 865 -1900 A0 7 1105 -1900 A1 8 1375 -1900 A2 9 1375 -1700 SA0 10 1375 -1500 VSS 11 1375 -1300 VLCD 12 1375 -1100 BP0 13 1375 300 BP2 14 1375 500 BP1 15 1375 700 BP3 16 1375 900 S0 17 1375 1100 S1 18 1375 1300 S2 19 1375 1500 S3 20 1375 1700 S4 21 1375 1900 S5 22 1105 1900 S6 23 865 1900 S7 24 645 1900 S8 25 445 1900 S9 26 245 1900 S10 27 45 1900 Pad pitch 200 m S11 28 -155 1900 Pad size, aluminium 120 x 120 m S12 29 -355 1900 Gold bump dimensions 94 x 94 x 25 m 2001 Oct 02 Table 16 Bonding pad dimensions 35 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 14 TRAY INFORMATION: PCF8576U x handbook, full pagewidth G A C H y 1,1 2,1 x,1 D 1,2 B F x,y 1,y A A E M J SECTION A-A MGU431 For dimensions see Table 18. Fig.31 Tray details. Table 17 Tray dimensions (see Fig.33) SYMBOL DESCRIPTION VALUE handbook, halfpage PC8576U MGU432 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Fig.32 Tray alignment. 2001 Oct 02 36 A pocket pitch; x direction 6.32 mm B pocket pitch; y direction 6.32 mm C pocket width; x direction 4.55 mm D pocket width; y direction 4.55 mm E tray width; x direction 50.67 mm F tray width; y direction 50.67 mm G cut corner to pocket 1,1 centre 6.32 mm H cut corner to pocket 1,1 centre 6.32 mm J tray thickness 3.94 mm M pocket depth 0.61 mm x number of pockets; x direction 7 y number of pockets; y direction 7 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 15 TRAY INFORMATION: PCF8576U/2 x handbook, full pagewidth y G A C H 1,1 2,1 x,1 D 1,2 B F x,y 1,y A A E K M L J SECTION A-A MGW014 For dimensions see Table 17. Fig.33 Tray details. Table 18 Tray dimensions (see Fig.31) SYMBOL DESCRIPTION VALUE handbook, halfpage PCF8576U/2 MGW015 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Fig.34 Tray alignment. 2001 Oct 02 37 A pocket pitch; x direction 5.33 mm B pocket pitch; y direction 7.11 mm C pocket width; x direction 3.43 mm D pocket width; y direction 4.67 mm E tray width; x direction 50.67 mm F tray width; y direction 50.67 mm G cut corner to pocket 1,1 centre 6.67 mm H cut corner to pocket 1,1 centre 7.56 mm J tray thickness 3.94 mm K tray cross section 1.76 mm L tray cross section 2.46 mm M pocket depth 0.89 mm x number of pockets; x direction 8 y number of pockets; y direction 6 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 16 PACKAGE OUTLINES VSO56: plastic very small outline package; 56 leads SOT190-1 D E A X c y HE v M A Z 56 29 Q A2 A (A 3) A1 pin 1 index Lp L 1 detail X 28 w M bp e 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 3.3 0.3 0.1 3.0 2.8 0.25 0.42 0.30 0.22 0.14 21.65 21.35 11.1 11.0 0.75 15.8 15.2 2.25 1.6 1.4 1.45 1.30 0.2 0.1 0.1 0.90 0.55 0.13 0.012 0.004 0.12 0.11 0.01 0.017 0.0087 0.85 0.012 0.0055 0.84 0.44 0.62 0.0295 0.43 0.60 0.089 0.063 0.055 inches 0.057 0.035 0.008 0.004 0.004 0.051 0.022 Note 1. Plastic or metal protrusions of 0.3 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 96-04-02 97-08-11 SOT190-1 2001 Oct 02 EUROPEAN PROJECTION 38 o 7 0o Philips Semiconductors Product specification Universal LCD driver for low multiplex rates If wave soldering is used the following conditions must be observed for optimal results: 17 SOLDERING 17.1 Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 17.2 PCF8576 - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 17.3 17.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. To overcome these problems the double-wave soldering method was specifically developed. 2001 Oct 02 Manual soldering 39 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 17.5 PCF8576 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Oct 02 40 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 18 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective specification Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary specification Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product specification Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. 19 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products 2001 Oct 02 41 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Oct 02 42 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates NOTES 2001 Oct 02 43 PCF8576 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA73 (c) Koninklijke Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403512/04/pp44 Date of release: 2001 Oct 02 Document order number: 9397 750 08044