Product Brief PE42674 Flip Chip SP7T UltraCMOSTM WEDGE Switch 100 - 3000 MHz, +67 dBm IIP3 Figure 1. Functional Diagram Features * One WEDGE compliant port (TX1), two RX1 TX1 WCDMA RX2 TX2 GSM 1800/1900 RX3 TX3 GSM 850/900 * * * * RX4 * CMOS Control Driver and ESD V1 V2 * * V3 * Figure 2. Die Top View Product Description ANT RX1 14 RX2 13 RX3 12 RX4 11 GND 10 15 PE42674 Die GSM/EDGE TX ports, four RX ports Three pin CMOS logic control with integral decoder/driver Exceptional harmonic performance: 2fo = -85 dBc and 3fo = -79 dBc Low TX insertion loss: 0.65 dB at 900 MHz, 0.75 dB at 1900 MHz TX - RX Isolation of 38.5 dB at 900 MHz, 31 dB at 1900 MHz 1500 V HBM ESD tolerance all ports +67 dBm IIP3 -109 dBm IMD3 No blocking capacitors required 1 TX1 2 GND 3 TX2 4 TX3 9 8 7 6 5 V1 V2 V3 VDD GND Figure 3. Package Type: Flip Chip Document No. 70-0227-01 www.psemi.com Contact sales@psemi.com for full version of datasheet The PE42674 is a HaRPTM-enhanced SP7T RF Switch developed on the UltraCMOSTM process technology. This Flip Chip is comprised of three TX and four RX ports and is intended for use in GSM/EDGE/PCS/DCS/ WCDMA handsets. An on-chip CMOS decode logic facilitates three-pin low voltage CMOS control. High ESD tolerance of 1500 V at all ports, no blocking capacitor requirements, and on-chip SAW filter over-voltage protection devices make this the ultimate in integration and ruggedness. Peregrine's HaRPTM technology enhancements deliver high linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOSTM process, providing performance superior to GaAs with the economy and integration of conventional CMOS. (c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 4 PE42674 Product Brief Table 1. Target Electrical Specifications @ +25 C, VDD = 2.75 V Parameter Typ Units 0.65 0.75 0.80 0.90 1.0 dB dB dB dB dB 20 dB Isolation TX - RX (850 / 900) TX - RX (1800 / 1900)2 TX - TX (850 / 900) TX - TX (1800 / 1900) TX1 - RX (1900 / 2100)2 TX - TX1 (850 / 900)2 TX - TX1 (1800 / 1900)2 38.5 31 30.5 25 30 30 25 dB dB dB dB dB dB dB 2nd Harmonic3 TX3 850 / 900 MHz, +35 dBm output power, 50 TX2 1800 / 1900 MHz, +33 dBm output power, 50 -85 -84 dBc dBc 3rd Harmonic3 TX3 850 / 900 MHz, +35 dBm output power, 50 TX2 1800 / 1900 MHz, +33 dBm output power, 50 -79 -76 dBc dBc WCDMA Band I IMD3 TX1 - Measured in a 50 system at 2.14 GHz at the TX1 port. Input signals are referenced to the ANT port with +20 dBm CW signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz -109 dBm WCDMA Band I IIP3 TX1 - Measured in a 50 system at 2.14 GHz at the TX1 port. Input signals are referenced to the ANT port with +20 dBm CW signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz +67 dBm Switching time 50% of control to (10/90%) RF 2 s Insertion loss 1,2 Return Loss Condition TX - Ant (850 / 900) TX - Ant (1800 / 1900) TX1 - Ant (1900 / 2200) RX - Ant (850 / 900) RX - Ant (1800 / 1900) Port under test in on state 2 Notes: 1. The Device was matched with a 0.5pF cap on the ANT trace. 2. All port combinations may not meet typical performance. Limits will be established after device characterization. 3. Pulsed RF input duty cycle of 50% and 4620 s, measured per 3GPP TS 45.005. Table 2. Operating Ranges Parameter Table 3. Absolute Maximum Ratings Symbol Min Typ Max Units Temperature range TOP -40 25 +85 C VDD Supply Voltage VDD 2.5 2.75 3.2 V IDD Power Supply Current (VDD = 2.75 V) IDD 13 TX input power (VSWR 3:1) 824-915 MHz 50 TX input power4 (VSWR 3:1) 1710-1910 MHz RX input power4 (VSWR =1:1) Min Max Units Power supply voltage -0.3 4.0 V VI Voltage on any DC input -0.3 VDD+ 0.3 V TST Storage temperature range -65 +150 C VDD A 4 PIN(50 ) +35 PIN Symbol dBm +33 PIN Control Voltage High5 VIH Control Voltage Low5 VIL +20 dBm V 1.4 0.4 PIN (:1) Parameter/Conditions TX input power (50 ) 6,7 824-915 MHz +38 TX input power (50 ) 1710-1910 MHz +36 RX input power (50 ) 6,7 +23 6,7 TX input power (VSWR = (:1)6,7 824-915 MHz +35 TX input power (VSWR = (:1)6,7 1710-1910 MHz +33 dBm dBm V Notes: 4. Pulsed RF input duty cycle of 50% and 4620 s, measured per 3GPP TS 45.005. 5. VIH and VIL values apply to a VDD Supply Voltage range of 2.5-2.95 volts. VESD ESD Voltage (HBM, MIL_STD 883 Method 3015.7) 1500 V Notes: 6. Pulsed RF input duty cycle of 50% and 4620 s, measured per 3GPP TS 45.005. 7. V DD within operating range specified in Table 2. Part performance is not guaranteed under these conditions. Exposure to absolute maximum conditions for extended periods of time may adversely affect reliability. Stresses in excess of absolute maximum ratings may cause permanent damage. (c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 4 Document No. 70-0227-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet PE42674 Product Brief Table 4. Pin Descriptions Pin No. Pin Name 1 TX19 RF I/O - TX1 2 GND8 Ground Figure 4. Pad Configuration (Top View) ANT Description 3 9 TX2 RF I/O - TX2 4 TX39 RF I/O - TX3 5 GND8 Ground 6 VDD10 Supply 7 V310 Switch control input, CMOS logic level 8 V210 Switch control input, CMOS logic level 9 V110 Switch control input, CMOS logic level 10 GND8 Ground 11 RX49 RF I/O - RX4 12 RX39 RF I/O - RX3 13 RX29 RF I/O - RX2 14 RX19 RF I/O - RX1 15 ANT9 RF Common - Antenna RX1 14 RX2 13 RX3 12 RX4 11 GND 10 15 PE42674 Die 1 TX1 2 GND 3 TX2 4 TX3 9 8 7 6 5 V1 V2 V3 VDD GND Table 5. Truth Table Path Notes: 8. GND traces should be physically short and connected to ground plane for best performance. 9. Blocking capacitors needed only when non-zero DC voltage present. 10. Application must ensure at least 40 dB of voltage isolation from the RF signal. V3 V2 V1 RX1 - ANT 0 0 0 RX2 - ANT 0 0 1 RX3 - ANT 0 1 0 RX4 - ANT 0 1 1 TX1 - ANT 1 0 0 TX2 - ANT 1 0 1 TX3 - ANT 1 1 0 All Off 1 1 1 Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Table 6. Ordering Information Order Code PE42674DTI PE42674DBI EK-42674-01 Description Package Shipping Method PE42674-DIE-D Bumped Wafer on Film Frame Wafer (Gross Die / Wafer Quantity) PE42674-DIE-304G Die in Waffle Pack 304 Dice / Waffle Pack PE42674-DIE-1H Eval Kit 1/ box Document No. 70-0227-01 www.psemi.com Contact sales@psemi.com for full version of datasheet (c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 4 PE42674 Product Brief Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Space and Defense Products Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). (c)2007 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 4 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Document No. 70-0227-01 UltraCMOSTM RFIC Solutions Contact sales@psemi.com for full version of datasheet