Page 1 of 4
Document No. 70-0227-01 │www. pse mi.com ©2007 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
CMOS
Control Driver
and ESD
RX2
RX3
RX4
RX1
TX2 GSM 1800/1900
TX3 GSM 850/900
TX1 WCDMA
V3V2V1
The PE42674 is a HaRP™-enhanced SP7T
RF Switch develop ed on the UltraCMOS™
process technology. This Flip Chip is
comprised of three TX and four RX ports and
is in tended for use in GSM/EDGE/PCS/DCS/
WCDMA handsets. An on-chip CMOS decode
log ic facilitates three -pin low voltage CMOS
control. Hig h ESD tol eranc e of 15 00 V at al l
p orts, no blocki ng capa cito r requ irements, an d
on-chip SAW filter over-voltage protection
devices make this the ultimate in integration
and ruggedness.
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
proc es s , pr ov i ding perf or m a nc e superior t o
GaAs with th e ec o nom y and in te gr ation of
conventional CMOS.
Product Brief
SP7T UltraCMOS™ WEDGE Switch
100 – 3000 MH z, + 67 dBm IIP 3
Product Description
Figure 1. Functional Diagram
PE42674 Flip Chip
Features
• One WEDGE compliant port (TX1 ), two
GSM/EDGE TX ports, four RX po rts
• Three pin CMOS logic control with
integral decoder/driver
• Exce pti o nal har m o ni c per f or m ance:
2fo = -85 dBc and 3fo = -79 dBc
• Low TX insertion loss: 0.65 dB at
900 MH z, 0.75 dB at 190 0 MHz
• TX – RX Isolation of 38.5 dB at
900 MHz, 31 dB at 1900 MHz
• 1500 V HBM ESD tol er ance all por ts
• +67 dBm IIP3
• -109 dBm IMD3
• No blocking capacitors required
Figure 2. Die Top View
PE42674
Die
11
8
4
5
14 15 1
13 2
12
3
GND
TX2
GND
GND
RX1
RX2
ANT
TX1
10
9 67
TX3
RX3
RX4
V1 V3V2 VDD
Figure 3. Package Type: Flip Chip
Product Brief
PE42674
Page 2 of 4
©2007 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0227-01 │ UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
Table 1. Target Electrical Specifications @ +25 °C, V DD = 2 .75 V
Table 2. Opera ti ng Ranges Table 3. Absolute Max imum Rati ngs
Part perf or m anc e is not guar anteed under t hes e
conditi ons . Expos ur e to absolut e maximum c onditions
for extended per iods of time may adversely aff ec t
reliability . Stress es in exces s of absolute maxim um
rati ngs m ay c aus e per m anent damage.
Parameter Condition Typ Units
Insertion loss 1,2
TX - Ant (850 / 900)
TX - Ant (1800 / 190 0)
TX1 - Ant (1900 / 2200)
RX - A nt (850 / 900)
RX - A nt (180 0 / 1900 )
0.65
0.75
0.80
0.90
1.0
dB
dB
dB
dB
dB
Return Loss Port under t est i n on state 20 dB
Isolation
TX - RX (850 / 900)2
TX - RX (180 0 / 1900 )2
TX - T X (850 / 900)
TX - T X (1800 / 1900)
TX1 - RX (19 00 / 210 0)2
TX - T X 1 (850 / 900 )2
TX - T X 1 (1800 / 1900)2
38.5
31
30.5
25
30
30
25
dB
dB
dB
dB
dB
dB
dB
2nd Harmonic3 TX3 850 / 900 MHz, +35 dB m output power, 50 Ω
TX2 1800 / 19 00 M Hz, +33 dB m out put po wer, 50 Ω -85
-84 dBc
dBc
3rd Harmonic3 TX3 850 / 900 MHz, +35 dB m output power, 50 Ω
TX2 1800 / 19 00 M Hz, +33 dB m out put po wer, 50 Ω -79
-76 dBc
dBc
WCDM A Band I IM D3 TX1 – M easur ed i n a 50 Ω system at 2.14 GHz at the TX1 port. Input si gnals are ref erenc ed to the
ANT port wi th + 20 dBm CW si gnal at 1.95 GHz and -15 dBm CW s i gnal at 1.76 GHz -109 dBm
WCDM A Band I II P3 TX1 – M easur ed i n a 50 Ω system at 2.14 GHz at the TX1 port. Input si gnals are ref erenc ed to the
ANT port wi th + 20 dBm CW si gnal at 1.95 GHz and -15 dBm CW s i gnal at 1.76 GHz +67 dBm
Switchi ng time 50% of control to (10/90% ) RF 2 µs
Notes: 1. The Device was matched with a 0.5pF cap on the ANT trace.
2. All port combinations may not meet typical performance. Limits will be established after device characterization.
3. Pu lsed RF input du ty cycle of 50% and 4620 µs, measured per 3G PP TS 45.005.
Parameter Symbol Min Typ Max Units
Temperature range TOP -40 25 +85 °C
VDD Supply V ol t age VDD 2.5 2.75 3.2 V
IDD Power Supply Current
(VDD = 2. 75 V ) IDD 13 50 µA
TX i nput power4 (VSWR ≤ 3:1)
824-915 M Hz +35 dBm
+33
RX input po wer4 (VSWR =1:1 ) PIN +20 dBm
Control V ol tage Hi gh5 VIH 1.4 V
Control V ol tage L ow5 VIL 0.4 V
PIN
TX i nput power4 (VSWR ≤ 3:1)
1710-1910 MHz
Notes: 4. Pulsed RF input duty cycle of 50% and 4620 µs, measured
per 3GP P TS 4 5.0 05 .
5. VIH and VIL values apply t o a VDD Su pply Voltage range of
2.5-2.95 volts.
Symbol Parameter/Conditions Min Max Units
VDD Power s uppl y vol tage -0.3 4.0 V
VI Volt age on any DC i nput -0.3 VDD+ 0.3 V
TST Storage temperat ure ran ge -65 +150 °C
PIN(50 Ω)
TX i nput power (50 Ω) 6,7
824-915 M Hz +38
dBm
TX i nput power (50 Ω) 6,7
1710-1910 MHz +36
RX input po wer (50 Ω) 6,7 +23
PIN (∞:1)
TX i nput power (VSWR = (∞:1)6,7
824-915 M Hz +35 dBm
TX i nput power (VSWR = (∞:1)6,7
1710-1910 MHz +33
VESD ES D V ol tage (HB M, M I L_STD 88 3
Method 3015. 7) 1500 V
Notes: 6. Pulsed RF input duty cycle of 50% and 4620 µs, measured
per 3GP P TS 4 5.0 05 .
7. VDD within operating range specified in Table 2.
Product Brief
PE42674
Page 3 of 4
Document No. 70-0227-01 │www. pse mi.com ©2007 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latc h-Up Avoidance
Unlike conventional CMOS de v ic es, Ultra CMOS™
devices are immune to latch-up.
Table 5. Truth Table
Table 6. Ordering Information
Table 4. Pin Descriptions Figure 4. Pad Configuration (Top View)
PE42674
Die
11
8
4
5
14 15 1
13 2
12
3
GND
TX2
GND
GND
RX1
RX2
ANT
TX1
10
9 67
TX3
RX3
RX4
V1 V3V2 VDD
Pin No. Pin Name Description
1 TX19 RF I/O - TX1
2 GND8 Ground
3 TX29 RF I/O – TX2
4 TX39 RF I/O – TX3
5 GND8 Ground
6 VDD10 Supply
7 V310 Sw itch control input, CMOS logic level
8 V210 Sw itch control input, CMOS logic level
9 V110 Sw itch control input, CMOS logic level
10 GND8 Ground
11 RX49 RF I/O – RX4
12 RX39 RF I/O – RX3
13 RX29 RF I/O – RX2
14 RX19 RF I/O – RX1
15 ANT9 RF Common – Antenna
Notes: 8. GND traces should be physically short and connected to
gro un d pl ane for bes t per f or m anc e.
9. Blocking capacitors needed only when non-zero DC
voltage present.
10. Application must ensure at least 40 dB of voltage isolation
from the RF signal.
Path V3 V2 V1
RX1 - ANT 0 0 0
RX2 - ANT 0 0 1
RX3 - ANT 0 1 0
RX4 - ANT 0 1 1
TX1 - ANT 1 0 0
TX2 - ANT 1 0 1
TX3 - ANT 1 1 0
All Off 1 1 1
Order Code Description Package Ship pin g Met hod
PE42674DTI PE42674-DIE-D Bumped Wafer on Film Frame Wafer (Gross Die / Wafer Quantity)
PE42674DBI PE42674-DIE-304G Die in Wa f fl e Pac k 304 Dice / Waffle Pack
EK-42674-01 PE42674-DIE-1H Eval Kit 1/ box
Product Brief
PE42674
Page 4 of 4
©2007 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0227-01 │ UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
Sales Offices
The Americas
Peregrine Semiconductor Corporation
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858- 731-9499
Europe
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Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches , France
Tel: +33-1-4741-9173
Fax : +33-1 -4741 -917 3
For a list of representatives in your area, please ref er to our W eb site at: www.psem i.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet cont ains design target specifications for product
development. Specifications and features m ay change in
any manner without notice.
Preliminary Specification
The data sheet cont ains preliminar y data. Additional data
may be added at a later dat e. Peregr ine reserves the right
to change specifications at any tim e without notice in order
to supply t he best possible product .
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify
cust omers of the intended changes by issuing a DCN
(Document Change Notice).
The information in t his dat a sheet is believed to be r eliable.
Howeve r, Peregrine assum es no liability f or th e use of this
information. Use shall be entirely at the user ’s own risk.
No patent rights or licenses t o any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or syst ems intended for surgical implant , or in other
applications intended to support or sust ain life, or in any
application in which the failure of the Per egrine product could
create a situation in which personal injury or death might occur.
Peregr ine assum e s no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine nam e, logo, and UTSi are registered tr ademarks
and UltraCMOS and HaRP ar e trademar ks of Per egrine
Semiconductor Corp.
Spa ce and Defense Products
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Tel: 858-731-9453
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