SZESD7371P2T5G - ON SEMICONDUCTOR

August, 2018 − Rev. 3 1Publication Order Number:

ESD7371/D

ESD7371,

SZESD7371 Series

ESD Protection Diode

Ultra−Low Capacitance

The ESD7371 Series is designed to protect voltage sensitive

components that require ultra−low capacitance from ESD and

transient voltage events. Excellent clamping capability, low

capacitance, high breakdown voltage, high linearity, low leakage, and

fast response time make these parts ideal for ESD protection on

designs where board space is at a premium. It has industry leading

capacitance linearity over voltage making it ideal for RF applications.

This capacitance linearity combined with the extremely small package

and low insertion loss makes this part well suited for use in antenna

line applications for wireless handsets and terminals.

Features

•Industry Leading Capacitance Linearity Over Voltage

•Low Capacitance (0.7 pF Max, I/O to GND)

•Stand−off Voltage: 5.3 V

•Low Leakage: < 1 nA

•Low Dynamic Resistance < 1 W

•IEC61000−4−2 Level 4 ESD Protection

•1000 ESD IEC61000−4−2 Strikes ±8 kV Contact / Air Discharged

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•RF Signal ESD Protection

•RF Switching, PA, and Antenna ESD Protection

•Near Field Communications

•USB 2.0, USB 3.0

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Rating Symbol Value Unit

IEC 61000−4−2 (ESD) (Note 1) 20 kV

IEC 61000−4−5 (ESD) (Note 2) 3.0 A

Total Power Dissipation (Note 3) @ TA = 25°C

Thermal Resistance, Junction−to−Ambient °PD°

RqJA 300

400 mW

°C/W

Junction and Storage Temperature Range TJ, Tstg −55 to

+150 °C

Lead Solder Temperature − Maximum

(10 Second Duration) TL260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

1. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−2 waveform.

2. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.

3. Mounted with recommended minimum pad size, DC board FR−4

MARKING

DIAGRAMS

PIN CONFIGURATION

AND SCHEMATIC

www.onsemi.com

X, XX = Specific Device Code

M = Date Code

Cathode 2

Anode

SOD−323

CASE 477

SOD−523

CASE 502

SOD−923

CASE 514AB

2AG

AE M

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

ESD7371, SZESD7371 Series

www.onsemi.com

See Application Note AND8308/D for further description of survivability specs.

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional

IPP

VRWM

VCVBR VF

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM 5.3 V

Breakdown Voltage (Note 4) VBR IT = 1 mA 7.0 V

Reverse Leakage Current IRVRWM = 5.3 V < 1.0 50 nA

Clamping Voltage (Note 5) VCIPP = 1 A 11 15 V

Clamping Voltage (Note 5) VCIPP = 3 A 14 20 V

Junction Capacitance CJVR = 0 V, f = 1 MHz

VR = 0 V, f < 1 GHz 0.43

0.39 0.7

0.7 pF

Dynamic Resistance RDYN TLP Pulse 0.45 W

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.

5. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform.

ESD7371, SZESD7371 Series

www.onsemi.com

Figure 1. IV Characteristics Figure 2. CV Characteristics

I (A)

V (V)

CAPACITANCE (pF)

Vbias (V)

Figure 3. RF Insertion Loss Figure 4. Capacitance over Frequency

CAPACITANCE (pF)

FREQUENCY

FREQUENCY (Hz)

1E8 1E9 1E10

Figure 5. Positive TLP I−V Curve

TLP CURRENT (A)

VOLTAGE (V) Figure 6. Negative TLP I−V Curve

EQUIVALENT VIEC (kV)

VOLTAGE (V)

1.E−12

1.E−11

1.E−10

1.E−09

1.E−08

1.E−07

1.E−06

1.E−05

1.E−04

1.E−03

0123456789101112 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0123456

−2

−4

−6

−8

−10

−12

−14 2E10 0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5

0 2 4 6 8 101214161820

TLP CURRENT (A)

EQUIVALENT VIEC (kV)

8−16

−14

−12

−10

−8

−6

−4

−2

002468101214161820

EQUIVALENT VIEC (kV)

ESD7371, SZESD7371 Series

www.onsemi.com

IEC 61000−4−2 Spec.

Level Test Volt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 W aveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 7. IEC61000−4−2 Spec

Figure 8. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

Device

Under

Test Oscilloscope

ESD Gun

50 W

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 9. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 10 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels.

Figure 9. Simplified Schematic of a Typical TLP

System

DUT

LS÷

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

ESD7371, SZESD7371 Series

www.onsemi.com

Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

ORDERING INFORMATION

Device Package Shipping†

ESD7371HT1G,

SZESD7371HT1G* SOD−323

(Pb−Free) 3000 / Tape & Reel

ESD7371XV2T1G,

SZESD7371XV2T1G* SOD−523

(Pb−Free) 3000 / Tape & Reel

ESD7371XV2T5G,

SZESD7371XV2T5G* SOD−523

(Pb−Free) 8000 / Tape & Reel

ESD7371P2T5G,

SZESD7371P2T5G* SOD−923

(Pb−Free) 8000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP

Capable.

SOD−323

CASE 477−02

ISSUE H

DATE 13 MAR 2007

SCALE 4:1 NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. LEAD THICKNESS SPECIFIED PER L/F DRAWING

WITH SOLDER PLATING.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

5. DIMENSION L IS MEASURED FROM END OF RADIUS.

NOTE 3

XX = Specific Device Code

M = Date Code

XX M XX M

GENERIC

MARKING DIAGRAM*

NOTE 5

1.60

0.063

0.63

0.025

0.83

0.033

2.85

0.112

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

DIM MIN NOM MAX

MILLIMETERS

A0.80 0.90 1.00

A1 0.00 0.05 0.10

A3 0.15 REF

b0.25 0.32 0.4

C0.089 0.12 0.177

D1.60 1.70 1.80

E1.15 1.25 1.35

0.08

2.30 2.50 2.70

0.031 0.035 0.040

0.000 0.002 0.004

0.006 REF

0.010 0.012 0.016

0.003 0.005 0.007

0.062 0.066 0.070

0.045 0.049 0.053

0.003

0.090 0.098 0.105

MIN NOM MAX

INCHES

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

STYLE 1:

PIN 1. CATHODE (POLARITY BAND)

2. ANODE

STYLE 2:

NO POLARITY

STYLE 1 STYLE 2

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB17533C

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

SOD−323

SOD−523

CASE 502−01

ISSUE E

DATE 28 SEP 2010

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.

MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO-

TRUSIONS, OR GATE BURRS.

XX = Specific Device Code

M Date Code

−X−

−Y−

b2X

0.08 X Y

DIM MIN NOM MAX

MILLIMETERS

D1.10 1.20 1.30

E0.70 0.80 0.90

A0.50 0.60 0.70

b0.25 0.30 0.35

c0.07 0.14 0.20

L0.30 REF

H1.50 1.60 1.70

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

SCALE 4:1

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

GENERIC

MARKING DIAGRAM*

STYLE 1:

PIN 1. CATHODE (POLARITY BAND)

2. ANODE

STYLE 2:

NO POLARITY

STYLE 1 STYLE 2

RECOMMENDED

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.48

0.40

1.80

DIMENSION: MILLIMETERS

PACKAGE

OUTLINE

L2 0.15 0.20 0.25

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON11524D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

SOD−523

SOD−923

CASE 514AB

ISSUE D

DATE 03 SEP 2020

SCALE 8:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH. MINIMUM LEAD THICKNESS IS THE

MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR GATE BURRS.

5. DIMENSION L WILL NOT EXCEED 0.30mm.

GENERIC

MARKING DIAGRAM*

X = Specific Device Code

M = Date Code

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

DIM MIN NOM MAX

MILLIMETERS

A0.34 0.37 0.40

b0.15 0.20 0.25

c0.07 0.12 0.17

D0.75 0.80 0.85

E0.55 0.60 0.65

0.95 1.00 1.05

L0.19 REF

0.013 0.015 0.016

0.006 0.008 0.010

0.003 0.005 0.007

0.030 0.031 0.033

0.022 0.024 0.026

0.037 0.039 0.041

0.007 REF

MIN NOM MAX

INCHES

−Y−

−X−

X M

STYLE 1:

PIN 1. CATHODE (POLARITY BAND)

2. ANODE

STYLE 2:

NO POLARITY

STYLE 1 STYLE 2

X M

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

See Application Note AND8455/D for more mounting details

1.20

0.25

0.36

PACKAGE

OUTLINE

b2X

0.08 XY TOP VIEW

SIDE VIEW

BOTTOM VIEW

L2 0.05 0.10 0.15 0.002 0.004 0.006

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON23284D

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

SOD−923, 1.0X0.6X0.37, MAX HEIGHT 0.40

www.onsemi.com

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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

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