© Semiconductor Components Industries, LLC, 2016
January, 2018 − Rev. 1
1Publication Order Number:
LC717A30UJ/D
LC717A30UJ
Capacitance‐Digital‐Converter
LSI for Electrostatic
Capacitive Touch Sensors
The LC717A30UJ is a high performance, low cost, and highly
usable capacitance converter for electrostatic capacitive touch and
proximity sensors.
8 capacitance-sensing input channels ideal for use in any end
products that needs an array of switches. The LC717A30UJ facilitates
a short system development time through its automatic calibration
function and minimal external components. The detection result
(ON/OFF) for each sensor is read out by the serial interface (I2C or
SPI).
Features
•Differential Capacitive Detection Using Mutual Capacitance
•Operates with Small to Large Capacitance Sensor Input Pads
•Capacitance Detection Down to Femto-Farad Level
•Measurement Time 16 ms for 8 Sensors
•Minimal External Components
•Selectable Interface: I2C or SPI
•Current Consumption: 0.8 mA (VDD = 5.5 V)
•Supply Voltage: 2.6 V to 5.5 V
•AEC−Q100 Qualified and PPAP Capable
Typical Applications
•Automotive: Smart Key, Control Switches, Car Audio, Proximity
•Consumer: Home Appliance, White Goods, Induction Cooking
•Industrial: Security Lock
•Computing: PC Peripherals, Audio Visual Equipment
•Lighting: Remote Control Switches
Figure 1. Application Schematic 1
LC717A30UJ
I2C/SPI
Main
Microcomputer
Cref CrefAdd
Cref
SW1
SW2
SW7
SW8
IFSEL
INOUT
nRST
nCS
SCL/SCK
SDA/SI
SA0/SO
Cdrv
Cin7
Cin6
Cin1
Cin0
CMAdd4
CMAdd0
CdrvBar
VDD or VSS
GPIO
EXTINT
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MARKING DIAGRAM
See detailed ordering and shipping information on page 9 of
this data sheet.
ORDERING INFORMATION
SSOP30 (225 mil)
CASE 565AZ
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
XXXXXXXXXX
YMDDD
LC717A30UJ
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2
8 small capacitance sensors channels and 4-wire SPI interface.
Figure 2. Application Schematic 2
Main
Microcomputer
(open)
(open)
(open)
(open)
SW1 (Small capacitance: e.g. 4 pF)
CdrvBar
GPIO
EXTINT
nCS
SCL/SCK
SDA/SI
SA0/SO
nRST
INTOUT
IFSEL
CMAdd0
CMAdd4
Cin0
Cin1
Cin2
Cin3
Cin0
Cin1
Cin2
Cin3
Cin4
Cin5
Cin6
Cin7
Cdrv
Cref CrefAdd
4 pF
SW2 (Small capacitance: e.g. 4 pF)
SW3 (Small capacitance: e.g. 4 pF)
SW4 (Small capacitance: e.g. 4 pF)
SW5 (Small capacitance: e.g. 4 pF)
SW6 (Small capacitance: e.g. 4 pF)
SW7 (Small capacitance: e.g. 4 pF)
SW8 (Small capacitance: e.g. 4 pF)
LC717A30UJ
8 Large capacitance sensors and I2C interface.
Figure 3. Application Schematic 3
Main
Microcomputer
CdrvBar
GPIO
EXTINT
nCS
SCL/SCK
SDA/SI
SA0/SO
nRST
INTOUT
IFSEL
CMAdd0
CMAdd4
Cin1
Cin3
Cin0
Cin2
Cin4
Cin5
Cin6
Cin7
Cdrv
Cref CrefAdd
LC717A30UJ
VDD
VDD
(open)
20 pF
16 pF
16 pF
16 pF
SW1 (Big capacitance: e.g. 20 pF)
SW2 (Big capacitance: e.g. 20 pF)
SW3 (Big capacitance: e.g. 20 pF)
SW4 (Big capacitance: e.g. 20 pF)
SW5 (Big capacitance: e.g. 20 pF)
SW6 (Big capacitance: e.g. 20 pF)
SW7 (Big capacitance: e.g. 20 pF)
SW8 (Big capacitance: e.g. 20 pF)
LC717A30UJ
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BLOCK DIAGRAM
The LC717A30UJ is a capacitance-digital converter LSI
that can detect capacitance at the femto farad level. It
consists a multiplexer that selects the input channels,
a two-stage amplifier that detects the changes in the
capacitance and outputs analog-amplitude values, an A/D
converter, a system clock, a power-on reset circuit, control
logic and interface, I2C bus or SPI.
Figure 4. Simplified Block Diagram
Cin0
Cin1
Cin2
Cin3
Cin4
Cin5
Cin6
Cin7
CMAdd0
CMAdd4
Cref
CrefAdd
VDD
VSS
Tout0
Tout1
Tout2
Tout3
Tout4
CdrvBar
Cdrv
INTOUT
nRST
nCS
MUX
MUX
A/D
CONVERTER
OSCILLATOR
POWER
ON
RESET
CONTROL LOGIC
I2C/SPI
INTERFACE
1st
AMP
2nd
AMP
−
+
−
+
SCL/SCK
SDA/SI
SA0/SO
IFSEL
LC717A30UJ
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4
PIN ASSIGNMENT
Figure 5. Pin Assignment (Top View)
LC717A30UJ
(SSOP30 (225mil))
115
30 16
Tout4
Tout3
Cin1
Cin0
NC
nRST
nCS
SA0/SO
SDA/SI
SCL/SCK
IFSEL
INOUT
Cdrv
CrefAdd
CdrvBar
VDD
VSS
NC
Cin2
Cin3
Tout0
Tout1
Cin4
Cin5
CMAdd4
CMAdd0
Cin6
Cin7
Tout2
Cref
Table 1. PIN ASSIGNMENT
Pin No. Pin Name I/O Description
1 VDD Power Power supply (+2.6 V to +5.5 V) (Note 1)
2 VSS Power Ground (Notes 1, 2)
3Non Connect −Connect to Ground
27 Cin0 I/O Sensor inputs.
Cin0 to Cin7 are connected to the inverting input of the 1st amplifier through the
multiplexer.
All unused input pins must remain open.
Cdrv and Cin printed circuit board patterns should be close to each other as they are
capacitively coupled.
28 Cin1 I/O
4 Cin2 I/O
5 Cin3 I/O
8 Cin4 I/O
9 Cin5 I/O
12 Cin6 I/O
13 Cin7 I/O
6 Tout0 O Test pin, must remain open
7 Tout1 O Test pin, must remain open
10 CMAdd4 I/O Offset capacitance input pin for the sensor inputs 4 to 7.
When using large sensor pads with high capacitance, additional capacitance is
added between CMAdd4 and CdrvBar. See Figure 3.
Remain open if not in use.
11 CMAdd0 I/O Offset capacitance input pin for the sensor inputs 0 to 3.
When using large sensor pads with high capacitance, additional capacitance is
added between CMAdd4 and CdrvBar. See Figure 3.
Remain open if not in use.
14 Tout2 O Test pin, must remain open
15 Cref I/O Reference capacitance input pins. See Figures 2 and 3.
When using large sensor pads with high capacitance, additional capacitance maybe
added for Cref. See Figure 3.
Remain open if not in use.
17 CrefAdd I/O
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Table 1. PIN ASSIGNMENT (continued)
Pin No. DescriptionI/OPin Name
16 CdrvBar O Capacitance sensors drive signal inversion output.
When using large sensor pads with high capacitance, additional capacitance is
added between CMAdd0 and CMAdd4 and CdrvBar. See Figure 3.
Remain open if not in use.
18 Cdrv O Capacitance sensors drive output.
Cdrv and Cin printed circuit board patterns should be close to each other as they are
capacitively coupled.
19 INTOUT O Interrupt output pin. (Active high)
Remain open if not in use
20 IFSEL I Interface Select.
IFSEL = “Low” (VSS): SPI mode
IFSEL = “High” (VDD): I2C mode
21 SCL/SCK I I2C = SCL clock input
SPI = SCK clock input
22 SDA/SI I/O I2C = SDA data input/output
SPI = SI data input
23 SA0/SO I/O I2C = SA0 slave address selection input
SPI = SO data output
24 nCS I I2C = “High” (VDD)
SPI = nCS chip select inversion input
25 nRST I Reset signal inversion input pin.
nRST = “Low” (VSS), in reset state
Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd, CdrvBar and Tout0 to Tout4 are
“Hi−Z”
26 Non Connect −Connect to Ground
29 Tout3 O Test pin, must remain open
30 Tout4 O Test pin, must remain open
1. For noise de-coupling place a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS. The small-valued capacitor,
at least 0.1 mF, should be mounted near the LSI.
2. When VSS terminal is not grounded, in battery-powered mobile equipment, detection sensitivity may be degraded.
Table 2. PIN FUNCTIONS
Pin No. Pin Name I/O Pin Functions Pin Type
1 VDD Power Power supply (+2.6 V to +5.5 V)
2 VSS Power Ground
27 Cin0 I/O Capacitance sensor input 0
R
AMP
VDD
VSS Buffer
28 Cin1 I/O Capacitance sensor input 1
4 Cin2 I/O Capacitance sensor input 2
5 Cin3 I/O Capacitance sensor input 3
8 Cin4 I/O Capacitance sensor input 4
9 Cin5 I/O Capacitance sensor input 5
12 Cin6 I/O Capacitance sensor input 6
13 Cin7 I/O Capacitance sensor input 7
10 CMAdd4 I/O Additional offset capacitance input pin
for the sensor inputs 4 to 7
11 CMAdd0 I/O Additional offset capacitance input pin
for the sensor inputs 0 to 3
15 Cref I/O Reference capacitance input
17 CrefAdd I/O Additional Reference capacitance input
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Table 2. PIN FUNCTIONS (continued)
Pin No. Pin TypePin FunctionsI/OPin Name
6 Tout0 O Output for tests
VDD
VSS
Buffer
7 Tout1 O Output for tests
14 Tout2 O Output for tests
29 Tout3 O Output for tests
30 Tout4 O Output for tests
16 CdrvBar O Capacitance sensors drive signal inver-
sion output
18 Cdrv O Capacitance sensors drive output
19 INTOUT O Interrupt output VDD
VSS
Buffer
20 IFSEL I Switching control input of the serial data
communication interface
R
VDD
VSS
Schmitt
21 SCL/SCK ISCL clock input (I2C)
ISCK clock input (SPI)
24 nCS I nCS chip select inversion input (SPI)
25 nRST I External reset signal inversion input
22 SDA/SI I/O SDA data input/output (I2C)
R
VDD
VSS
O.D.
Schmitt
ISI data input (SPI)
23 SA0/SO ISA0 slave address selection input (I2C)
R
VDD
VSS
Schmitt
Buffer
OSO data output (SPI)
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ABSOLUTE MAXIMUM RATINGS (VSS = 0 V, TA = +25°C)
Symbol Parameter Value Unit
VDD Supply Voltage Range −0.3 to +6.5 V
VIN Input Voltage Range (Note 3) −0.3 to VDD+0.3 V
VOUT Output Voltage Range (Note 4) −0.3 to VDD+0.3 V
IOP Peak Output Current Range (Notes 4, 5) −8.0 to +8.0 mA
IOA Total Outputs Current Range (Note 6) −40 to +40 mA
Pdmax Maximum Power Dissipation (Note 7) 160 mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Apply to Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd ,SCL/SCK ,SDA/SI ,SA0, nCS, nRST, IFSEL.
4. Apply to Cdrv, CdrvBar, SDA, SO, INTOUT, Tout0 to Tout4.
5. Total value with duty cycle under 25%.
6. Limited to one pin, with duty cycle under 50%.
7. TA = 105°C, Single-layer glass epoxy board (76.1 × 114.3 × 1.6 mm).
RECOMMENDED OPERATING CONDITIONS (VSS = 0 V)
Symbol Parameter Min Max Unit
VDD Operating Supply Voltage Range (Note 8) 2.6 5.5 V
VIH Input High-level Voltage Range (Note 9) 0.8 VDD VDD V
VIL Input Low-level Voltage Range (Note 9) 0 0.2 VDD V
TAAmbient Temperature Range −40 105 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
8. For noise de-coupling place a high-valued capacitor and a low-valued capacitor in parallel between VDD and VSS. The small-valued capacitor,
at least 0.1 mF, should be mounted near the LSI. In addition, it is recommended that the power supply ripple + noise is less than ±40 mV.
9. Apply to SCL/SCK ,SDA/SI ,SA0, nCS, nRST, IFSEL.
ELECTRICAL CHARACTERISTICS
(VDD = 2.6 to 5.5 V, VSS = 0 V, TA = −40 to + 105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 121 kHz.)
Symbol Parameter Condition Min Typ Max Unit
COMMON
VOH1 Output High-level Voltage (Note 10) IO = −1.5 mA, VDD = 2.6 to 3.6 V 0.8 VDD − − V
VOH2 IO = −3.0 mA, VDD = 3.6 to 5.5 V 0.8 VDD − − V
VOL1 Output Low-level Voltage (Note 10) IO = +1.5 mA, VDD = 2.6 to 3.6 V − − 0.2 VDD V
VOL2 IO = +3.0 mA, VDD = 3.6 to 5.5 V − − 0.2 VDD V
VOL3 Tout0 to Tout4 pins Output Low-level
Voltage
IO = +1.5 mA − − 0.2 VDD V
VOL4 SDA pin Output Low-level Voltage IO = +3.0 mA − − 0.4 V
IIH Input High-level Current (Note 11) VI = VDD − − 1.0 mA
IIL Input Low-level Current (Note 11) VI = VSS −1.0 − − mA
IOFF Output Off Leakage Current (Note 12) VI = VDD or VI = VSS −1.0 −1.0 mA
IDD1 Current Consumption Initial setting, Long interval operation,
Sensor pins are open (Note 13),
VDD = 5.5 V
−0.8 2.2 mA
IDD2 Initial setting, Short interval operation,
Sensor pins are open (Note 13),
VDD = 5.5 V
−3.25 6.5 mA
ISTBY Sleep mode (Sleep period)
Sensor pins are open (Note 13)
−0.1 70 mA
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ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.6 to 5.5 V, VSS = 0 V, TA = −40 to + 105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 121 kHz.)
Symbol UnitMaxTypMinConditionParameter
CAPACITANCE SENSOR FUNCTION
CinSENSE Cin Detection Sensitivity Measurements conducted using the
test mode in the LSI,
Minimum gain setting
0.0476 0.068 0.0884 LSB/fF
ICin Sensor Pin Leakage Current (Note 14) VI = VDD or VI = VSS −±25 ±500 nA
fCDRV Cdrv Drive Frequency With 121 kHz setting 84.85 121.21 157.57 kHz
POWER-ON RESET FUNCTION
tNRST nRST Minimum Pulse Width 1.0 − − ms
tPOR Power-on Reset Time − − 20 ms
tPOROP Power-on Reset Operation Condition:
Hold Time
10 − − ms
VPOROP Power-on Reset Operation Condition:
Input Voltage
− − 0.1 V
tVDD Power-on Reset Operation Condition:
Power Supply Rise Rate
0 V to VDD 1.0 − − V/ms
INTERVAL OPERATION TIMING
TLIVAL1 Long Interval Time VDD = 2.6 to 4.5 V, Long interval mode
(Long interval time is set to 101 ms)
35 101 145 ms
TLIVAL2 VDD = 4.5 to 5.5 V, Long interval mode
(Long interval time is set to 101 ms)
40 101 125 ms
TSIVAL1 Short Interval Time VDD = 2.6 to 4.5 V, Short interval mode
(Short interval time is set to 5 ms)
1.7 5 7.3 ms
TSIVAL2 VDD = 4.5 to 5.5 V, Short interval mode
(Short interval time is set to 5 ms)
1.9 5 6.3 ms
I2C COMPATIBLE BUS INTERFACE TIMING
fSCL SCL Clock Frequency SCL − − 400 kHz
tHD; STA START Condition Hold Time SCL, SDA 0.6 − − ms
tLOW SCL Clock Low Period SCL 1.3 − − ms
tHIGH SCL Clock High Period SCL 0.6 − − ms
tSU; STA Repeated START Condition Setup
Time
SCL, SDA 0.6 − − ms
tHD; DAT Data Hold Time SCL, SDA 0−0.9 ms
tSU; DAT Data Setup Time SCL, SDA 0.5 − − ms
tr/tfSDA, SCL Rise/Fall Time SCL, SDA − − 0.3 ms
tSU; STO STOP Condition Setup Time SCL, SDA 0.6 − − ms
tBUF STOP-to-START Bus Release Time SCL, SDA 2.5 − − ms
SPI INTERFACE TIMING
fSCK SCK Clock Frequency SCK − − 5.0 MHz
tLOW SCK Clock Low Time SCK 100 − − ns
tHIGH SCK Clock High Time SCK 100 − − ns
tr/tfInput Signal Rise/Fall Time nCS, SCK, SI − − 300 ns
tSU; NCS nCS Setup Time nCS, SCK 200 − − ns
tSU; SCK SCK Clock Setup Time nCS, SCK 100 − − ns
tSU; SI Data Setup Time SCK, SI 100 − − ns
tHD; SI Data Hold Time SCK, SI 100 − − ns
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ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.6 to 5.5 V, VSS = 0 V, TA = −40 to + 105°C, Unless otherwise specified, the Cdrv drive frequency is fCDRV = 121 kHz.)
Symbol UnitMaxTypMinConditionParameter
SPI INTERFACE TIMING
tHD; NCS nCS Hold Time nCS, SCK 200 − − ns
tHD;SCK SCK Clock Hold Time nCS, SCK 700 − − ns
tCPH nCS Standby Pulse Width nCS 300 − − ns
tCHZ Output High Impedance Time from
nCS
nCS, SO − − 100 ns
tVOutput Data Determination Time SCK, SO − − 100 ns
tHD; SO Output Data Hold Time SCK, SO 0− − ns
tCLZ Output Low Impedance Time from
SCK Clock
SCK, SO 100 − − ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.Apply to Cdrv, CdrvBar, SO, INTOUT.
11. Apply to SCL/SCK, SDA/SI, SA0, nCS, nRST, IFSEL.
12.Apply to Cdrv, CdrvBar, SDA, SO.
13.Sensor pins (Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd) are open condition.
14.Apply to Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd.
Table 3. ORDERING INFORMATION
Device Package Shipping (Qty / Packing)†
LC717A30UJ−AH SSOP30 (225 mil)
(Pb-Free / Halogen Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifi-
cations Brochure, BRD8011/D.
LC717A30UJ
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10
FUNCTIONAL DESCRIPTION
Power-on Reset (POR)
When power is turned on, power-on reset is enabled, it is
released after power-on reset time, tPOR. Power-on reset
operation condition; Power supply rise rate tVDD must be at
least 1.0 V/ms.
Since INTOUT pin changes from “High” to “Low” at the
same time as reset release, it is possible to verify the timing
of release of reset externally. During power-on reset, Cin0
to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd, and CdrvBar
are unknown.
Figure 6. Power-on Sequence by the Power-on Reset
tPOR
tVDD VPOROP
Unknown
VALID
tPOROP
Unknown
Unknown
Unknown Reset Release
tPOR
VALID
ReleaseReset
VDD
POR
(LSI Internal
Signal)
INTOUT
Cin0 to 7,
CMAdd0,
CMAdd4,
Cref, CrefAdd,
CdrvBar
0%
100%
External Reset (nRST)
Reset State nRST = “Low”. Pins Cin0 to Cin7, CMAdd0,
CMAdd4, Cref, CrefAdd and CdrvBar, are “Hi-Z” during
reset state. The reset state is released after tPOR.
Since INTOUT pin changes from “High” to “Low” at the
same time as the released of reset, it is possible to verify the
timing of release of reset externally.
Figure 7. Power-on Sequence by the External Reset
Reset
VDD
nRST
POR
(LSI Internal signal)
INTOUT
Cin0 to 7,
CMAdd0,
CMAdd4,
Cref, CrefAdd,
CdrvBar
Reset ReleaseRelease
100%
0%
Reset
tNRST
Hi-Z
VALID
VALID
Reset
tNRST
Hi-Z
tPOR tPOR
Unknown Unknown
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11
I2C Data Timing
Figure 8. I2C Data Timing
SDA
SCL
tHD;STA
tLOW
tHIGH
tr
condition
tf
tHD;DAT tSU;DAT
80%
tSU;STA tHD;STA
tSU;STO
tBUF
Repeated START
condition
START condition
STOP condition
START
20%
80%
20%
I2C Communication Formats
Write Format
When using the Write format of I2C the data can be written into sequentially incremented addresses.
Figure 9. I2C Write Format
START Slave Address Write=L Register Address (N)ACK ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave Slave Slave Slave
Read Format
When using the Read format of I2C the data can be read from sequentially incremented addresses.
Figure 10. I2C Read Format
START Slave Address Write=L Register Address (N)ACK ACK
Data read from Register Address (N)ACKRESTART Slave Address Read=H ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Slave
Slave
Master Master Master
I2C Slave Address
SA0 pin is used to select the slave address
Table 4. I2C SLAVE ADDRESS
SA0 Pin Input 7 bit Slave Address Binary Notation 8 bit Slave Address
Low 0x16 00101100b (Write) 0x2C
00101101b (Read) 0x2D
High 0x17 00101110b (Write) 0x2E
00101111b (Read) 0x2F
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12
SPI Data Timing (Mode 0/Mode 3)
Figure 11. SPI Data Timing
nCS
SCK
SI
SO
tSU;SI
VALID
Hi−Z
tr
tHD;SI
tSU;SCK tHIGH tLOW tf
tCPH
tHD;NCS tHD;SCK
tCLZ tHD;SO tCHZ
VALID
tV
50%
50%
50% Hi−Z
tSU;NCS 50%
80%
20%
SPI Write Format (Example of Mode 0)
When using the SPI Write format the data can be written into sequentially incremented addresses with preserving nCS = “L”.
Figure 12. SPI Write Format
nCS
SCK
SI
SO
76543210
Hi-Z
Register Address(N) Data written to Register Address(N) Data written to Register Address(N+1)
Write=L
7654321076543210
SPI Read Format
When using the SPI Read format the data can be read from sequentially incremented addresses with preserving nCS = “L”.
Figure 13. SPI Read Format
7
Read=H
76543210
Hi-Z
nCS
SCK
SI
SO 7654321076543210
Register Address(N)
Data read from Register Address(N) Data read from Register Address(N+1)
I2C Bus is a trademark of Philips Corporation.
SSOP30 (225 mil)
CASE 565AZ
ISSUE A
DATE 25 OCT 2013
SOLDERING FOOTPRINT*
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
(Unit: mm)
5.80
0.32
1.00
0.50
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXXXXXXX
YMDDD
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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