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© 1990, 1993, 1994
MOS INTEGRATED CIRCUIT
µ
PD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
DATA SHEET
Document No. M10770EJCV0DS00 (12th edition)
Date Published June 2000 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
Description
The
µ
PD43256B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available. And A and B versions are wide voltage operations.
The
µ
PD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I) (8 x 13.4 mm).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Low VCC data retention: 2.0 V (MIN.)
• /OE input for easy application
Part number Access ti m e Operating suppl y Operating ambient Supply c urrent
ns (MAX .) voltage temperature At operating At standby At data retention
V °C mA (MAX.)
µ
A (MAX.)
µ
A (MAX.) Note1
µ
PD43256B-xxL 70, 85 4.5 to 5.5 0 to 70 45 50 3
µ
PD43256B-xxLL 15 2
µ
PD43256B-Axx 85, 100 Note2, 120 Note2 3.0 to 5.5
µ
PD43256B-Bxx Note2 100, 120, 150 2.7 to 5.5
Notes 1. TA ≤ 40 °C, VCC = 3.0 V
2. Access time: 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
Version X and P
This Data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in the
fifth character position in a lot number signifies version X, letter P, version P.
D43256B
Lot number
JAPAN
2
µ
PD43256B
Data Sheet M10770EJCV0DS00
Ordering Information
Part number Package Access ti m e Operating suppl y Operating ambient Remark
ns (MAX .) voltage temperature
V°C
µ
PD43256BCZ-70L 28-PIN PLA STIC DIP 70 4.5 to 5.5 0 to 70 L version
µ
PD43256BCZ-85L (15.24 mm (600)) 85
µ
PD43256BCZ-70LL 70 LL version
µ
PD43256BCZ-85LL 85
µ
PD43256BGU-70L 28-PIN PLA STIC SOP 70 L version
µ
PD43256BGU-85L (11.43 mm (450)) 85
µ
PD43256BGU-70LL 70 LL version
µ
PD43256BGU-85LL 85
µ
PD43256BGU-A85 85 3.0 to 5.5 A versi on
µ
PD43256BGU-A10 100
µ
PD43256BGU-A12 120
µ
PD43256BGU-B10 100 2.7 to 5.5 B versi on
µ
PD43256BGU-B12 120
µ
PD43256BGW-70LL-9JL 28-PIN PLA STIC TSOP (I) 70 4.5 to 5.5 LL version
µ
PD43256BGW-85LL-9JL (8x13.4) (Normal bent ) 85
µ
PD43256BGW-A85-9J L 85 3.0 to 5.5 A versi on
µ
PD43256BGW-A10-9JL 100
µ
PD43256BGW-A12-9JL 120
µ
PD43256BGW-B10-9J L 100 2.7 to 5.5 B version
µ
PD43256BGW-B12-9JL 120
µ
PD43256BGW-B15-9JL 150
µ
PD43256BGW-70LL-9KL 28-PIN PLA STIC TSOP (I) 70 4.5 to 5.5 LL version
µ
PD43256BGW-85LL-9KL (8x13.4) (Reverse bent) 85
µ
PD43256BGW-A85-9K L 85 3.0 to 5.5 A versi on
µ
PD43256BGW-A10-9KL 100
µ
PD43256BGW-A12-9KL 120
µ
PD43256BGW-B10-9K L 100 2.7 to 5.5 B version
µ
PD43256BGW-B12-9KL 120
µ
PD43256BGW-B15-9KL 150
3
µ
PD43256B
Data Sheet M10770EJCV0DS00
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-PIN PLASTIC DIP (15.24 mm (600))
[
µ
µµ
µ
PD43256BCZ-xxL ]
[
µ
µµ
µ
PD43256BCZ-xxLL ]
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
V
CC
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0 - A14 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
4
µ
PD43256B
Data Sheet M10770EJCV0DS00
28-PIN PLASTIC SOP (11.43 mm (450))
[
µ
µµ
µ
PD43256BGU-xxL ]
[
µ
µµ
µ
PD43256BGU-xxLL ]
[
µ
µµ
µ
PD43256BGU-Axx ]
[
µ
µµ
µ
PD43256BGU-Bxx ]
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
V
CC
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0 - A14 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
5
µ
PD43256B
Data Sheet M10770EJCV0DS00
28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent)
[
µ
µµ
µ
PD43256BGW-xxLL-9JL ]
[
µ
µµ
µ
PD43256BGW-Axx-9JL ]
[
µ
µµ
µ
PD43256BGW-Bxx-9JL ]
/OE
A11
A9
A8
A13
/WE
V
CC
A14
A12
A7
A6
A5
A4
A3
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent)
[
µ
µµ
µ
PD43256BGW-xxLL-9KL ]
[
µ
µµ
µ
PD43256BGW-Axx-9KL ]
[
µ
µµ
µ
PD43256BGW-Bxx-9KL ]
/OE
A11
A9
A8
A13
/WE
V
CC
A14
A12
A7
A6
A5
A4
A3
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0 - A14 : Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS : Chip Select
/WE : Write Enable
/OE : Output Enable
VCC : Power supply
GND : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
6
µ
PD43256B
Data Sheet M10770EJCV0DS00
Block Diagram
Address buffer
Memory cell array
262,144 bits
Input data
controller
A0
A14
I/O8
Sense amplifier /
Switching circuit
Column decoder
/WE
I/O1
V
CC
GND
/CS
/OE
Address
buffer Row
decoder
Output data
controller
Truth Table
/CS /OE /WE Mode I/O Supply c urrent
H××Not selected High impedance ISB
L H H Output di sable ICCA
L×LWrite D
IN
L L H Read DOUT
Remark × : VIH or VIL
7
µ
PD43256B
Data Sheet M10770EJCV0DS00
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply v ol tage VCC –0.5 Note to +7.0 V
Input / Output vol t age VT–0.5 Note to VCC + 0.5 V
Operating ambient temperature TA0 to 70 °C
Storage tem perature Tstg –55 to +125 °C
Note –3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition
µ
PD43256B-xxL
µ
PD43256B-Axx
µ
PD43256B-Bxx Unit
µ
PD43256B-xxLL
MIN. MAX. MIN. MAX. MIN. MAX.
Supply v ol tage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V
High level i nput voltage VIH 2.2 VCC+0.5 2.2 VCC+0.5 2.2 VCC+0.5 V
Low level input voltage VIL –0.3 Note +0.8 –0. 3 Note +0.5 –0.3 Note +0.5 V
Operating ambient temperature TA070070070
°C
Note –3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Sy m bol Test c ondi t i ons MIN. TYP. MAX. Unit
Input capacitanc e CIN VIN = 0 V 5 pF
Input / Output capac i tance CI/O VI/O = 0 V 8 pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
8
µ
PD43256B
Data Sheet M10770EJCV0DS00
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter Symbol Test c ondi t i on
µ
PD43256B-xxL
µ
PD43256B-xxLL Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Input leak age current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0
µ
A
I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0
µ
A
/CS = VIH or /WE = VIL
Operating suppl y current ICCA1 /CS = VIL, Minimum cycle time, II/O = 0 mA 45 45 mA
ICCA2 /CS = VIL, II/O = 0 mA 10 10
ICCA3 /CS ≤ 0.2 V, Cy c l e = 1 MHz, 10 10
II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
Standby supply c urrent ISB /CS = VIH 33mA
ISB1 /CS ≥ VCC − 0.2 V 1.0 50 0.5 15
µ
A
High level output voltage VOH1 IOH = –1.0 mA 2.4 2.4 V
VOH2 IOH = –0.1 mA VCC–0.5 VCC–0.5
Low level out put voltage VOL IOL = 2.1 mA 0.4 0.4 V
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
9
µ
PD43256B
Data Sheet M10770EJCV0DS00
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter Symbol Test condi tion
µ
PD43256B-Axx
µ
PD43256B-Bxx Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Input leak age current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0
µ
A
I/O leakage current ILO VI/O = 0 V to VCC, /OE = VIH or –1.0 +1.0 –1.0 +1.0
µ
A
/CS = VIH or /WE = VIL
Operating suppl y current ICCA1 /CS = VIL,
µ
PD43256B-Axx 45 – mA
Minimum cycle time,
µ
PD43256B-Bxx – 45
II/O = 0 mA VCC ≤ 3.3 V – 20
ICCA2 /CS = VIL, II/O = 0 mA 10 10
VCC ≤ 3.3 V – 5
ICCA3 /CS ≤ 0.2 V, Cy c l e = 1 MHz, II/O = 0 mA , 10 10
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V – 5
Standby supply c urrent ISB /CS = VIH 33mA
VCC ≤ 3.3 V – 2
ISB1 /CS ≥ VCC − 0.2 V 0.5 15 0.5 15
µ
A
VCC ≤ 3.3 V – 0.5 10
High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4. 5 V 2.4 2.4 V
IOH = –0.5 mA, VCC < 4. 5 V 2.4 2.4
VOH2 IOH = –0.02 mA VCC–0.1 VCC–0.1
Low level out put voltage VOL IOL = 2.1 mA, V CC ≥ 4.5 V 0.4 0.4 V
IOL = 1.0 mA, VCC < 4. 5 V 0.4 0.4
VOL1 IOL = 0.02 mA 0.1 0.1
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
10
µ
PD43256B
Data Sheet M10770EJCV0DS00
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
µ
µµ
µ
PD43256B-70L,
µ
µµ
µ
PD43256B-85L,
µ
µµ
µ
PD43256B-70LL,
µ
µµ
µ
PD43256B-85LL ]
Input Waveform (Rise and Fall Time ≤
≤≤
≤ 5 ns)
Test points
0.8 V
2.2 V
1.5 V 1.5 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1 Figure 2
(tAA, tACS, tOE, tOH)(t
CHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
I/O (Output)
1.8 kΩ
5 pF
C
L
990 Ω
+5 V
I/O (Output)
1.8 kΩ
100 pF
C
L
990 Ω
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[
µ
µµ
µ
PD43256B-A85,
µ
µµ
µ
PD43256B-A10,
µ
µµ
µ
PD43256B-A12,
µ
µµ
µ
PD43256B-B10,
µ
µµ
µ
PD43256B-B12,
µ
µµ
µ
PD43256B-B15 ]
Input Waveform (Rise and Fall Time ≤
≤≤
≤ 5 ns)
Test points
0.5 V
2.2 V
1.5 V 1.5 V
Output Waveform
Test points1.5 V 1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
tAA, tACS, tOE, tOH tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW
1TTL + 100 pF 1TTL + 5 pF
11
µ
PD43256B
Data Sheet M10770EJCV0DS00
Read Cycle (1/2)
Parameter Symbol VCC ≥ 4.5 V Unit Condi tion
µ
PD43256B-70
µ
PD43256B-85
µ
PD43256B-A85/A10/A12
µ
PD43256B-B10/B12/B15
MIN. MAX. MIN. MAX.
Read cycle time tRC 70 85 ns
Address access time tAA 70 85 ns Note
/CS access time tACS 70 85 ns
/OE access time tOE 35 40 ns
Output hold f rom address change tOH 10 10 ns
/CS to out put in low impedance tCLZ 10 10 ns
/OE to output in low i m pedance tOLZ 55ns
/CS to out put in high impedance tCHZ 30 30 ns
/OE to output in high i m pedance tOHZ 30 30 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Con-
µ
PD43256B
-A85
µ
PD43256B
-A10
µ
PD43256B
-A12
µ
PD43256B
-B10
µ
PD43256B
-B12
µ
PD43256B
-B15 dition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC 85 100 120 100 120 150 ns
Address access
time tAA 85 100 120 100 120 150 ns Note
/CS access time tACS 85 100 120 100 120 150 ns
/OE access time tOE 50 60 60 60 60 70 ns
Output hold f rom
address c hange tOH 10 10 10 10 10 10 ns
/CS to out put in
low impedanc e tCLZ 10 10 10 10 10 10 ns
/OE to output in
low impedanc e tOLZ 555555ns
/CS to out put in
high impedance tCHZ 35 35 40 35 40 50 ns
/OE to output in
high impedance tOHZ 35 35 40 35 40 50 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
12
µ
PD43256B
Data Sheet M10770EJCV0DS00
Read Cycle Timing Chart
t
OHZ
t
RC
t
OH
t
CHZ
t
OLZ
t
OE
t
CLZ
t
ACS
t
AA
High impedance Data out
/OE (Input)
/CS (Input)
Address (Input)
I/O (Output)
Remark In read cycle, /WE should be fixed to high level.
13
µ
PD43256B
Data Sheet M10770EJCV0DS00
Write Cycle (1/2)
Parameter Symbol VCC ≥ 4.5 V Unit Condi tion
µ
PD43256B-70
µ
PD43256B-85
µ
PD43256B-A85/A10/A12
µ
PD43256B-B10/B12/B15
MIN. MAX. MIN. MAX.
Write cycle time tWC 70 85 ns
/CS to end of wri te tCW 50 70 ns
Address valid to end of write tAW 50 70 ns
Write puls e wi dt h tWP 55 60 ns
Data valid to end of write tDW 30 35 ns
Data hold ti m e tDH 00ns
Address setup ti m e tAS 00ns
Write recovery t i m e t WR 00ns
/WE to output in high i m pedance tWHZ 30 30 ns Note
Output active f rom end of wri te tOW 10 10 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
Parameter Symbol VCC ≥ 3.0 V VCC ≥ 2.7 V Unit Con-
µ
PD43256B
-A85
µ
PD43256B
-A10
µ
PD43256B
-A12
µ
PD43256B
-B10
µ
PD43256B
-B12
µ
PD43256B
-B15 dition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC 85 100 120 100 120 150 ns
/CS to end of wri te tCW 70 70 90 70 90 100 ns
Address valid to
end of write tAW 70 70 90 70 90 100 ns
Write puls e wi dt h tWP 60 60 80 60 80 90 ns
Data va lid to e nd
of write tDW 60 60 70 60 70 80 ns
Data hold ti m e tDH 000000
ns
Address setup tAS 000000ns
Write recovery tWR 000000ns
/WE to output in
high impedance tWHZ 30 35 40 35 40 50 ns Note
Output active
from end of wri t e tOW 10 10 10 10 10 10 ns
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
14
µ
PD43256B
Data Sheet M10770EJCV0DS00
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out High
impe-
dance
High
impe-
dance
Data in Indefinite data out
Address (Input)
/CS (Input)
I/O (Input / Output)
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O
pins will remain high impedance state.
•
15
µ
PD43256B
Data Sheet M10770EJCV0DS00
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
DW
t
DH
Data in
High impedance
Address (Input)
/CS (Input)
I/O (Input) High
impedance
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
•
16
µ
PD43256B
Data Sheet M10770EJCV0DS00
Low VCC Data Retention Characteristics (TA = 0 to 70 °
°°
°C)
Parameter Symbol Test Conditi on
µ
PD43256B-xxL
µ
PD43256B-xxLL Unit
µ
PD43256B-Axx
µ
PD43256B-Bxx
MIN. TYP. MAX. MIN. TYP. MAX.
Data retenti on supply v ol tage VCCDR /CS ≥ VCC − 0.2 V 2.0 5.5 2.0 5.5 V
Data retenti on supply c urrent ICCDR VCC = 3.0 V, / CS ≥ VCC − 0. 2 V 0.5 20 Note1 0.5 7 Note2
µ
A
Chip deselec tion
to data retention mode tCDR 00ns
Operation recovery tim e tR55ms
Notes 1. 3
µ
A (TA ≤ 40 °C)
2. 2
µ
A (TA ≤ 40 °C), 1
µ
A (TA ≤ 25 °C)
Data Retention Timing Chart
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CS
/CS ≥ V
CC
– 0.2 V
GND
4.5 V
Note
t
CDR
Data retention mode t
R
Note A version : 3.0 V, B version : 2.7 V
Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
17
µ
PD43256B
Data Sheet M10770EJCV0DS00
Package Drawings
ITEM MILLIMETERS
A
B
C
F
G
H
I
J
K
38.10 MAX.
2.54 (T.P.)
3.6±0.3
0.51 MIN.
4.31 MAX.
2.54 MAX.
L
0.25
15.24 (T.P.)
5.72 MAX.
13.2
N
1.2 MIN.
P28C-100-600A1-2
D 0.50±0.10
M 0.25+0.10
−0.05
R 0 - 15°
NOTES
Each lead centerline is located within 0.25 mm
of its true position (T.P.) at maximum material condition.
Item "K" to center of leads when formed parallel.
1.
2.
28
1
15
14
A
MR
K
L
B
J
G
I
C
F
D
M
N
28-PIN PLASTIC DIP (15.24 mm (600))
H
18
µ
PD43256B
Data Sheet M10770EJCV0DS00
28 15
114
S
−3°
ITEM MILLIMETERS
A
B
C
E
F
G
H
J
18.0
1.27 (T.P.)
2.95 MAX.
2.55±0.1
11.8±0.3
1.27 MAX.
0.12
1.7±0.2
M
0.2±0.1
N
P28GU-50-450A-4
P3°+7°
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
D 0.42+0.08
−0.07
K 0.22±0.05
+0.6
−0.05
L 0.7±0.2
0.10
I 8.4±0.1
28-PIN PLASTIC SOP (11.43 mm (450))
M
F
E
DM
C
G
B
L
J
K
P
detail of lead end
A
SN
I
H
•
19
µ
PD43256B
Data Sheet M10770EJCV0DS00
+7°
−3°
28-PIN PLASTIC TSOP(I) (8x13.4)
ITEM MILLIMETERS
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
P28GW-55-9JL-2
M 0.08
N 0.10
H 12.4±0.2
I 11.8±0.1
J 0.8±0.2
S 1.2 MAX.
A 8.0±0.1
B 0.6 MAX.
C 0.55 (T.P.)
G 1.0
K 0.145
L 0.5±0.1
P 13.4±0.2
Q 0.1±0.05
R3°
D 0.22+0.08
−0.07
M
detail of lead end
QR
G
B
C
DM
L
K
+0.025
−0.015
S
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
1
14
28
15
SN
S
A
J
P
I
H
20
µ
PD43256B
Data Sheet M10770EJCV0DS00
28-PIN PLASTIC TSOP(I) (8x13.4)
ITEM MILLIMETERS
NOTE
P28GW-55-9KL-2
M 0.08
N 0.10
H 12.4±0.2
I 11.8±0.1
J 0.8±0.2
S 1.2 MAX.
A 8.0±0.1
B 0.6 MAX.
C 0.55 (T.P.)
G 1.0
K 0.145
L 0.5±0.1
P 13.4±0.2
Q 0.1±0.05
R3°+7°
−3°
D 0.22+0.08
−0.07
detail of lead end
R
Q
S
B
C
D
+0.025
−0.015
M
MN
G
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
1
14
28
15
S
S
A
J
L
K
P
I
H
21
µ
PD43256B
Data Sheet M10770EJCV0DS00
Recommended Soldering Conditions
The following conditions (See table below) must be met when soldering
µ
PD43256B. For more details, refer to our
document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
Types of Surface Mount Device
µ
PD43256BGU-xxL : 28-PIN PLASTIC SOP (11.43 mm (450))
µ
PD43256BGU-xxLL : 28-PIN PLASTIC SOP (11.43 mm (450))
µ
PD43256BGU-Axx : 28-PIN PLASTIC SOP (11.43 mm (450))
µ
PD43256BGU-Bxx : 28-PIN PLASTIC SOP (11.43 mm (450))
µ
PD43256BGW-xxLL-9JL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent)
µ
PD43256BGW-xxLL-9KL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent)
µ
PD43256BGW-Axx-9JL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent)
µ
PD43256BGW-Axx-9KL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent)
µ
PD43256BGW-Bxx-9JL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Normal bent)
µ
PD43256BGW-Bxx-9KL : 28-PIN PLASTIC TSOP (I) (8x13.4) (Reverse bent)
Please consult with our sales offices.
Types of Through Hole Mount Device
µ
PD43256BCZ-xxL : 28-PIN PLASTIC DIP (15.24 mm (600))
µ
PD43256BCZ-xxLL : 28-PIN PLASTIC DIP (15.24 mm (600))
Soldering proc es s Soldering c ondi t i ons
Wave solderi ng (onl y to leads) S ol der temperature : 260 °C or below,
Flow time : 10 seconds or bel ow
Partial heating method Terminal tem perature : 300 °C or below,
Time : 3 s econds or below (Per one l ead)
Caution Do not jet molten solder on the surface of package.
22
µ
PD43256B
Data Sheet M10770EJCV0DS00
[ MEMO ]
23
µ
PD43256B
Data Sheet M10770EJCV0DS00
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
PD43256B
M8E 00. 4
The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
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NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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