CLC401AJE-TRNOPB - National Semiconductor

CLC401

Fast Settling, Wideband High Gain Monolithic Op Amp

General Description

The CLC401 is a wideband, fast settling op amp designed

for applications requiring gains greater than ±7. Constructed

using an advanced complementary bipolar process and a

proprietary design, the CLC401 features dynamic perfor-

mance far beyond that of typical high speed monolithic op

amps. For example, at a gain of +20, the −3dB bandwidth is

150MHz and the rise/fall time is only 2.5ns.

The wide bandwidth and linear phase (0.2˚ deviation from

linear at 50MHz) and a very flat gain response makes the

CLC401 ideal for many digital communication system appli-

cations. For example, demodulators need both DC coupling

and high frequency amplification-requirements that are ordi-

narily difficult to meet.

The very fast 10ns settling to 0.1% and the ability to drive

capacitive loads lend themselves well to flash A/D applica-

tions. Systems employing D/A converters also benefit from

the settling time and also by the fact that current-to-voltage

transimpedance amplification is easily accomplished.

The CLC401 provides a quick, effective design solution. Its

stable operation over the entire ±7to±

50 gain range pre-

cludes the need for external compensation. And, unlike

many other high speed-op amps, the CLC401’s power dis-

sipation of 150mW is compatible with designs which must

limit total power dissipation or power supply requirements.

The CLC401 is based on National’s proprietary op amp

topology that uses current feedback instead of the usual

voltage feedback. This unique design has many advantages

over conventional designs (such as settling time that is

relatively independent of gain), yet it is used in basically the

same way (see the gain equations in

Figure 1

and

Figure 2

However, an understanding of the topology will aid in achiev-

ing the best performance. The discussion below will proceed

for the non-inverting gain configuration with the inverting

mode analysis being very similar.

Enhanced Solutions (Military/Aerospace)

SMD Number: 5962-89973

Space level versions also available.

For more information, visit http://www.national.com/mil

Features

n−3dB bandwidth of 150MHz

n0.1% settling in 10ns

nLow power, 150mW

nOverload and short circuit protected

nStable without compensation

nRecommended gain range, ±7to±

Applications

nFlash, precision A/D conversion

nPhotodiode, CCD preamps

nIF processors

nHigh speed modems, radios

nLine drivers

nDC coupled log amplifiers

nHigh speed communications

Pulse Response

01274418

Connection Diagram

01274417

Pinout

DIP & SOIC

June 2001

CLC401 Fast Settling, Wideband High Gain Monolithic Op Amp

01274401

Non-Inverting Frequency Response

Ordering Information

Package Temperature Range

Industrial Part Number Package

Marking NSC

Drawing

8-pin plastic DIP −40˚C to +85˚C CLC401AJP CLC401AJP N08E

8-pin plastic SOIC −40˚C to +85˚C CLC401AJE CLC401AJE M08A

CLC401

www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)±7V

OUT

Output is short circuit protected to

ground, but maximum reliability will

be maintained if I

OUT

does not

exceed... 60mA

Common Mode Input Voltage ±V

Differential Input Voltage 5V

Junction Temperature Range +150˚C

Operating Temperature Range −40˚C to +85˚C

Storage Temperature Range −65˚C to +150˚C

Lead Solder Duration (+300˚C) 10 sec

Operating Ratings

Thermal Resistance

Package (θ

)(θ

)

MDIP 70˚C/W 125˚C/W

SOIC 65˚C/W 145˚C/W

Electrical Characteristics

= +20, V

=±5V, R

= 100Ω,R

=1.5kΩ; unless specified).

Symbol Parameter Conditions Typ Max/Min Ratings

(Note 2) Units

Ambient Temperature CLC401AJ +25˚C −40˚C +25˚C +85˚C

Frequency Domain Response

SSBW −3dB Bandwidth V

OUT

<2V

150 >100 >100 >70 MHz

LSBW V

OUTt

<5V

100 >65 >65 >55 MHz

Gain Flatness V

OUT

<2V

GFPL Peaking <25MHz 0 <0.1 <0.1 <0.1 dB

GFPH Peaking >25MHz 0 <0.2 <0.2 <0.2 dB

GFR Rolloff <50MHz 0.2 <1.0 <1.0 <1.3 dB

LPD Linear Phase Deviation DC to 50MHz 0.2 <1.0 <1.0 <1.5 deg

Time Domain Response

TRS Rise and Fall Time 2V Step 2.5 <3.5 <3.5 <5.0 ns

TRL 5V Step 5 <7.0 <7.0 <8.0 ns

TS Settling Time to ±0.1% 2V Step 10 <15 <15 <15 ns

OS Overshoot 2V Step 0 <10 <10 <10 %

SR Slew Rate 1200 >800 >800 >700 V/µs

Distortion And Noise Response

HD2 2nd Harmonic Distortion 2V

, 20MHz −45 <−35 <−35 <−35 dBc

HD3 3rd Harmonic Distortion 2V

, 20MHz −60 <−50 <−50 <−45 dBc

Equivalent Input Noise

SNF Noise Floor >1MHz −158 <−155 <−155 <−154 dBm

(1Hz)

INV Integrated Noise 1MHz to 150MHz 35 <50 <50 <55 µV

Static, DC Performance

VIO Input Offset Voltage (Note 3) 3 ±10.0 ±6.0 ±11.0 mV

DVIO Average Temperature Coefficient 20 ±50 – ±50 µV/˚C

IBN Input Bias Current (Note 3) Non-Inverting 10 ±36 ±20 ±20 µA

DIBN Average Temperature Coefficient 100 ±200 – ±100 nA/˚C

IBI Input Bias Current (Note 3) Inverting 10 46 30 40 µA

DIBI Average Temperature Coefficient 100 ±200 – ±100 nA/˚C

PSRR Power Supply Rejection Ratio 55 50 50 50 dB

CMRR Common Mode Rejection Ratio 55 50 50 50 dB

ICC Supply Current (Note 3) No Load 15 21 21 21 mA

Miscellaneous Performance

RIN Non-Inverting Input Resistance 200 >50 >100 >100 kΩ

CIN Capacitance 0.5 <2.5 <2.5 <2.5 pF

CLC401

www.national.com3

Electrical Characteristics (Continued)

= +20, V

=±5V, R

= 100Ω,R

=1.5kΩ; unless specified).

Symbol Parameter Conditions Typ Max/Min Ratings

(Note 2) Units

RO Output Impedance at DC 0.2 <0.3 <0.3 <0.3 Ω

VO Output Voltage Range No Load 3.5 >3.0 >3.2 >3.2 V

CMIR Common Mode Input Range For Rated Performance 2.8 >2.0 >2.5 >2.5 V

IO Output Current 60 >35 >50 >50 mA

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: AJ-level: spec. is 100% tested at +25˚C.

CLC401

www.national.com 4

Typical Performance Characteristics (T

= 25˚, A

= +20, V

=±5V, R

= 100Ω: Unless Speci-

fied).

Non-Inverting Frequency Response Inverting Frequency Response

01274401 01274402

Frequency Response for Various R

s Open-Loop Transimpedance Gain, Z(s)

01274403

01274404

2nd and 3rd Harmonic Distortion 2-Tone,3rd Order, Intermodulation Intercept

01274405 01274406

CLC401

www.national.com5

Typical Performance Characteristics (T

= 25˚, A

= +20, V

=±5V, R

= 100Ω: Unless

Specified). (Continued)

Equivalent Input Noise CMRR and PSRR

01274407 01274408

Pulse Response Settling Time

01274418 01274419

Long-Term Settling Time Settling Time vs. Load Capacitance

01274420

01274409

CLC401

www.national.com 6

Typical Performance Characteristics (T

= 25˚, A

= +20, V

=±5V, R

= 100Ω: Unless

Specified). (Continued)

Recommended R

vs. Load Capacitance Low Gain & Transimpedance Applications

01274413

01274421

Frequency Response, A

= −1, R

= 2.25kΩ

01274414

CLC401

www.national.com7

Application Division

Understanding the Loop Gain

Referring to the equivalent circuit of

Figure 3

, any current

flowing in the inverting input is amplified to a voltage at the

output through the transimpedance gain shown on the plots

on page 3. This Z(s) is analogous to the open-loop gain of a

voltage feedback amplifier.

Developing the non-inverting frequency response for the

topology of

Figure 3

yields:

Equation 1

where LG is the loop gain defined by,

Equation 2

Equation 1 has a form identical to that for a voltage feedback

amplifier with the differences occurring in the LG expression.

For an idealized treatment, set Z

= 0 which results in a very

simple LG = Z(s)/R

(Derivation of the transfer function for

the case where Z

= 0 is given in Application NoteAN300-1).

Using the Z(s) (open-loop transimpedance gain) plot shown

on the previous page and dividing by the recommended R

1.5kΩ, yields a large loop gain at DC. As a result, Equation

1 shows that the closed-loop gain at DC is very close to

(1+R

At higher frequencies, the roll-off of Z(s) determines the

closed-loop frequency response which, ideally, is dependent

only on R

.The specifications reported on the previous

pages are therefore valid only for the specified R =

1.5kΩ.Increasing R from 1.5kΩwill decrease the loop gain

and band width, while decreasing it will increase the loop

gain possibly leading to inadequate phase margin and

closed-loop peaking. Conversely, fixing R

will hold the fre-

quency response constant while the closed-loop gain can be

adjusted using R

The CLC401 departs from this idealized analysis to the

extent that the inverting input impedance is finite. With the

low quiescent power of the CLC401, Z ≅50Ωleading to drop

in loop gain and bandwidth at high gain settlings, as given by

Equation 2. The second term is Equation 2 accounts for the

division in feedback current that occurs between Z

and

at the inverting node of the CLC400. This decrease in

bandwidth can be circumvented as described in “Increasing

Bandwidth at High Gains.”

DC Accuracy and Noise

Since the two inputs for the CLC401 are quite dissimilar, the

noise and offset error performance differs somewhat from

that of a standard differential input amplifier. Specifically, the

inverting input current noise is much larger than the

non-inverting current noise. Also the two input bias currents

are physically unrelated rendering bias current cancellation

through matching of the inverting and non-inverting pin re-

sistors ineffective.

In Equation 3, the output offset is the algebraic sum of the

equivalent input voltage and current sources that influence

DC operation. Output noise is determined similarly except

that a root-sum-of-squares replaces the algebraic sum. R

the non-inverting pin resistance.

Equation 3

Output Offset V

=±IBNxR

(1+ R

)±

VIO (1+ R

)±IBIxR

An important observation is that for fixed R

, offsets as

referred to the input improve as the gain is increased (divide

all terms by 1+R

). A similar result is obtained for noise

where noise figure improves as gain increases.

01274415

FIGURE 1. Recommended Non-Inverting Gain Circuit

01274416

FIGURE 2. Recommended Inverting Gain Circuit

01274422

FIGURE 3. Current feedback topology

CLC401

www.national.com 8

Selecting Between the CLC400 or CLC401

The CLC400 is intended for gains of ±1to±

8 while the

CLC401 is designed for gains of ±7to±

50. Optimum per-

formance is achieved with a feedback resistor of 250Ωwith

the CLC400 and 1.5Ωwith the CLC401- this distinction may

be important in transimpedance applications such as D/A

buffering.Although the CLC400 can be used at higher gains,

the CLC401 will provide a wider bandwidth because loop

gain losses due to finite Z

are lower with the larger CLC401

feedback resistor as explained above. On the other hand,

the lower recommended feedback resistance of the CLC400

minimizes the output errors due to inverting input noise and

bias currents.

Increasing Bandwidth At High Gains

Bandwidth may be increased at high closed-loop gains by

adjusting R

and R

to make up for the losses in loop gain that

occur at these high gain settlings due to current division at

the inverting input. An approximate relationship my be ob-

tained by holding the LG expression constant as the gain is

changed from the design point used in the specifications

(that is, R

= 1.5kΩand R

=79Ω). For the CLC401 this

gives,

Equation 4

where A

is the desired non-inverting gain. Note that with A

= +20 we get the specified R

= 1.5kΩ, while at higher gains,

a lower value gives stable performance with improved band-

width.

Capacitive Feedback

Capacitive feedback should not be used with the CLC401

because of the potential for loop instability. See Application

Note OA-7 for active filter realizations with the CLC401.

Printed Circuit Layout

As with any high frequency device, a good PCB layout will

enhance performance. Ground plane construction and good

power supply bypassing close to the package are critical to

achieving full performance. In the non-inverting configura-

tion, the amplifier is sensitive to stray capacitance to ground

at the inverting input. Hence, the inverting node connections

should be small with minimal coupling to the ground plane.

Shunt capacitance across the feedback resistor should not

be used to compensate for this effect.

Parasitic or load capacitance directly on the output will intro-

duce additional phase shift in the loop degrading the loop

phase margin and leading to frequency response peaking. A

small series resistor before the capacitance effectively de-

couples this effect. The graphs on the preceding page illus-

trate the required resistor value and resulting performance

vs. capacitance.

Precision buffed resistors (PRP8351 series from Precision

Resistive Products) with low parasitic reactances were used

to develop the data sheet specifications. Precision carbon

composition resistors will also yield excellent results. Stan-

dard spirally-trimmed RN55D metal film resistors will work

with the slight decrease in bandwidth due to their reactive

nature at high frequencies.

Evaluation PC boards (part no. CLC730013 for through-hole

and CLC730027 for SOIC) for the CLC401 are available.

CLC401

www.national.com9

Physical Dimensions inches (millimeters)

unless otherwise noted

8-Pin SOIC

NS Package Number M08A

8-Pin MDIP

NS Package Number N08E

CLC401

www.national.com 10

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Email: support@nsc.com

National Semiconductor

Europe Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

Email: ap.support@nsc.com

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

www.national.com

CLC401 Fast Settling, Wideband High Gain Monolithic Op Amp

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.