X9258 Low Noise/Low Power/2-Wire Bus/256 Taps Data Sheet December 15, 2011 Quad Digital Controlled Potentiometers (XDCPTM) FN8168.6 Features * Four potentiometers in one package The X9258 integrates 4 digitally controlled potentiometers (XDCPTM) on a monolithic CMOS integrated circuit. * 256 resistor taps/potentiometer................. 0.4% resolution * 2-wire serial interface The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 non-volatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of DR0 to the WCR. * Wiper resistance, 40 typical @ V+ = 5V, V- = -5V * Four nonvolatile data registers for each potentiometer * Nonvolatile storage of wiper position * Standby current <5A max (total package) * Power supplies - VCC = 2.7V to 5.5V - V+ = 2.7V to 5.5V - V- = -2.7V to -5.5V * 100k, 50k total potentiometer resistance The XDCPTM can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. * High reliability - Endurance: 100,000 data changes per bit per register - Register data retention . . . . . . . . . . . . . . . . . . 100 years * 24 Ld SOIC, 24 Ld TSSOP * Dual supply version of X9259 * Pb-free (RoHS compliant) Block Diagram POT 0 VCC VSS R0 R1 V+ VR2 WP R3 VH0/RH0 WIPER COUNTER REGISTER (WCR) VL0/RL0 A0 A1 A2 A3 R2 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY INTERFACE AND CONTROL CIRCUITRY VH2/RH2 POT 2 VL2/RL2 VW0/RW0 SCL SDA R0 VW2/RW2 8 VW1/RW1 DATA R0 R2 1 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 1 VW3/RW3 VH1/RH1 R0 R1 VL1/RL1 R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 3 VH3/RH3 VL3/RL3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2006, 2011. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. X9258 Ordering Information PART NUMBER (Note 2) PART MARKING X9258US24Z (Note 1) X9258US Z X9258US24IZ (Note 1) VCC LIMITS (V) 50 PACKAGE (Pb-free) PKG. DWG. # 0 to +70 24 Ld SOIC (300 mil) M24.3 X9258US ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 X9258UV24IZ X9258UV ZI -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9258TS24Z X9258TS Z 0 to +70 24 Ld SOIC (300 mil) M24.3 X9258TS24IZ (Note 1) X9258TS ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 0 to +70 24 Ld SOIC (300 mil) M24.3 X9258US24IZ-2.7 (Note 1) X9258US ZG -40 to +85 24 Ld SOIC (300 mil) M24.3 X9258UV24IZ-2.7 -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 0 to +70 24 Ld SOIC (300 mil) M24.3 X9258TS24IZ-2.7 (Note 1) X9258TS ZG -40 to +85 24 Ld SOIC (300 mil) M24.3 X9258TV24IZ-2.7 X9258TV ZG -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9258TV24Z-2.7 X9258TV ZF 0 to +70 24 Ld TSSOP (4.4mm) MDP0044 X9258US24Z-2.7 (Note 1) X9258US ZF 5 10 POTENTIOMETER TEMPERATURE RANGE ORGANIZATION (C) (k) 100 2.7 to 5.5 50 X9258UV ZG X9258TS24Z-2.7 (Note 1) X9258TS ZF 100 NOTES: 1. Add "T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for X9258. For more information on MSL please see tech brief TB363. 2 FN8168.6 December 15, 2011 X9258 Pinout X9258 (24 LD SOIC, TSSOP) TOP VIEW NC 1 24 A3 A0 2 23 SCL VW3/RW3 3 22 VL2/RL2 VH3/RH3 4 21 VH2/RH2 VL3/RL3 5 20 VW2/RW2 V+ 6 19 V- 18 VSS VCC 7 X9258 VL0/RL0 8 17 VW1/RW1 VH0/RH0 9 16 VH1/RH1 VW0/RW0 10 15 VL1/RL1 A2 11 14 A1 12 13 SDA WP Pin Descriptions Pin Names SYMBOL Host Interface Pins DESCRIPTION SERIAL CLOCK (SCL) SCL Serial Clock The SCL input is used to clock data into and out of the X9258. SDA Serial Data A0 thru A3 SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to "Guidelines for Calculating Typical Values of Bus Pull-Up Resistors" on page 10. DEVICE ADDRESS (A0 - A3) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9258. A maximum of 16 devices may occupy the 2-wire serial bus. Device Address VH0/RH0 thru VH3/RH3, VL0/RL0 thru VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0 thru VW3/RW3 Potentiometers Pins (wiper equivalent) WP V+, V- Hardware Write Protection Analog Supplies VCC System Supply Voltage VSS System Ground NC No Connection (Allowed) Principles Of Operation The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. The X9258 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. VW/RW (VW0/RW0 - VW3/RW3) Serial Interface (2-Wire) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. The X9258 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9258 will be considered a slave device in all applications. Potentiometer Pins VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3) Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for the DCP analog section. 3 FN8168.6 December 15, 2011 X9258 Clock and Data Conventions Device Addressing Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Following a start condition the master must output the address of the slave it is accessing. The most significant 4 bits of the slave address are the device type identifier (refer to Figure 1). For the X9258 this is fixed as 0101[B]. Start Condition All commands to the X9258 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9258 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. DEVICE TYPE IDENTIFIER 0 1 0 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting 8 bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the 8 bits of data. The X9258 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte, the X9258 will respond with a final acknowledge. Array Description The X9258 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). 1 A3 A2 A1 A0 DEVICE ADDRESS FIGURE 1. SLAVE ADDRESS The next 4 bits of the slave address are the device address. The physical device address is defined by the state of the A0 thru A3 inputs. The X9258 compares the serial data stream with the address input state; a successful compare of all 4 address bits is required for the X9258 to respond with an acknowledge. The A0 thru A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs (during the internal nonvolatile write operation), can be used to take advantage of the typical 5ms nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command, the X9258 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9258 is still busy with the write operation, no ACK will be returned. If the X9258 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. 4 FN8168.6 December 15, 2011 X9258 ACK Polling Sequence . REGISTER SELECT NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING I3 I2 I1 I0 R1 R0 P1 P0 WIPER COUNTER INSTRUCTIONS REGISTER SELECT ISSUE START FIGURE 2. INSTRUCTION BYTE FORMAT ISSUE SLAVE ADDRESS The four high order bits define the instruction. The next 2 bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction. ISSUE STOP ACK RETURNED? NO Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. YES FURTHER OPERATION? NO YES ISSUE INSTRUCTION ISSUE STOP PROCEED PROCEED Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9258; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected potentiometer), Write Wiper Counter Register (change current wiper position of the selected potentiometer), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected data register). The sequence of operations is shown in Figure 4. Instruction Structure The next byte sent to the X9258 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the two potentiometers and when applicable they point to one of four associated registers. The format is shown in Figure 2. SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K S T O P FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE 5 FN8168.6 December 15, 2011 X9258 The Increment/Decrement command is different from the other commands. Once the command is issued and the X9258 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. TABLE 1. INSTRUCTION SET INSTRUCTION SET INSTRUCTION I3 I2 I1 I0 R1 R0 P1 P0 OPERATION Read Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by P1 - P0 and R1 - R0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1 - P0 and R1 - R0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by P1 - P0 and R1 - R0 to its associated Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by R1 - R0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four potentiometers to their respective Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by R1 - R0 of all four potentiometers Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch pointed to by P1 - P0 NOTE: 4. 1/0 = data is one or zero. 6 FN8168.6 December 15, 2011 X9258 SCL SDA 0 S T A R T 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 A C K S T O P FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE I SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE F I INC/DEC CMD ISSUED tWRID SCL SD A VOLTAGE OUT VW/RW FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER 7 FN8168.6 December 15, 2011 X9258 SERIAL DATA PATH VH/RH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 1 8 REGISTER 2 8 WIPER COUNTER REGISTER (WCR) REGISTER 3 INC/DEC LOGIC If WCR = 00[H] then VW/RW = VL/RL If WCR = FF[H] then VW/RW = VH/RH PARALLEL BUS INPUT COUNTER DECODER REGISTER 0 UP/DN UP/DN MODIFIED SCL VL/RL CLK VW/RW FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM DETAILED OPERATION All DCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9258 contains four Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: 1. Written directly by the host via the Write Wiper Counter Register instruction (serial load) 2. Written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load) 3. Can be modified one step at a time by the Increment/Decrement instruction. 4. Loaded with the contents of its data register zero (R0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9258 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. 8 Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (8-bit), Nonvolatile WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 NV NV NV NV NV NV NV NV (MSB) (LSB) Four 8-bit Data Registers for each DCP (sixteen 8-bit registers in total). {D7~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. FN8168.6 December 15, 2011 X9258 the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR. Wiper Counter Register, (8-bit), Volatile WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V V V (MSB) Instruction Format NOTES: (LSB) 5. "MACK"/"SACK": stands for the acknowledge sent by the master/slave. One 8-bit Wiper Counter Register for each DCP (four 8-bit registers in total.) 6. "A3 ~ A0": stands for the device addresses sent by the master. 7. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. {D7~D0}: These bits specify the wiper position of the respective DCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of 8. "I": stands for the increment operation, SDA held high during active SCL phase (high). 9. "D": stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) WIPER POSITION INSTRUCTION WCR DEVICE S DEVICE TYPE (SENT BY SLAVE ON SDA) M S OPCODE ADDRESSES S T IDENTIFIER ADDRESSES S A T A A A 0 1 0 1 A3 A2 A1 A0 1 0 0 1 0 0 P1 P0 WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 C O C C R K P K K T Write Wiper Counter Register (WCR) DEVICE S TYPE DEVICE T A IDENTIFIER ADDRESSES R 0 1 0 1 A3 A2 A1 A0 T S A C K INSTRUCTION OPCODE 1 0 1 0 DATA BYTE S WCR S (SENT BY MASTER ON SDA) A ADDRESSES A C C 0 0 P1 P0 WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 K K S T O P Read Data Register (DR) DEVICE S DEVICE TYPE T IDENTIFIER ADDRESSES S A A 0 1 0 1 A3 A2 A1 A0 C R K T INSTRUCTION OPCODE 1 0 1 1 DATA BYTE (SENT BY SLAVE ON SDA) M S S A T A R1 R0 P1 P0 WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 C O C K P K DR AND WCR ADDRESSES Write Data Register (WR) DEVICE S TYPE DEVICE T A IDENTIFIER ADDRESSES R 0 1 0 1 A3 A2 A1 A0 T S INSTRUCTION DR AND WCR OPCODE ADDRESSES A C 1 1 0 0 R1 R0 P1 P0 K 9 DATA BYTE S S (SENT BY MASTER ON SDA) A A C C WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 K K HIGH-VOLTAGE S WRITE CYCLE T O P FN8168.6 December 15, 2011 X9258 XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 S S A T C O K P DEVICE S INSTRUCTION DR AND WCR OPCODE ADDRESSES ADDRESSES A C 1 A3 A2 A1 A0 K 1 1 0 1 R1 R0 P1 P0 XFR Wiper Counter Register (WCR) to Data Register (DR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 DEVICE S INSTRUCTION DR AND WCR OPCODE ADDRESSES ADDRESSES A C 1 A3 A2 A1 A0 1 1 1 0 R1 R0 P1 P0 K S A C K HIGH-VOLTAGE WRITE CYCLE S T O P Increment/Decrement Wiper Counter Register (WCR) DEVICE S DEVICE TYPE T IDENTIFIER ADDRESSES A 0 1 0 1 A3 A2 A1 A0 R T S A C K INSTRUCTION OPCODE 0 0 1 0 WCR ADDRESSES 0 0 P1 P0 INCREMENT/DECREMENT S (SENT BY MASTER ON SDA) A I/D I/D . . . . I/D I/D C K S T O P Global XFR Data Register (DR) to Wiper Counter Register (WCR) DEVICE S DEVICE TYPE IDENTIFIER ADDRESSES T A 0 1 0 1 A3 A2 A1 A0 R T S A C K INSTRUCTION DR OPCODE ADDRESSES 0 0 0 1 R1 R0 0 0 S A C K S T O P Global XFR Wiper Counter Register (WCR) to Data Register (DR) DEVICE TYPE IDENTIFIER 0 1 0 DR DEVICE S INSTRUCTION OPCODE ADDRESSES ADDRESSES A C 1 A3 A2 A1 A0 K 1 0 0 0 R1 R0 0 0 Symbol Table WAVEFORM HIGH-VOLTAGE WRITE CYCLE S S A T C O K P Guidelines for Calculating Typical Values of Bus Pull-Up Resistors INPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 10 120 OUTPUTS VCC MAX RMIN = 100 RESISTANCE (k) S T A R T 80 IOL MIN RMAX = 60 =1.8k tR CBUS MAXIMUM RESISTANCE 40 20 0 MINIMUM RESISTANCE 0 20 40 60 80 100 120 BUS CAPACITANCE (pF) FN8168.6 December 15, 2011 X9258 Absolute Maximum Ratings Thermal Information Voltage on SDA, SCL or any Address Input with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage on V+ (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . .10V Voltage on V- (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . -10V (V+) - (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Any VH/RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ Any VL/RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Thermal Resistance (Typical) JA (C/W) JC (C/W) 24 Lead SOIC (Notes 10, 11). . . . . . . . 46 21 24 Lead TSSOP (Notes 10, 11) . . . . . . 68 17 Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage Range (Typical) X9258. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 10% X9258-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 10. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 11. For JC, the "case temp" location is taken at the package top center. Analog Specifications SYMBOL Over recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (Note 12) TYP End-to-end Resistance Tolerance MAX (Note 12) UNIT 20 % 50 mW 7.5 mA Power Rating +25C, each potentiometer IW Wiper Current Wiper current = 1mA RW Wiper Resistance IW = 1mA @ V+ = 3V, V- = -3V 150 250 RW Wiper Resistance IW = 1mA @ V+ = 5V, V- = -5V 40 100 V+ Voltage on V+ Pin V- VTERM Voltage on V- Pin X9258 +4.5 +5.5 V X9258-2.7 +2.7 +5.5 V X9258 -5.5 -4.5 V X9258 -2.7 -5.5 -2.7 V V- V+ V Voltage on any VH/RH or VL/RL Pin Noise Ref: 1kHz Resolution (Note 16) Absolute Linearity (Note 13) Vw(n)(actual) - Vw(n)(expected) Relative Linearity (Note 14) Vw(n + 1) - [Vw(n) + MI] Temperature Coefficient of RTOTAL -120 dBV 0.6 % Potentiometer Capacitance 11 MI (Note 15) 0.6 MI (Note 15) 300 Ratiometric Temperature Coefficient CH/CL/CW 1 ppm/C 20 See "Test Circuit #3 SPICE Macro Model" on page 13 10/10/25 ppm/C pF FN8168.6 December 15, 2011 X9258 DC Operating Characteristics SYMBOL Over recommended operating conditions, unless otherwise specified. PARAMETER MIN (Note 12) TEST CONDITIONS ICC1 VCC Supply Current (Nonvolatile Write) fSCL = 400kHz, SDA = Open, Other Inputs = VSS ICC2 VCC Supply Current (Move Wiper, Write, Read) fSCL = 400kHz, SDA = Open, Other Inputs = VSS ISB VCC Current (Standby) ILI TYP MAX (Note 12) UNIT 1 mA 100 A SCL = SDA = VCC, Addr. = VSS 5 A Input Leakage Current VIN = VSS to VCC 10 A ILO Output Leakage Current VOUT = VSS to VCC 10 A VIH Input HIGH Voltage VCC x 0.7 VCC + 0.1 V VIL Input LOW Voltage -0.5 VCC x 0.3 V VOL Output LOW Voltage 0.4 V IOL = 3mA NOTES: 12. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 14. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 15. MI = RTOT/255 or (VH/RH--VL/RL)/255, single potentiometer. 16. Max = all four arrays cascaded together; typical = individual array resolutions. Endurance and Data Retention PARAMETER MIN (Note 12) UNIT 100,000 Data changes per bit per register 100 years Minimum Endurance Data Retention Capacitance TEST CONDITIONS MAX (Note 12) UNIT CI/O (Note 17) Input/Output Capacitance (SDA) VI/O = 0V 8 pF CIN (Note 17) VIN = 0V 6 pF SYMBOL PARAMETER Input Capacitance (A0, A1, A2, A3, and SCL) Power-Up Timing SYMBOL PARAMETER MIN (Note 12) MAX (Note 12) UNIT tPUR (Note 18) Power-up to Initiation of Read Operation 1 ms tPUW (Note 18) Power-up to Initiation of Write Operation 5 ms 50 V/ms tR VCC (Note 19) VCC Power-up Ramp 0.2 NOTES: 17. This parameter is periodically sampled and not 100% tested. 18. tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. 19. Sample tested only. 12 FN8168.6 December 15, 2011 X9258 Power-Up and Power-Down Requirement Equivalent AC Load Circuit The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach their final values within 1ms of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The VCC ramp rate specification is always in effect. 5V 2.7V 1533 SDA OUTPUT 100pF 100pF AC Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x 0.5 Test Circuit #3 SPICE Macro Model MACRO MODEL RTOTAL RH CL CH CW 10pF RL 10pF 25pF RW AC Timing Over recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER MIN (Note 12) MAX (Note 12) UNIT 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time (Note 20) 300 ns tF SCL and SDA Fall Time (Note 20) 300 ns tAA SCL Low to SDA Data Output Valid Time 900 ns tDH SDA Data Output Hold Time 50 ns Noise Suppression Time Constant at SCL and SDA Inputs 50 ns 1300 ns TI tBUF Bus Free Time (Prior to any Transmission) tSU:WPA WP, A0, A1, A2 and A3 Setup Time 0 ns tHD:WPA WP, A0, A1, A2 and A3 Hold Time 0 ns NOTE: 20. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 13 FN8168.6 December 15, 2011 X9258 High-Voltage Write Cycle Timing SYMBOL PARAMETER tWR High-Voltage Write Cycle Time (Store Instructions) TYP MAX (Note 12) UNIT 5 10 ms DCP Timing SYMBOL MIN MAX (Note 12) (Note 12) PARAMETER UNIT tWRPO Wiper Response Time After the Third (Last) Power Supply is Stable 10 s tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 s tWRID Wiper Response Time from an Active SCL/SCK Edge (Increment/Decrement Instruction) 10 s Timing Diagrams 2-Wire Interface Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA 14 tDH FN8168.6 December 15, 2011 X9258 DCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx DCP Timing (for Increment/Decrement Instruction) SCL SDA WIPER REGISTER ADDRESS INCREMENT/DECREMENT INCREMENT/DECREMENT tWRID VWx Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (ANY INSTRUCTION) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 A2, A3 15 FN8168.6 December 15, 2011 X9258 Applications information Basic Configurations of Electronic Potentiometers VR +VR VW/RW I FIGURE 9. THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER FIGURE 10. TWO-TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT Application Circuits VS + VO - VIN VO (REG) 317 R1 R2 IADJ R1 R2 VO = (1+ R2/R1) VS VO (REG) = 1.25V (1+ R2/R1)+ IADJ R2 FIGURE 11. NON-INVERTING AMPLIFIER R1 FIGURE 12. VOLTAGE REGULATOR R2 VS VS 100k - - + VO + VO TL072 10k } +12V 10k } 10k R1 R2 VUL = {R1/(R1+R2)} VO(MAX) VLL = {R1/(R1+R2)} VO(MIN) -12V FIGURE 13. OFFSET VOLTAGE ADJUSTMENT 16 FIGURE 14. COMPARATOR WITH HYSTERESIS FN8168.6 December 15, 2011 X9258 Application Circuits (Continued) C VS + R2 R1 VS VO - - R VO + R3 R2 R4 All RS = 10k R1 VO = G VS -1/2 G +1/2 GO = 1 + R2/R1 fc = 1/(2RC) FIGURE 15. ATTENUATOR FIGURE 16. FILTER R2 R1 R2 } VS } C1 VS + - - VO + R1 ZIN R3 VO = G VS G = - R2/R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FIGURE 18. EQUIVALENT L-R CIRCUIT FIGURE 17. INVERTING AMPLIFIER C R2 - R1 - + + } RA } RB FREQUENCY R1, R2, C AMPLITUDE RA, RB FIGURE 19. FUNCTION GENERATOR 17 FN8168.6 December 15, 2011 X9258 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A MILLIMETERS (N/2)+1 N SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 0.05 A2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL "X" 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0 - 8 DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN8168.6 December 15, 2011 X9258 Package Outline Drawing M24.3 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 2, 3/11 24 INDEX AREA 7.60 (0.299) 7.40 (0.291) 10.65 (0.419) 10.00 (0.394) DETAIL "A" 1 2 3 TOP VIEW 1.27 (0.050) 0.40 (0.016) SEATING PLANE 2.65 (0.104) 2.35 (0.093) 15.60 (0.614) 15.20 (0.598) 0.75 (0.029) x 45 0.25 (0.010) 0.30 (0.012) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.33 (0.013) 8 0 0.32 (0.012) 0.23 (0.009) SIDE VIEW "B" SIDE VIEW "A" 1.981 (0.078) 9.373 (0.369) 1.27 (0.050) NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. 0.533 (0.021) TYPICAL RECOMMENDED LAND PATTERN 19 FN8168.6 December 15, 2011