3.3 V/2.5 V LVCMOS 1:12 Clock Fanout Buffer MPC9448 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET The Freescale Semiconductor, Inc. MPC9448 is a 3.3 V or 2.5 V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. Features * * * * * * * * * * * * * 12 LVCMOS compatible clock outputs Selectable LVCMOS and differential LVPECL compatible clock inputs Maximum clock frequency of 350 MHz Maximum clock skew of 150 ps Synchronous output stop in logic low state eliminates output runt pulses High-impedance output control 3.3 V or 2.5 V power supply Drives up to 24 series terminated clock lines Ambient temperature range -40C to +85C 32-Lead LQFP packaging, Pb-free Supports clock distribution in networking, telecommunication and computing applications Pin and function compatible to MPC948 For drop in replacement part use 83948AYI-147 LOW VOLTAGE 3.3 V/2.5 V LVCMOS 1:12 CLOCK FANOUT BUFFER AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 terminated transmission lines on the incident edge. Each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5 V or 3.3 V power supply and an ambient temperature range of -40C to +85C. The MPC9448 is pin and function compatible but performance-enhanced to the MPC948. MPC9448 Rev 7 3/15/16 1 (c)2016 Integrated Device Technology, Inc. Q4 VCC Q5 GND Q6 VCC Q7 Q0 VCC GND MPC9448 DATASHEET 24 23 22 21 20 19 18 17 Q1 Q3 25 16 GND Q3 VCC 26 15 Q8 Q2 27 14 VCC GND 28 13 Q9 Q1 29 12 GND VCC 30 11 Q10 Q0 31 10 VCC GND 32 9 Q11 VCC Q6 CLK_STOP Q7 SYNC Q8 1 2 3 4 5 6 7 VCC CLK_SEL MPC9448 OE Q5 CLK_STOP Q4 VCC PCLK 1 Q2 PCLK CCLK CLK Stop CCLK 0 CLK_SEL PCLK PCLK 8 Q10 VCC OE Q11 (All input resistors have a value of 25 k) Figure 1. Logic Diagram GND Q9 Figure 2. 32-Lead Pinout (Top View) Table 1. Function Table Control Default 0 1 CLK_SEL 1 PECL differential input selected CCLK input selected OE 1 Outputs disabled (high-impedance state)(1) Outputs enabled CLK_STOP 1 Outputs synchronously stopped in logic low state Outputs active 1. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP. Table 2. Pin Configurations Pin I/O Type Function PCLK, PCLK Input LVPECL Clock signal input CCLK Input LVCMOS Alternative clock signal input CLK_SEL Input LVCMOS Clock input select CLK_STOP Input LVCMOS Clock output enable/disable OE Input LVCMOS Output enable/disable (high-impedance tristate) Q0-11 Output LVCMOS Clock outputs GND Supply Ground Negative power supply (GND) VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation MPC9448 Rev 7 3/15/16 2 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET Table 3. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V DC Input Current 20 mA IOUT DC Output Current 50 mA TStor Storage temperature 125 C VOUT IIN -65 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol Characteristics Min Typ Max Unit VCC 2 Condition VTT Output Termination Voltage V MM ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 2000 V LU Latch-up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = -40C to +85C) Symbol Characteristics Min Max Unit 2.0 VCC + 0.3 V LVCMOS -0.3 0.8 VIH Input HIGH Voltage VIL Input LOW Voltage VPP Peak-to-Peak Input Voltage PCLK 250 Common Mode Range PCLK 1.1 VCMR (1) IIN Input Current(2) VOH Output HIGH Voltage VOL Output LOW Voltage ZOUT Output Impedance ICCQ(4) Typ V LVCMOS mV LVPECL VCC - 0.6 V LVPECL 300 A VIN = VCC or GND V IOH = -24 mA(3) 0.55 0.30 V V IOL = 24 mA(3) IOL = 12 mA 2.0 mA 2.4 17 Maximum Quiescent Supply Current Condition All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC = 3.3 V) or one 50 series terminated transmission line (for VCC = 2.5 V). 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. MPC9448 Rev 7 3/15/16 3 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = -40C to +85C)(1) Symbol fref Characteristics Min Input Frequency Typ 0 Max Unit 350 MHz Condition fMAX Maximum Output Frequency 0 350 MHz VPP Peak-to-Peak Input Voltage PCLK 400 1000 mV LVPECL Common Mode Range PCLK 1.3 VCC - 0.8 V LVPECL VCMR (2) tP, REF tr, tf Reference Input Pulse Width 1.4 ns CCLK Input Rise/Fall Time PCLK to any Q CCLK to any Q 1.6 1.3 1.0(3) ns 3.6 3.3 ns ns tPLH/HL tPLH/HL Propagation Delay tPLZ, HZ Output Disable Time 11 ns tPZL, LZ Output Enable Time 11 ns tS Setup Time CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 ns ns tH Hold Time CCLK to CLK_STOP PCLK to CLK_STOP 1.0 1.5 ns ns tsk(O) Output-to-Output Skew tsk(PP) Device-to-Device Skew tSK(P) Output Pulse skew (4) DCQ Output Duty Cycle tr, tf Output Rise/Fall Time 150 ps PCLK or CCLK to any Q 2.0 ns Using CCLK Using PCLK 300 400 ps ps fQ<170 MHz 45 50 0.1 0.8 to 2.0 V 55 % DCREF = 50% 1.0 ns 0.55 to 2.4 V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Table 7. DC Characteristics (VCC = 2.5 V 5%, TA = -40C to +85C) Symbol Characteristics Min Typ Max Unit Condition VIH Input high voltage 1.7 VCC + 0.3 V LVCMOS VIL Input low voltage -0.3 0.7 V LVCMOS VPP Peak-to-peak input voltage PCLK 250 Common Mode Range PCLK 1.0 VCMR(1) IIN Input current (2) VOH Output High Voltage VOL Output Low Voltage ZOUT Output impedance ICCQ (4) mV LVPECL VCC - 0.7 V LVPECL 300 A VIN = GND or VIN = VCC V IOH = -15 mA(3) V IOL= 15 mA(3) 1.8 0.6 19 Maximum Quiescent Supply Current 2.0 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines at VCC = 2.5 V. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. MPC9448 Rev 7 3/15/16 4 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET Table 8. AC Characteristics (VCC = 2.5 V 5%, TA = -40C to +85C)(1) Symbol fref Characteristics Min Input Frequency Typ 0 Max Unit 350 MHz Condition fMAX Maximum Output Frequency 0 350 MHz VPP Peak-to-peak input voltage PCLK 400 1000 mV LVPECL Common Mode Range PCLK 1.2 VCC - 0.8 V LVPECL VCMR (2) tP, REF tr, tf Reference Input Pulse Width 1.4 ns CCLK Input Rise/Fall Time PCLK to any Q CCLK to any Q 1.5 1.7 1.0(3) ns 4.2 4.4 ns ns tPLH/HL tPLH/HL Propagation delay tPLZ, HZ Output Disable Time 11 ns tPZL, LZ Output Enable Time 11 ns tS Setup time CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 ns ns tH Hold time CCLK to CLK_STOP PCLK to CLK_STOP 1.0 1.5 ns ns tsk(O) Output-to-output Skew tsk(PP) Device-to-device Skew tSK(p) Output pulse skew (4) 150 ps PCLK or CCLK to any Q 2.7 ns Using CCLK Using PCLK 200 300 ps ps 55 55 % % 1.0 ns DCQ DCREF = 50% Output Duty Cycle tr, tf 0.8 to 2.0 V fQ< 350 MHz and using CCLK fQ<200 MHz and using PCLK Output Rise/Fall Time 45 45 0.1 50 50 0.6 to 1.8 V 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. MPC9448 Rev 7 3/15/16 5 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET APPLICATION INFORMATION 3.0 CCLK or PCLK 2.5 CLK_STOP Q0 to Q11 Voltage (V) Driving Transmission Lines The MPC9448 clock driver was designed to drive highspeed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC = 3.3 V), the outputs can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Freescale application note AN1091. In most high performance clock networks, point-topoint distribution of signals is the method of choice. In a pointto-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC2. MPC9448 Output BufferR IN RS = 33 ZO = 50 RS = 33 ZO = 50 RS = 33 ZO = 50 In 1.5 1.0 0.5 0 2 6 8 Time (ns) 10 12 14 The waveform plots in Figure 5 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9448 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9448. The output waveform in Figure 5 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: OutA OutB0 17 VL = Z0 = RS = R0 = VL = = OutB1 Figure 4. Single versus Dual Transmission Lines This technique draws a fairly high level of DC current ,and thus, only a single terminated line can be driven by each output of the MPC9448 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9448 clock driver is effectively doubled due to its capability to drive multiple lines at VCC = 3.3 V. MPC9448 Rev 7 3/15/16 4 Figure 5. Single versus Dual Line Termination Waveforms MPC9448 Output Buffer 17 OutB tD = 3.9386 2.0 Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram IN OutA tD = 3.8956 VS (Z0 (RS+R0 +Z0)) 50 || 50 33 || 33 17 3.0 (25 (16.5+17+25) 1.28 V At the load end, the voltage will double, due to the near unity reflection coefficient, to 2.5 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 6 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET Since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6 should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC9448 Output Buffer RS = 16 ZO = 50 RS = 16 ZO = 50 Table 9. Die Junction Temperature and MTFB Junction Temperature (C) MTBF (Years) 100 20.4 110 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC9448 needs to be controlled, and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC9448 is represented in equation 1. Where ICCQ is the static current consumption of the MPC9448, CPD is the power dissipation capacitance per output. CL represents the external capacitive output load, and N is the number of active outputs (N is always 12 in case of the MPC9448). The MPC9448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output, termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination. VOL, IOL, VOH and IOH are a function of the output termination technique, and DCQ is the clock signal duty cycle. If transmission lines are used, CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient), and TA is the ambient temperature. According to Figure 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC9448 in a series terminated transmission line system, equation 4. 17 17+ 16 || 16 = 50 || 50 25 = 25 Figure 6. Optimized Dual Line Termination Power Consumption of the MPC9448 and Thermal Management The MPC9448 AC specification is guaranteed for the entire operating frequency range up to 350 MHz. The MPC9448 power consumption, and the associated long-term reliability, may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC9448 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability, please refer to the Freescale application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: PTOT = [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] * VCC Equation 1 M PTOT = VCC * [ ICCQ + VCC * fCLOCK * ( N * CPD + CL ) ] + [ DCQ * IOH * (VCC - VOH) + (1 - DCQ) * IOL * VOL ] Equation 2 M P Equation 3 TJ = TA + PTOT * Rthja fCLOCK,MAX = MPC9448 Rev 7 3/15/16 1 CPD * N * V2CC * [ 7 Tj,MAX - TA Rthja - (ICCQ * VCC) ] Equation 4 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET TJ,MAX should be selected according to the MTBF system requirements, and Figure 9 Rthja can be derived from Figure 10. The Rthja represent data based on 1S2P boards. Using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC9448. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection, a decision on the maximum operating frequency can be made. Table 10. Thermal Package Impedance of the 32ld LQFP Convection, LFPM Rthja (1P2S board), Rthja (2P2S board), C/W C/W Still air 86 61 100 lfpm 76 56 200 lfpm 71 54 300 lfpm 68 53 400 lfpm 66 52 500 lfpm 60 49 Figure 7. Maximum MPC9448 Frequency, VCC = 3.3 V, MTBF 9.1 Years, Driving Series Terminated transmission lines, 2s2p board Figure 8. Maximum MPC9448 frequency, VCC = 3.3 V, MTBF 9.1 Years, 4 pF Load per Line, 2s2p Board Figure 9. No maximum Frequency Limitation for VCC = 3.3 V, MTBF 4 Years, Driving Series Terminated Transmission Lines, 2s2p Board Figure 10. Maximum MPC9448 Frequency, VCC = 3.3 V, MTBF 4 Years, 4 pF Load per Line, 2s2p Board MPC9448 Rev 7 3/15/16 8 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit MPC9448 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 RT = 50 VTT VTT Figure 11. CCLK MPC9448 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V Differential Pulse Generator Z = 50 ZO = 50 MPC9448 DUT ZO = 50 RT = 50 RT = 50 VTT VTT Figure 12. PCLK MPC9448 AC Test Reference MPC9448 Rev 7 3/15/16 9 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 DATASHEET PCLK VCC CCLK VCC2 VPP PCLK GND VCC VCC VCC2 QX QX GND tP(LH) GND tP(HL) tP(LH) Figure 13. Propagation Delay (tPD) Test Reference tP(HL) Figure 14. Propagation Delay (tPD) Test Reference VCC VCC2 VCC VCC2 CCLK GND GND VCC VCC2 VCC VCC2 QX GND tSK(LH) GND tSK(HL) tP(HL) tP(LH) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. tSK(P) = | tPLH - tPHL | Figure 16. Output Pulse Skew (tSK(P)) Test Reference Figure 15. Output-to-Output Skew tSK(LH, HL) VCC VCC2 GND tP T0 DC = (tP T0 x 100%) tF VCC=3.3 V VCC=2.5 V 2.4 1.8 V 0.55 0.6 V tR The time from the output controlled edge to the noncontrolled edge, divided by the time between output controlled edges, expressed as a percentage. Figure 18. Output Transition Time Test Reference Figure 17. Output Duty Cycle (DC) VCC TN TN+1 TJIT(CC) = |TN-TN+1| GND VCC VCC2 CLK_STOP The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. GND tS Figure 19. Cycle-to-Cycle Jitter MPC9448 Rev 7 3/15/16 VCC2 CCLK PCLK tH Figure 20. Setup and Hold Time (tS, tH) Test Reference 10 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9448 Data Sheet 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER PACKAGE DIMENSIONS 4X 0.20 H 6 A-B D D1 PIN 1 INDEX 3 e/2 D1/2 32 A, B, D 25 1 E1/2 A F B 6 E1 E 4 F DETAIL G 8 17 9 7 D/2 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 4 D A-B D H SEATING PLANE DETAIL G D 4X 0.20 C E/2 28X e 32X C 0.1 C DETAIL AD PLATING BASE METAL b1 c c1 b 8X (1) 0.20 R R2 A2 5 C A-B D SECTION F-F R R1 A M 0.25 GAUGE PLANE A1 (S) L (L1) DETAIL AD 8 DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 --0.20 REF CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE MPC9448 REVISION 7 3/15/16 11 (c)2016 Integrated Device Technology, Inc. MPC9448 DATASHEET Revision History Sheet Rev Table Page Description of Change Date 7 1 NRND - Not Recommend for New Designs 12/21/12 7 1 Removed NRND - Not Recommended for New Designs 2/13/15 7 1 Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02 3/15/16 MPC9448 Rev 7 3/15/16 12 (c)2016 INTEGRATED DEVICE TECHNOLOGY, INC. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright (c)2016 Integrated Device Technology, Inc.. All rights reserved.