ADP5050-EVALZ - Analog Devices

5-Channel Integrated Power Solution with Quad

Buck Regulators and 200 mA LDO Regulator

Data Sheet

ADP5050

Rev. B Document Feedback

nformation furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

Wide input voltage range: 4.5 V to 15 V

±1.5% output accuracy over full temperature range

250 kHz to 1.4 MHz adjustable switching frequency

Adjustable/fixed output options via factory fuse or I2C interface

I2C interface with interrupt on fault conditions

Power regulation

Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A

sync buck regulators with low-side FET driver

Channel 3 and Channel 4: 1.2 A sync buck regulators

Channel 5: 200 mA low dropout (LDO) regulator

Single 8 A output (Channel 1 and Channel 2 operated in parallel)

Dynamic voltage scaling (DVS) for Channel 1 and Channel 4

Precision enable with 0.8 V accurate threshold

Active output discharge switch

Programmable phase shift in 90° steps

Individual channel FPWM/PSM mode selection

Frequency synchronization input or output

Optional latch-off protection on OVP/OCP failure

Power-good flag on selected channels

Low input voltage detection

Overheat detection on junction temperature

UVLO, OCP, and TSD protection

48-lead, 7 mm × 7 mm LFCSP package

−40°C to +125°C junction temperature

APPLICATIONS

Small cell base stations

FPGA and processor applications

Security and surveillance

Medical applications

GENERAL DESCRIPTION

The ADP5050 combines four high performance buck regulators

and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP

package that meets demanding performance and board space

requirements. The device enables direct connection to high input

voltages up to 15 V with no preregulators.

Channel 1 and Channel 2 integrate high-side power MOSFETs and

low-side MOSFET drivers. External NFETs can be used in low-side

power devices to achieve an efficiency optimized solution and

deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.

Combining Channel 1 and Channel 2 in a parallel configuration

can provide a single output with up to 8 A of current.

Channel 3 and Channel 4 integrate both high-side and low-side

MOSFETs to deliver output current of 1.2 A.

TYPICAL APPLICATION CIRCUIT

CHANNEL 2

BUCK REGUL ATOR

(1.2A/2.5A/4A)

CHANNEL 3

BUCK REGUL ATOR

(1.2A)

OSCILLATOR

INT V RE G

100mA

VREG

SYNC/MODE

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

BST3

SW3

FB3

PGND3

ALERT

BST4

SW4

FB4

PGND4

INT

VREG

PVIN1

COMP1

EN1

PVIN2

COMP2

EN2

PVIN3

SS34

COMP3

EN3

VDDIO

PVIN4

COMP4

EN4

SCL

SDA

C6 C7

C8 C9

C10

C11

C12

C13

4.5V T O 15V

VOUT1

VOUT2

VOUT3

VOUT4

RILIM1

RILIM2

I2CPWRGD

VREG

EXPOSED PAD

SS12

VDD

CHANNEL 5

200mA LDO

REGULATOR FB5

PVIN5

EN5

VOUT5

C14 C15

VOUT5

1.7V T O 5.5V

ADP5050

CHANNEL 1

BUCK REGUL ATOR

(1.2A/2.5A/4A)

CHANNEL 4

BUCK REGUL ATOR

(1.2A)

10899-001

Figure 1.

Table 1. Family Models

Model Channels I2C Package

ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP

ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP

ADP5052 Four bucks, one LDO No 48-Lead LFCSP

ADP5053 Four bucks, supervisory No 48-Lead LFCSP

ADP5054 Four high current bucks No 48-Lead LFCSP

The switching frequency of the ADP5050 can be programmed

or synchronized to an external clock. The ADP5050 contains a

precision enable pin on each channel for easy power-up sequencing

or adjustable UVLO threshold.

The ADP5050 integrates a general-purpose LDO regulator with

low quiescent current and low dropout voltage that provides up

to 200 mA of output current.

The optional I2C interface provides the user with flexible

configuration options, including adjustable and fixed output

voltage options, junction temperature overheat warning, low

input voltage detection, and dynamic voltage scaling (DVS).

ADP5050 Data Sheet

Rev. B | Page 2 of 57

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Typical Application Circuit ............................................................. 1

Revision History ............................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications ..................................................................................... 5

Buck Regulator Specifications .................................................... 6

LDO Regulator Specifications .................................................... 8

I2C Interface Timing Specifications ........................................... 9

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Theory of Operation ...................................................................... 19

Buck Regulator Operational Modes ......................................... 19

Adjustable and Fixed Output Voltages .................................... 20

Dynamic Voltage Scaling (DVS) .............................................. 20

Internal Regulators (VREG and VDD) ................................... 20

Separate Supply Applications .................................................... 20

Low-Side Device Selection ........................................................ 21

Bootstrap Circuitry .................................................................... 21

Active Output Discharge Switch .............................................. 21

Precision Enabling ...................................................................... 21

Oscillator ..................................................................................... 21

Synchronization Input/Output ................................................. 22

Soft Start ...................................................................................... 23

Parallel Operation....................................................................... 23

Startup with Precharged Output .............................................. 23

Current-Limit Protection .......................................................... 24

Frequency Foldback ................................................................... 24

Hiccup Protection ...................................................................... 24

Latch-Off Protection .................................................................. 24

Undervoltage Lockout (UVLO) ............................................... 25

Power-Good Function ............................................................... 25

Interrupt Function ...................................................................... 25

Thermal Shutdown ..................................................................... 26

Overheat Detection .................................................................... 26

Low Input Voltage Detection .................................................... 26

LDO Regulator ........................................................................... 26

I2C Interface .................................................................................... 27

SDA and SCL Pins ...................................................................... 27

I2C Addresses .............................................................................. 27

Self-Clear Register Bits .............................................................. 27

I2C Interface Timing Diagrams ................................................ 28

Applications Information .............................................................. 29

ADIsimPower Design Tool ....................................................... 29

Programming the Adjustable Output Voltage ........................ 29

Voltage Conversion Limitations ............................................... 29

Current-Limit Setting ................................................................ 29

Soft Start Setting ......................................................................... 30

Inductor Selection ...................................................................... 30

Output Capacitor Selection....................................................... 30

Input Capacitor Selection .......................................................... 31

Low-Side Power Device Selection ............................................ 31

Programming the UVLO Input ................................................ 31

Compensation Components Design ....................................... 32

Power Dissipation....................................................................... 32

Junction Temperature ................................................................ 33

Design Example .............................................................................. 34

Setting the Switching Frequency .............................................. 34

Setting the Output Voltage ........................................................ 34

Setting the Current Limit .......................................................... 34

Selecting the Inductor ................................................................ 34

Selecting the Output Capacitor ................................................ 35

Selecting the Low-Side MOSFET ............................................. 35

Designing the Compensation Network ................................... 35

Selecting the Soft Start Time..................................................... 35

Selecting the Input Capacitor ................................................... 35

Recommended External Components .................................... 36

Circuit Board Layout Recommendations ................................... 37

Typical Application Circuits ......................................................... 38

Detailed Register Descriptions ..................................................... 42

....................................................................................................... 42

3), Address 0x03 ......................................................................... 43

Data Sheet ADP5050

Rev. B | Page 3 of 57

....................................................................................................... 43

Channel 4), Address 0x05 .......................................................... 44

Discharge Function Configuration), Address 0x06 ................... 45

Overvoltage Latch-Off Configuration), Address 0x07 .............. 46

Configuration), Address 0x08 ................................................... 47

Warning Threshold Configuration), Address 0x09 ................ 48

0x0A .............................................................................................. 49

for PWRGD Pin), Address 0x0B ................................................. 50

Address 0x0C ............................................................................... 51

....................................................................................................... 51

Address 0x0E ............................................................................... 52

Address 0x0F ............................................................................... 53

Factory Programmable Options .................................................... 54

Factory Default Options............................................................. 56

Outline Dimensions ........................................................................ 57

Ordering Guide ........................................................................... 57

REVISION HISTORY

9/15—Rev. A to Rev. B

Changes to Figure 1 and Table 1 ..................................................... 1

3/14—Rev. 0 to Rev. A

Changed Pin 13 from nINT to INT ............................ Throughout

Added Table 1; Renumbered Sequentially ..................................... 1

Changes to Figure 8......................................................................... 13

Changes to Figure 12 ...................................................................... 14

Changes to Table 14 ........................................................................ 30

Updated Outline Dimensions (Exposed Paddle Changed for

JEDEC Compliance) ....................................................................... 57

5/13—Revision 0: Initial Version

ADP5050 Data Sheet

Rev. B | Page 4 of 57

DETAILED FUNCTIONAL BLOCK DIAGRAM

DG1

PWRGD

DG3

UVLO1

PVIN1

SW1

BST1

VREG

DRIVER

PGND

DL1

CONTROL LOGIC

AND MOSFE T

DRIVE R W ITH

ANTICROSS

PROTECTION

CONTROL LOGIC

AND MOSFE T

DRIVE R W ITH

ANTICROSS

PROTECTION

EN1

0.8V

1MΩ

HICCUP

AND

LATCH-OFF

OCP

COMP1

FB1

0.8V

CLK1

SLOPE

COMP

CLK1

0.72V PWRGD1

ZERO

CROSS

CURRENT-LIMIT

SELECTION

FREQUENCY

FOLDBACK

–

CHANNEL 1 BUCK REGULATOR

DUPLI CATE CHANNEL 1

CHANNEL 2 BUCK REGULATOR

CURRENT BALANCE

EN2

COMP2

FB2

DL2

PVIN2

SW2

BST2

DISCHARGE

SWITCH

VID1 0.99V

OVP

LATCH-OFF

EA1

CMP1

OSCILLATOR

SYNC/MODE

SOFT START

DECODER

SS12

SS34

VDD

VREG

INTERNAL

REGULATOR

PVIN1

VDDIO

SCL

SDA

INTERFACE

AND

REGISTERS

VREG

POWER-ON

RESET

PWRGD

HOUSEKEEPING

LOGIC

UVLO3

PVIN3

SW3

BST3

VREG

DRIVER Q3

DRIVER

PGND3

EN3

COMP3

FB3

CHANNEL 3 BUCK REGULATOR

DUPLI CATE CHANNEL 3

CHANNEL 4 BUCK REGULATOR

EN4

COMP4

FB4 PGND4

PVIN4

SW4

BST4

CS1

–

CS3

PVIN5 VOUT5

EN5

LDO

CONTROL

FB5

0.5V

CHANNEL 5 LDO REGULAT OR

0.8V

1MΩ

–

DISCHARGE

SWITCH

0.8V

1MΩ

HICCUP

AND

LATCH-OFF

OCP

0.8V

CLK3

SLOPE

COMP

CLK3

0.72V PWRGD3

FREQUENCY

FOLDBACK

–

VID3 0.99V

OVP

LATCH-OFF

EA3

CMP3

ZERO

CROSS

EA5

10899-202

INT

Figure 2.

Data Sheet ADP5050

Rev. B | Page 5 of 57

SPECIFICATIONS

VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,

unless otherwise noted.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

4.5

15.0

PVIN1, PVIN2, PVIN3, PVIN4 pins

QUIESCENT CURRENT PVIN1, PVIN2, PVIN3, PVIN4 pins

Operating Quiescent Current IQ(4-BUCKS) 4.8 6.25 mA No switching, all ENx pins high

ISHDN(4BUCKS+LDO) 25 65 µA All ENx pins low

UNDERVOLTAGE LOCKOUT UVLO PVIN1, PVIN2, PVIN3, PVIN4 pins

Rising Threshold VUVLO-RISING 4.2 4.36 V

Falling Threshold VUVLO-FALLING 3.6 3.78 V

Hysteresis VHYS 0.42 V

OSCILLATOR CIRCUIT

Switching Frequency fSW 700 740 780 kHz RT = 25.5 kΩ

Switching Frequency Range 250 1400 kHz

SYNC Input

Input Clock Range fSYNC 250 1400 kHz

Input Clock Pulse Width

Minimum On Time tSYNC_MIN_ON 100 ns

Minimum Off Time tSYNC_MIN_OFF 100 ns

Input Clock High Voltage VH(SYNC) 1.3 V

Input Clock Low Voltage VL(SYNC) 0.4 V

SYNC Output

Clock Frequency fCLK fSW kHz

Positive Pulse Duty Cycle tCLK_PULSE_DUTY 50 %

Rise or Fall Time tCLK_RISE_FAL L 10 ns

High Level Voltage VH(SYNC_OUT) VVREG V

PRECISION ENABLING EN1, EN2, EN3, EN4, EN5 pins

High Level Threshold VTH_H(EN) 0.806 0.832 V

Low Level Threshold VTH_L(EN) 0.688 0.725 V

Pull-Down Resistor RPULL-DOWN(EN) 1.0 MΩ

POWER GOOD

Internal Power-Good Rising Threshold VPWRGD(RISE) 86.3 90.5 95 %

Internal Power-Good Hysteresis VPWRGD(HYS) 3.3 %

Internal Power-Good Falling Delay tPWRGD_FAL L 50 µs

Rising Delay for PWRGD Pin tPWRGD_PIN_RISE 1 ms

Leakage Current for PWRGD Pin IPWRGD_LEAKAGE 0.1 1 µA

Output Low Voltage for PWRGD Pin VPWRGD_LOW 50 100 mV IPWRGD = 1 mA

LOGIC INPUTS (SCL AND SDA PINS) VDDIO = 3.3 V

High Level Threshold VLOGIC_HIGH 0.7 × VDDIO V

Low Level Threshold VLOGIC_LOW 0.3 × VDDIO V

LOGIC OUTPUTS

Low Level Output Voltage

SDA Pin VSDA_LOW 0.4 V VDDIO = 3.3 V, ISDA = 3 mA

INT Pin VINT_LOW 0.4 V IINT = 3 mA

INTERNAL REGULATORS

VDD Output Voltage VVDD 3.2 3.305 3.4 V IVDD = 10 mA

VDD Current Limit ILIM_VDD 20 51 80 mA

VREG Output Voltage

VREG

4.9

5.1

5.3

VREG Dropout Voltage VDROPOUT 225 mV IVREG = 50 mA

VREG Current Limit ILIM_VREG 50 95 140 mA

ADP5050 Data Sheet

Rev. B | Page 6 of 57

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

LOW INPUT VOLTAGE DETECTION

Low Input Voltage Threshold VLVIN-TH 4.07 4.236 4.39 V LVIN_TH[3:0] = 0000

10.05 10.25 10.4 V LVIN_TH[3:0] = 1100

Low Input Voltage Threshold Range 4.2 11.2 V I2C programmable (4-bit value)

THERMAL SHUTDOWN

Thermal Shutdown Threshold TSHDN 150 °C

Thermal Shutdown Hysteresis THYS 15 °C

THERMAL OVERHEAT WARNING

Thermal Overheat Threshold THOT 115 °C TEMP_TH[1:0] = 10

Overheat Threshold Range 105 125 °C I2C programmable (2-bit value)

Thermal Overheat Hysteresis THOT(HYS) 5 °C

BUCK REGULATOR SPECIFICATIONS

VIN = 12 V, VVREG = 5.1 V, fSW = 600 kHz for all channels, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C

for typical specifications, unless otherwise noted.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

CHANNEL 1 SYNC BUCK REGULATOR

FB1 Pin

Fixed Output Options VOUT1 0.85 1.60 V Fuse trim or I2C interface

(5-bit value)

Adjustable Feedback Voltage VFB1 0.800 V

Feedback Voltage Accuracy VFB1(DEFAULT ) −0.55 +0.55 % TJ = 25°C

−1.25 +1.0 % 0°C ≤ TJ ≤ 85°C

−1.5 +1.5 % −40°C ≤ TJ ≤ +125°C

Feedback Bias Current IFB1 0.1 µA Adjustable voltage

SW1 Pin

High-Side Power FET

On Resistance

RDSON(1H) 100 mΩ Pin-to-pin measurement

Current-Limit Threshold

TH(ILIM1)

3.50

4.4

5.28

ILIM1

= floating

1.91 2.63 3.08 A RILIM1 = 47 kΩ

4.95 6.44 7.48 A RILIM1 = 22 kΩ

Minimum On Time tMIN_ON1 117 155 ns fSW = 250 kHz to 1.4 MHz

Minimum Off Time tMIN_OFF1 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz

Low-Side Driver, DL1 Pin

Rising Time tRISING1 20 ns CISS = 1.2 nF

Falling Time tFALLING1 3.4 ns CISS = 1.2 nF

Sourcing Resistor tSOURCING1 10 Ω

Sinking Resistor tSINKING1 0.95 Ω

Error Amplifier (EA), COMP1 Pin

EA Transconductance gm1 310 470 620 µS

Soft Start

Soft Start Time tSS1 2.0 ms SS12 connected to VREG

Programmable Soft Start Range 2.0 8.0 ms

Hiccup Time tHICCUP1 7 × tSS1 ms

OUT

Discharge Switch On Resistance

DIS1

250

Ω

Data Sheet ADP5050

Rev. B | Page 7 of 57

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

CHANNEL 2 SYNC BUCK REGULATOR

FB2 Pin

Fixed Output Options VOUT2 3.3 5.0 V Fuse trim or I2C interface

(3-bit value)

Adjustable Feedback Voltage VFB2 0.800 V

Feedback Voltage Accuracy VFB2(DE FAULT ) −0.55 +0.55 % TJ = 25°C

−1.25 +1.0 % 0°C ≤ TJ ≤ 85°C

−1.5 +1.5 % −40°C ≤ TJ ≤ +125°C

Feedback Bias Current IFB2 0.1 µA Adjustable voltage

SW2 Pin

High-Side Power FET

On Resistance

DSON(2H)

110

mΩ

Pin-to-pin measurement

Current-Limit Threshold ITH(ILIM2) 3.50 4.4 5.28 A RILIM2 = floating

1.91 2.63 3.08 A RILIM2 = 47 kΩ

4.95 6.44 7.48 A RILIM2 = 22 kΩ

Minimum On Time tMIN_ON2 117 155 ns fSW = 250 kHz to 1.4 MHz

Minimum Off Time tMIN_OFF2 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz

Low-Side Driver, DL2 Pin

Rising Time tRISING2 20 ns CISS = 1.2 nF

Falling Time tFALLING2 3.4 ns CISS = 1.2 nF

Sourcing Resistor tSOURCING2 10 Ω

Sinking Resistor

SINKING2

0.95

Ω

Error Amplifier (EA), COMP2 Pin

EA Transconductance gm2 310 470 620 µS

Soft Start

Soft Start Time tSS2 2.0 ms SS12 connected to VREG

Programmable Soft Start Range 2.0 8.0 ms

Hiccup Time tHICCUP2 7 × tSS2 ms

COUT Discharge Switch On Resistance RDIS2 250 Ω

CHANNEL 3 SYNC BUCK REGULATOR

FB3 Pin

Fixed Output Options VOUT3 1.20 1.80 V Fuse trim or I2C interface

(3-bit value)

Adjustable Feedback Voltage VFB3 0.800 V

Feedback Voltage Accuracy

FB3(DE FAULT )

−0.55

+0.55

= 25°C

−1.25

+1.0

0°C ≤ T

≤ 85°C

−1.5 +1.5 % −40°C ≤ TJ ≤ +125°C

Feedback Bias Current IFB3 0.1 µA Adjustable voltage

SW3 Pin

High-Side Power FET

On Resistance

RDSON(3H) 225 mΩ Pin-to-pin measurement

Low-Side Power FET

On Resistance

RDSON(3L) 150 mΩ Pin-to-pin measurement

Current-Limit Threshold ITH(ILIM3) 1.7 2.2 2.55 A

Minimum On Time tMIN_ON3 90 120 ns fSW = 250 kHz to 1.4 MHz

Minimum Off Time tMIN_OFF3 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz

Error Amplifier (EA), COMP3 Pin

EA Transconductance gm3 310 470 620 µS

Soft Start

Soft Start Time tSS3 2.0 ms SS34 connected to VREG

Programmable Soft Start Range 2.0 8.0 ms

Hiccup Time tHICCUP3 7 × tSS3 ms

OUT

Discharge Switch On Resistance

DIS3

250

Ω

ADP5050 Data Sheet

Rev. B | Page 8 of 57

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

CHANNEL 4 SYNC BUCK REGULATOR

FB4 Pin

Fixed Output Options VOUT4 2.5 5.5 V Fuse trim or I2C interface

(5-bit value)

Adjustable Feedback Voltage VFB4 0.800 V

Feedback Voltage Accuracy VFB4(DE FAULT ) −0.55 +0.55 % TJ = 25°C

−1.25 +1.0 % 0°C ≤ TJ ≤ 85°C

−1.5 +1.5 % −40°C ≤ TJ ≤ +125°C

Feedback Bias Current IFB4 0.1 µA

SW4 Pin

High-Side Power FET

On Resistance

DSON(4H)

225

mΩ

Pin-to-pin measurement

Low-Side Power FET

On Resistance

RDSON(4L) 150 mΩ Pin-to-pin measurement

Current-Limit Threshold ITH(ILIM4) 1.7 2.2 2.55 A

Minimum On Time tMIN_ON4 90 120 ns fSW = 250 kHz to 1.4 MHz

Minimum Off Time tMIN_OFF4 1/9 × tSW ns fSW = 250 kHz to 1.4 MHz

Error Amplifier (EA), COMP4 Pin

EA Transconductance gm4 310 470 620 µS

Soft Start

Soft Start Time

SS4

2.0

SS34 connected to VREG

Programmable Soft Start Range

2.0

8.0

Hiccup Time tHICCUP4 7 × tSS4 ms

COUT Discharge Switch On Resistance RDIS4 250 Ω

LDO REGULATOR SPECIFICATIONS

VIN5 = (VOUT5 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; CIN = COUT = 1 µF; TJ = −40°C to +125°C for minimum and maximum

specifications, and TA = 25°C for typical specifications, unless otherwise noted.

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE 1.7 5.5 V PVIN5 pin

OPERATIONAL SUPPLY CURRENT

Bias Current for LDO Regulator 30 130 µA IOUT5 = 200 µA

60 170 µA IOUT5 = 10 mA

145 320 µA IOUT5 = 200 mA

VOLTAGE FEEDBACK (FB5 PIN)

Adjustable Feedback Voltage 0.500 V

Feedback Voltage Accuracy −1.0 +1.0 % TJ = 25°C

−1.6

+1.6

0°C ≤ T

≤ 85°C

−2.0 +2.0 % −40°C ≤ TJ ≤ +125°C

DROPOUT VOLTAGE

OUT5

= 200 mA

VOUT5 = 3.3 V

100 mV VOUT5 = 2.5 V

180 mV VOUT5 = 1.5 V

CURRENT-LIMIT THRESHOLD 250 510 mA Specified from the output voltage drop

to 90% of the specified typical value

OUTPUT NOISE

µV rms

10 Hz to 100 kHz, V

PVIN5

= 5 V, VOUT5 = 1.8 V

POWER SUPPLY REJECTION RATIO VPVIN5 = 5 V, VOUT5 = 1.8 V, IOUT5 = 1 mA

77 dB 10 kHz

66 dB 100 kHz

Data Sheet ADP5050

Rev. B | Page 9 of 57

I2C INTERFACE TIMING SPECIFICATIONS

TA = 25°C, VVDD = 3.3 V, VVDDIO = 3.3 V, unless otherwise noted.

Table 5.

Parameter Min Typ Max Unit Description

fSCL 400 kHz SCL clock frequency

tHIGH 0.6 µs SCL high time

tLOW 1.3 µs SCL low time

tSU,DAT 100 ns Data setup time

tHD,DAT 0 0.9 µs Data hold time1

tSU,STA 0.6 µs Setup time for a repeated start condition

tHD,STA 0.6 µs Hold time for a start or repeated start condition

tBUF 1.3 µs Bus free time between a stop condition and a start condition

tSU,STO 0.6 µs Setup time for a stop condition

tR 20 + 0.1CB2 300 ns Rise time of SCL and SDA

tF 20 + 0.1CB2 300 ns Fall time of SCL and SDA

tSP 0 50 ns Pulse width of suppressed spike

CB2 400 pF Capacitive load for each bus line

1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the

SCL falling edge.

2 CB is the total capacitance of one bus line in picofarads (pF).

Timing Diagram

S SP

S = START CONDITION

Sr = REP E ATED S TART CONDI TION

P = STOP CONDITION

SCL

SDA

HD,DAT

SU,DAT

HD,STA

SU,STA

SU,STO

HIGH

LOW

BUF

10899-102

Figure 3. I2C Interface Timing Diagram

ADP5050 Data Sheet

Rev. B | Page 10 of 57

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

PVIN1 to PGND −0.3 V to +18 V

PVIN2 to PGND

−0.3 V to +18 V

PVIN3 to PGND3 −0.3 V to +18 V

PVIN4 to PGND4 −0.3 V to +18 V

PVIN5 to GND −0.3 V to +6.5 V

SW1 to PGND −0.3 V to +18 V

SW2 to PGND −0.3 V to +18 V

SW3 to PGND3 −0.3 V to +18 V

SW4 to PGND4 −0.3 V to +18 V

PGND to GND −0.3 V to +0.3 V

PGND3 to GND −0.3 V to +0.3 V

PGND4 to GND −0.3 V to +0.3 V

BST1 to SW1 −0.3 V to +6.5 V

BST2 to SW2 −0.3 V to +6.5 V

BST3 to SW3 −0.3 V to +6.5 V

BST4 to SW4 −0.3 V to +6.5 V

DL1 to PGND −0.3 V to +6.5 V

DL2 to PGND −0.3 V to +6.5 V

SS12, SS34 to GND

−0.3 V to +6.5 V

EN1, EN2, EN3, EN4, EN5 to GND −0.3 V to +6.5 V

VREG to GND −0.3 V to +6.5 V

SYNC/MODE to GND −0.3 V to +6.5 V

VOUT5, FB5 to GND −0.3 V to +6.5 V

RT to GND −0.3 V to +3.6 V

INT, PWRGD to GND −0.3 V to +6.5 V

FB1, FB2, FB3, FB4 to GND1 −0.3 V to +3.6 V

FB2 to GND2 −0.3 V to +6.5 V

FB4 to GND2 −0.3 V to +7 V

COMP1, COMP2, COMP3, COMP4

to GND

−0.3 V to +3.6 V

VDD, VDDIO to GND −0.3 V to +3.6 V

SCL, SDA −0.3 V to VDDIO + 0.3 V

Storage Temperate Range −65°C to +150°C

Operational Junction Temperature

Range

−40°C to +125°C

1 This rating applies to the adjustable output voltage models of the ADP5050.

2 This rating applies to the fixed output voltage models of the ADP5050.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

48-Lead LFCSP 27.87 2.99 °C/W

ESD CAUTION

Data Sheet ADP5050

Rev. B | Page 11 of 57

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PVIN1

SW1

4SW1

5BST1

6DL1

7PGND

PVIN2 23EN2 22COMP2 21FB2 20PWRGD 19SCL 18SDA 17VDDIO 16FB4 15COMP4 14EN4 13INT

44 VREG

45 FB3

46 COMP3

47 SS34

48 EN3

43 SYNC/MODE

42 VDD

41 RT

40 FB1

39 COMP1

38 SS12

37 EN1

TOP

VIEW

(No t t o Scal e)

ADP5050

BST4 26

PGND4 27

SW4 28

PVIN4 29

PVIN5 30

VOUT5 31

FB5 32

EN5 33

PVIN3 34

SW3 35

PGND3 36

BST3

NOTES

1. THE EXPOSED PAD MUS T BE CONNECTED AND

SOLDERED TOAN EX TERNAL GROUND PLANE.

8DL2

9BST2

10 SW2

11 SW2

12 PVIN2

10899-002

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 BST3 High-Side FET Driver Power Supply for Channel 3.

2 PGND3 Power Ground for Channel 3.

3 SW3 Switching Node Output for Channel 3.

4 PVIN3 Power Input for Channel 3. Connect a bypass capacitor between this pin and ground.

5 EN5 Enable Input for Channel 5. An external resistor divider can be used to set the turn-on threshold.

FB5

Feedback Sensing Input for Channel 5.

7 VOUT5 Power Output for Channel 5.

8 PVIN5 Power Input for Channel 5. Connect a bypass capacitor between this pin and ground.

9 PVIN4 Power Input for Channel 4. Connect a bypass capacitor between this pin and ground.

10 SW4 Switching Node Output for Channel 4.

11 PGND4 Power Ground for Channel 4.

12 BST4 High-Side FET Driver Power Supply for Channel 4.

13 INT Interrupt Output on Fault Condition. Open-drain output port.

14 EN4 Enable Input for Channel 4. An external resistor divider can be used to set the turn-on threshold.

15 COMP4 Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.

16 FB4 Feedback Sensing Input for Channel 4.

VDDIO

Power Supply for the I

C Interface.

18 SDA Data Input/Output for the I2C Interface. Open-drain I/O port.

19 SCL Clock Input for the I2C Interface.

20 PWRGD Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels.

This pin can be programmed by the factory to set the I2C address of the part; the I2C address setting function

replaces the power-good function on this pin. For more information, see the I2C Addresses section.

21 FB2 Feedback Sensing Input for Channel 2.

22 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.

23 EN2 Enable Input for Channel 2. An external resistor divider can be used to set the turn-on threshold.

24, 25 PVIN2 Power Input for Channel 2. Connect a bypass capacitor between this pin and ground.

26, 27

SW2

Switching Node Output for Channel 2.

BST2

High-Side FET Driver Power Supply for Channel 2.

29 DL2 Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current-limit

threshold for Channel 2.

ADP5050 Data Sheet

Rev. B | Page 12 of 57

Pin No. Mnemonic Description

30 PGND Power Ground for Channel 1 and Channel 2.

31 DL1 Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-limit

threshold for Channel 1.

32 BST1 High-Side FET Driver Power Supply for Channel 1.

33, 34 SW1 Switching Node Output for Channel 1.

35, 36 PVIN1 Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass

capacitor between this pin and ground.

37 EN1 Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold.

38 SS12 Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and

Channel 2 (see the Soft Start section). This pin is also used to configure parallel operation of Channel 1 and

Channel 2 (see the Parallel Operation section).

39 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.

40 FB1 Feedback Sensing Input for Channel 1.

41 RT Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 1.4 MHz. For more

information, see the Oscillator section.

42 VDD Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.

43 SYNC/MODE Synchronization Input/Output (SYNC). To synchronize the switching frequency of the part to an external clock,

connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. This pin can also be configured

as a synchronization output using the I2C interface or by factory fuse.

Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, each channel operates

in forced PWM or automatic PWM/PSM mode, as specified by the PSMx_ON bits in Register 6. When this pin is

logic low, all channels operate in automatic PWM/PSM mode, and the PSMx_ON settings in Register 6 are ignored.

44 VREG Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground.

45 FB3 Feedback Sensing Input for Channel 3.

46 COMP3 Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground.

47 SS34 Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and

Channel 4 (see the Soft Start section).

48 EN3 Enable Input for Channel 3. An external resistor divider can be used to set the turn-on threshold.

EPAD Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane.

Data Sheet ADP5050

Rev. B | Page 13 of 57

TYPICAL PERFORMANCE CHARACTERISTICS

100

0 1 2 3 4

EFFICIENCY (%)

OUT

(A)

OUT

= 1.2V

OUT

=1.5V

OUT

= 1.8V

OUT

= 2.5V

OUT

= 3.3V

OUT

= 5.0V

10899-003

Figure 5. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,

FPWM Mode

100

01234

EFFICIENCY (%)

OUT

(A)

OUT

= 1.2V

OUT

= 1.5V

OUT

= 1.8V

OUT

= 2.5V

OUT

= 3.3V

10899-004

Figure 6. Channel 1/Channel 2 Efficiency Curve, VIN = 5.0 V, fSW = 600 kHz,

FPWM Mode

100

01234

EFFICIENCY (%)

OUT

(A)

=1.0MHz

=600kHz

=300kHz

10899-005

Figure 7. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V,

FPWM Mode

100

0.01 0.1 110

EFFICIENCY (%)

OUT

(A)

OUT

= 1.2V, FPWM

OUT

= 1.2V, AUTO PWM/PSM

OUT

= 1.8V, FPWM

OUT

= 1.8V, AUTO PWM/ PSM

OUT

=3.3V, FPWM

OUT

=3.3V, AUTO PWM/ PSM

10899-006

Figure 8. Channel 1/Channel 2 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,

FPWM and Automatic PWM/PSM Modes

100

00.2 0.4 0.6 0.8 1.0 1.2

EFFICIENCY (%)

IOUT (A)

OUT

=1.2V

OUT

= 1.5V

OUT

= 1.8V

OUT

= 2.5V

OUT

=3.3V

OUT

.0V

10899-007

Figure 9. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,

FPWM Mode

100

00.2 0.4 0.6 0.8 1.0 1.2

EFFICIENCY (%)

IOUT (A)

OUT

= 1.2V

OUT

= 1.5V

OUT

= 1.8V

OUT

= 2.5V

OUT

= 3.3V

10899-008

Figure 10. Channel 3/Channel 4 Efficiency Curve, VIN = 5.0 V, fSW = 600 kHz,

FPWM Mode

ADP5050 Data Sheet

Rev. B | Page 14 of 57

100

00.2 0.4 0.6 0.8 1.0 1.2

EFFICIENCY (%)

IOUT (A)

=1.0MHz

=600kHz

=300kHz

10899-009

Figure 11. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, VOUT = 1.8 V,

FPWM Mode

100

0.01 0.1 1 2

EFFICIENCY (%)

IOUT (A)

OUT

= 1.2V, FPWM

OUT

= 1.2V, AUTO PWM/PSM

OUT

= 1.8V, FPWM

OUT

= 1.8V, AUTO PWM/ PSM

OUT

=3.3V, FPWM

OUT

=3.3V, AUTO PWM/ PSM

10899-010

Figure 12. Channel 3/Channel 4 Efficiency Curve, VIN = 12 V, fSW = 600 kHz,

FPWM and and Automatic PWM/PSM Modes

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0 1 2 3 4

LOAD REG UL ATION (%)

OUT

(A)

10899-011

Figure 13. Channel 1 Load Regulation, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz,

FPWM Mode

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0

LI NE RE GULATION (%)

INPUT VOLTAGE (V)

10899-012

Figure 14. Channel 1 Line Regulation, VOUT = 3.3 V, IOUT = 4 A,

fSW = 600 kHz, FPWM Mode

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

00.2 0.4 0.6 0.8 1.0 1.2

LOAD REG UL ATION (%)

OUT

(A)

10899-013

Figure 15. Channel 3 Load Regulation, VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz,

FPWM Mode

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0

LINE REGULATION (%)

INPUT VOLTAGE (V)

10899-014

Figure 16. Channel 3 Line Regulation, VOUT = 3.3 V, IOUT = 1 A,

fSW = 600 kHz, FPWM Mode

Data Sheet ADP5050

Rev. B | Page 15 of 57

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

–50 –20 10 40 70 100 130

FE EDBACK V OLTAGE ACCURACY (%)

TEMPERAT URE ( °C)

10899-015

Figure 17. 0.8 V Feedback Voltage Accuracy vs. Temperature

for Channel 1, Adjustable Output Model

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

0510 15 20 25 30 35

OUTPUT VOLTAGE E RROR (%)

VID CODE

10899-016

VID1

VID2

VID3

VID4

Figure 18. Output Voltage Error vs. VID Code, Adjustable Output Model

550

600

650

700

750

800

850

–50 –20 10 40 70 100 130

FREQUENCY (kHz)

TEMPERAT URE ( °C)

10899-017

Figure 19. Frequency vs. Temperature, VIN = 12 V

3.0

3.5

4.0

4.5

5.0

5.5

6.0

–50 025–25 50 75 125100 150

QUI E S CE NT CURRENT (mA)

TEMPERAT URE ( °C)

10899-018

Figure 20. Quescient Current vs. Temperature (Includes PVIN1, PVIN2,

PVIN3, and PVIN4)

SHUT DO WN CURRENT (µA)

TEMPERAT URE ( °C)

–50 025–25 50 75 125100 150

VIN = 4.5V

VIN = 7.0V

VIN = 12V

VIN = 15V

10899-019

Figure 21. Shutdown Current vs. Temperature (EN1, EN2, EN3,

EN4, and EN5 Low)

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

–50 –20 10 40 70 100 130

UVL O THRES HOL D ( V )

TEMPERAT URE ( °C)

RISING

FALLING

10899-020

Figure 22. UVLO Threshold vs. Temperature

ADP5050 Data Sheet

Rev. B | Page 16 of 57

46810 12 14 16

CURRENT LI M IT ( A)

INPUT VOLTAGE (V)

ILIM

= 22kΩ

ILIM

= OPEN

ILIM

= 47kΩ

10899-021

Figure 23. Channel 1/Channel 2 Current Limit vs. Input Voltage

100

120

140

160

180

200

–50 –20 10 40 70 100 130

MINIMUM ON TIME (n s)

TEMPERAT URE ( °C)

CH1/CH2

CH3/CH4

10899-022

Figure 24. Minimum On Time vs. Temperature

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

OUT

1mA

OUT

10mA

OUT

50mA

OUT

100mA

OUT

150mA

OUT

200mA

10899-023

Figure 25. Channel 5 (LDO Regulator) Line Regulation over Output Load

0.01

0.1

100

10 100 1k 10k 100k

NOISE (µV/√Hz)

FREQUENCY ( Hz )

OUT

= 1.2V

OUT

= 1.8V

OUT

= 3.3V

OUT

= 2.5V

10899-024

Figure 26. Channel 5 (LDO Regulator) Output Noise Spectrum,

VIN = 5 V, COUT = 1 µF, IOUT = 10 mA

100

120

140

160

180

110 100

RMS NOISE (µV)

OUT

(mA)

OUT

= 1.2V

OUT

= 1.8V

OUT

= 3.3V

OUT

= 2.5V

10899-025

Figure 27. Channel 5 (LDO Regulator) Output Noise vs. Output Load,

VIN = 5 V, COUT = 1 µF

–120

–100

–80

–60

–40

–20

10 100 1k 10k 100k 1M 10M

PSRR (dB)

FREQUENCY ( Hz )

IOUT = 1mA

IOUT = 10mA

IOUT = 50mA

IOUT = 100mA

IOUT = 150mA

IOUT = 200mA

10899-026

Figure 28. Channel 5 (LDO Regulator) PSRR over Output Load,

VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF

Data Sheet ADP5050

Rev. B | Page 17 of 57

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

10 100 1k 10k 100k 1M 10M

PSRR (dB)

FREQUENCY ( Hz )

PVIN5 = 4.0V; I

OUT

= 1mA

PVIN5 = 3.6V, I

OUT

= 1mA

PVIN5 = 4.0V, I

OUT

= 100mA

PVIN5 = 3.6V, I

OUT

= 100mA

PVIN5 = 4.0V, I

OUT

= 200mA

PVIN5 = 3.6V, I

OUT

= 200mA

10899-027

Figure 29. Channel 5 (LDO Regulator) PSRR over Various Loads

and Dropout Voltages, VOUT = 3.3 V, COUT = 1 µF

CH1 5.00V CH2 10.0mV

M1.00µs A CH1 7. 40V

VOUT

10899-028

Figure 30. Steady State Waveform at Heavy Load, VIN = 12 V, VOUT = 3.3 V,

IOUT = 3 A, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 2, FPWM Mode

10899-029

CH1 5.00V CH2 50.0mVBWM100µs A CH1 11.0mV

VOUT

Figure 31. Steady State Waveform at Light Load, VIN = 12 V, VOUT = 3.3 V,

IOUT = 30 mA, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 2,

Automatic PWM/PSM Mode

CH1 50.0mVBWCH4 2.00A Ω M100µs A CH1 –22.0mV

VOUT

IOUT

10899-030

Figure 32. Channel 1/Channel 2 Load Transient, 1 A to 4 A, VIN = 12 V,

VOUT = 3.3 V, fSW = 600 kHz, L = 2.2 µH, COUT = 47 µF × 2

CH3 2.00A Ω

CH4 2.00A Ω

CH2 100mV

M100µs A CH2 –56.0mV

OUT

OUT2

OUT1

10899-031

Figure 33. Load Transient, Channel 1/Channel 2 Parallel Output, 0 A to 6 A,

VIN = 12 V, VOUT = 3.3 V, fSW = 600 kHz, L = 4.7 µH, COUT = 47 µF × 4

CH1 500mVBWCH2 5.00V

CH3 5.00VBWCH4 2.00A Ω

M1.00ms A CH1 650mV

VOUT

IOUT

PWRGD

10899-032

Figure 34. Channel 1/Channel 2 Soft Start with 4 A Resistance Load,

VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2

ADP5050 Data Sheet

Rev. B | Page 18 of 57

CH3 1.00V

CH1 10.0V

CH4 1.00A Ω

CH2 5.00V

M400µs A CH2 2.80V

10899-033

OUT

Figure 35. Startup with Precharged Output, VIN = 12 V, VOUT = 3.3 V

CH3 5.00V BW

CH1 500mV BWCH4 5.00A Ω BW

CH2 5.00V BWM10.0ms A CH1 650mV

10899-034

VOUT

IOUT

PWRGD

Figure 36. Channel 1/Channel 2 Shutdown with Active Output Discharge,

VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2

CH1 500mV

CH4 5.00A Ω

CH2 10.00V

M10.0ms A CH1 970mV

10899-135

OUT

Figure 37. Short-Circuit Protection Entry, VIN = 12 V, VOUT = 1.2 V,

fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2

CH1 500mV BWCH4 5.00A Ω BW

CH2 10.0V BWM10.0ms A CH1 970mV

10899-136

OUT

Figure 38. Short-Circuit Protection Recovery, VIN = 12 V, VOUT = 1.2 V,

fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2

CH2 200mV

M200µs A CH2 1.21V

10899-137

OUT

Figure 39. Channel 1 Dynamic Voltage Scaling (DVS) from 1.1 V to 1.3 V,

62.5 µs Interval, VIN = 12 V, IOUT = 4 A, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2

CH2 200mV

M200µs A CH2 1.18V

10899-138

OUT

Figure 40. Channel 1 Dynamic Voltage Scaling (DVS) from 1.3 V to 1.1 V,

62.5 µs Interval, VIN = 12 V, IOUT = 4 A, fSW = 600 kHz, L = 1 µH, COUT = 47 µF × 2

Data Sheet ADP5050

Rev. B | Page 19 of 57

THEORY OF OPERATION

The ADP5050 is a micropower management unit that combines

four high performance buck regulators with a 200 mA low dropout

(LDO) regulator in a 48-lead LFCSP package to meet demanding

performance and board space requirements. The device enables

direct connection to high input voltages up to 15 V with no pre-

regulators to make applications simpler and more efficient.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In pulse-width modulation (PWM) mode, the buck regulators

in the ADP5050 operate at a fixed frequency; this frequency is

set by an internal oscillator that is programmed by the RT pin.

At the start of each oscillator cycle, the high-side MOSFET turns

on and sends a positive voltage across the inductor. The inductor

current increases until the current-sense signal exceeds the peak

inductor current threshold that turns off the high-side MOSFET;

this threshold is set by the error amplifier output.

During the high-side MOSFET off time, the inductor current

decreases through the low-side MOSFET until the next oscillator

clock pulse starts a new cycle. The buck regulators in the ADP5050

regulate the output voltage by adjusting the peak inductor current

threshold.

PSM Mode

To achieve higher efficiency, the buck regulators in the ADP5050

smoothly transition to variable frequency power save mode (PSM)

operation when the output load falls below the PSM current

threshold. When the output voltage falls below regulation, the

buck regulator enters PWM mode for a few oscillator cycles until

the voltage increases to within regulation. During the idle time

between bursts, the MOSFET turns off, and the output capacitor

supplies all the output current.

The PSM comparator monitors the internal compensation node,

which represents the peak inductor current information. The

average PSM current threshold depends on the input voltage

(VIN), the output voltage (VOUT), the inductor, and the output

capacitor. Because the output voltage occasionally falls below

regulation and then recovers, the output voltage ripple in PSM

operation is larger than the ripple in the forced PWM mode of

operation under light load conditions.

Forced PWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in

PWM mode using the SYNC/MODE pin and the I2C interface.

In forced PWM (FPWM) mode, the regulator continues to

operate at a fixed frequency even when the output current is

below the PWM/PSM threshold. In PWM mode, efficiency is

lower compared to PSM mode under light load conditions. The

low-side MOSFET remains on when the inductor current falls

to less than 0 A, causing the ADP5050 to enter continuous

conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM/PSM mode using the SYNC/MODE pin and the I2C

interface. In automatic PWM/PSM mode, the buck regulators

operate in either PWM mode or PSM mode, depending on the

output current. When the average output current falls below the

PWM/PSM threshold, the buck regulator enters PSM mode

operation; in PSM mode, the regulator operates with a reduced

switching frequency to maintain high efficiency. The low-side

MOSFET turns off when the output current reaches 0 A,

causing the regulator to operate in discontinuous mode (DCM).

The user can alternate between forced PWM (FPWM) mode

and automatic PWM/PSM mode during operation. The flexible

configuration capability during operation of the device enables

efficient power management.

When a logic high level is applied to the SYNC/MODE pin (or

when SYNC/MODE is configured as a clock input or output),

the operational mode of each channel is set by the PSMx_ON

bit in Register 6. A value of 0 for the PSMx_ON bit configures

the channel for forced PWM mode; a value of 1 configures the

channel for automatic PWM/PSM mode.

When a logic low level is applied to the SYNC/MODE pin,

the operational mode of all four buck regulators is automatic

PWM/PSM mode, and the settings of the PSMx_ON bits in

Table 9 describes the function of the SYNC/MODE pin in

setting the operational mode of the device.

Table 9. Configuring the Mode of Operation Using the

SYNC/MODE Pin

SYNC/MODE Pin Mode of Operation for Each Channel

High Specified by the PSMx_ON bit setting

in Register 6 (0 = forced PWM mode;

1 = automatic PWM/PSM mode)

Clock Input/Output Specified by the PSMx_ON bit setting

in Register 6 (0 = forced PWM mode;

1 = automatic PWM/PSM mode)

Low Automatic PWM/PSM mode (PSMx_ON

bit settings in Register 6 are ignored)

For example, with the SYNC/MODE pin high, write 1 to the

PSM4_ON bit in Register 6 to configure automatic PWM/PSM

mode operation for Channel 4, and write 0 to the PSM1_ON,

PSM2_ON, and PSM3_ON bits to configure forced PWM mode

for Channel 1, Channel 2, and Channel 3.

ADP5050 Data Sheet

Rev. B | Page 20 of 57

ADJUSTABLE AND FIXED OUTPUT VOLTAGES

The ADP5050 provides adjustable and fixed output voltage

settings via the I2C interface or factory fuse. For the adjustable

output settings, use an external resistor divider to set the desired

output voltage via the feedback reference voltage (0.8 V for

Channel 1 to Channel 4, and 0.5 V for Channel 5).

For the fixed output settings, the feedback resistor divider is

built into the ADP5050, and the feedback pin (FBx) must be

tied directly to the output. Each buck regulator channel can be

programmed for a specific output voltage range using the VIDx

bits in Register 2 to Register 4. Table 10 lists the fixed output

voltage ranges configured by the VIDx bits.

Table 10. Fixed Output Voltage Ranges Set by the VIDx Bits

Channel Fixed Output Voltage Range Set by the VIDx Bits

Channel 1 0.85 V to 1.6 V in 25 mV steps

Channel 2 3.3 V to 5.0 V in 300 mV or 200 mV steps

Channel 3 1.2 V to 1.8 V in 100 mV steps

Channel 4

2.5 V to 5.5 V in 100 mV steps

The output range can also be programmed by factory fuse. If

a different output voltage range is required, contact your local

Analog Devices, Inc., sales or distribution representative.

DYNAMIC VOLTAGE SCALING (DVS)

The ADP5050 provides a dynamic voltage scaling (DVS) function

for Channel 1 and Channel 4; these outputs can be programmed

in real time via the I2C interface (Register 5, DVS_CFG). The

DVS_CFG register is used to enable DVS and to set the step

interval during the transition (see Table 29).

It is recommended that the user enable the DVS function before

setting the output voltage for Channel 1 or Channel 4. (The out-

put voltage for Channel 1 is set using the VID1 bits in Register 2;

the output voltage for Channel 4 is set using the VID4 bits in

voltage changes rapidly to the next target voltage, which can

result in problems such as a PWRGD failure or OVP and OCP

events. Figure 41 shows the dynamic voltage scaling function.

OUTPUT

NEW V I D CODE

OL D V ID CO DE

OLD VID NEW VID

VIDx

VID FOR

CH1 OR CH4

DVSx_I NTVAL SE TT ING

25mV FOR CH1

(100mV FOR CH4)

10899-035

Figure 41. Dynamic Voltage Scaling

During the DVS transition period, the regulator is forced into

PWM mode operation, and OVP latch-off, SCP latch-off, and

hiccup protection are masked.

INTERNAL REGULATORS (VREG AND VDD)

The internal VREG regulator in the ADP5050 provides a stable

5.1 V power supply for the bias voltage of the MOSFET drivers.

The internal VDD regulator in the ADP5050 provides a stable

3.3 V power supply for internal control circuits. Connect a 1.0 µF

ceramic capacitor between VREG and ground, and connect

another 1.0 µF ceramic capacitor between VDD and ground.

The internal VREG and VDD regulators are active as long as

PVIN1 is available.

The internal VREG regulator can provide a total load of 95 mA

including the MOSFET driving current, and it can be used as

an always alive 5.1 V power supply for a small system current

demand. The current-limit circuit is included in the VREG

regulator to protect the circuit when the part is heavily loaded.

The VDD regulator is for internal circuit use and is not recom-

mended for other purposes.

SEPARATE SUPPLY APPLICATIONS

The ADP5050 supports separate input voltages for the four buck

regulators. This means that the input voltages for the four buck

regulators can be connected to different supply voltages.

The PVIN1 voltage provides the power supply for the internal

regulators and the control circuitry. Therefore, if the user plans

to use separate supply voltages for the buck regulators, the PVIN1

voltage must be above the UVLO threshold before the other

channels begin to operate.

Precision enabling can be used to monitor the PVIN1 voltage

and to delay the startup of the outputs to ensure that PVIN1 is

high enough to support the outputs in regulation. For more

information, see the Precision Enabling section.

The ADP5050 supports cascading supply operation for the four

buck regulators. As shown in Figure 42, PVIN2, PVIN3, and

PVIN4 are powered from the Channel 1 output. In this config-

uration, the Channel 1 output voltage must be higher than the

UVLO threshold for PVIN2, PVIN3, and PVIN4.

PVIN1 BUCK 1

BUCK 2

VOUT1

PVIN2

PVIN4 VOUT2 TO VOUT4

VIN

10899-036

Figure 42. Cascading Supply Application

Data Sheet ADP5050

Rev. B | Page 21 of 57

LOW-SIDE DEVICE SELECTION

The buck regulators in Channel 1 and Channel 2 integrate 4 A

high-side power MOSFETs and low-side MOSFET drivers. The

N-channel MOSFETs selected for use with the ADP5050 must be

able to work with the synchronized buck regulators. In general,

a low RDSON N-channel MOSFET can be used to achieve higher

efficiency; dual MOSFETs in one package (for both Channel 1

and Channel 2) are recommended to save space on the PCB. For

more information, see the Low-Side Power Device Selection

section.

BOOTSTRAP CIRCUITRY

Each buck regulator in the ADP5050 has an integrated bootstrap

regulator. The bootstrap regulator requires a 0.1 µF ceramic capac-

itor (X5R or X7R) between the BSTx and SWx pins to provide

the gate drive voltage for the high-side MOSFET.

ACTIVE OUTPUT DISCHARGE SWITCH

Each buck regulator in the ADP5050 integrates a discharge switch

from the switching node to ground. This switch is turned on when

its associated regulator is disabled, which helps to discharge the

output capacitor quickly. The typical value of the discharge switch

is 250 Ω for Channel 1 to Channel 4.

The discharge switch function can be enabled or disabled for each

channel by factory fuse or by using the I2C interface (Register 6,

OPT_CFG).

PRECISION ENABLING

The ADP5050 has an enable control pin for each regulator,

including the LDO regulator. The enable control pin (ENx)

features a precision enable circuit with a 0.8 V reference voltage.

When the voltage at the ENx pin is greater than 0.8 V, the regulator

is enabled. When the voltage at the ENx pin falls below 0.725 V,

the regulator is disabled. An internal 1 MΩ pull-down resistor

prevents errors if the ENx pin is left floating.

The precision enable threshold voltage allows easy sequencing

of channels within the part, as well as sequencing between the

ADP5050 and other input/output supplies. The ENx pin can also

be used as a programmable UVLO input using a resistor divider

(see Figure 43). For more information, see the Programming the

UVLO Input section.

0.8V

DEGLITCH

TIMER

INTERNAL

ENABLE ENx R1

1MΩ

INPUT/OUTPUT

VOLTAGE

ADP5050

10899-037

Figure 43. Precision Enable Diagram for One Channel

In addition to the ENx pins, the I2C interface (Register 1,

PCTRL) can also be used to enable and disable each channel. The

on/off status of a channel is controlled by the I2C enable bit for

the channel (CHx_ON) and the external hardware enable pin for

the channel (logical AND).

The default value of the I2C enable bit (CHx_ON = 1) specifies

that the channel enable is controlled by the external hardware

enable pin. Pulling the external ENx pin low resets the channel

and forces the corresponding CHx_ON bit to the default value, 1,

to support another startup when the external ENx pin is pulled

high again.

OSCILLATOR

The switching frequency (fSW) of the ADP5050 can be set to a

value from 250 kHz to 1.4 MHz by connecting a resistor from

the RT pin to ground. The value of the RT resistor can be

calculated as follows:

RRT (kΩ) = [14,822/fSW (kHz)]1.081

Figure 44 shows the typical relationship between the switching

frequency (fSW) and the RT resistor. The adjustable frequency

allows users to make decisions based on the trade-off between

efficiency and solution size.

1.6M

1.4M

1.2M

1.0M

800k

FREQUENCY (Hz)

600k

400k

200k

0020 40

RT RES ISTOR (kΩ)

60 80

10899-044

Figure 44. Switching Frequency vs. RT Resistor

For Channel 1 and Channel 3, the frequency can be set to half

the master switching frequency set by the RT pin. This setting

is configured using Register 8 (Bit 7 for Channel 3, and Bit 6 for

Channel 1). If the master switching frequency is less than 250 kHz,

this halving of the frequency for Channel 1 or Channel 3 is not

recommended.

ADP5050 Data Sheet

Rev. B | Page 22 of 57

Phase Shift

By default, the phase shift between Channel 1 and Channel 2 and

between Channel 3 and Channel 4 is 180° (see Figure 45). This

value provides the benefits of out-of-phase operation by reduc-

ing the input ripple current and lowering the ground noise.

CH2

CH1

(½ f

OPTIONAL)

CH4

180° P HAS E S HIFT

0° RE FERENCE

90° P HAS E S HIFT

270° P HAS E S HIFT

0°, 90° ,180° , OR 270°

ADJUSTABLE

CH3

(½ f

OPTIONAL)

10899-040

Figure 45. Phase Shift Diagram, Four Buck Regulators

For Channel 2 to Channel 4, the phase shift with respect to

Channel 1 can be set to 0°, 90°, 180°, or 270° using Register 8,

SW_CFG (see Figure 46). When parallel operation of Channel 1

and Channel 2 is configured, the switching frequency of Channel 2

is locked to a 180° phase shift with respect to Channel 1.

CH3 10.0V BW

CH1 10.0V BWCH4 10. 0V BW

CH2 10.0V BWM400ns A CH1 7. 40V

10899-146

SW1

SW2

SW3

SW4

Figure 46. I2C Configurable 90° Phase Shift Waveforms, Four Buck Regulators

SYNCHRONIZATION INPUT/OUTPUT

The switching frequency of the ADP5050 can be synchronized

to an external clock with a frequency range from 250 kHz to

1.4 MHz. The ADP5050 automatically detects the presence of

an external clock applied to the SYNC/MODE pin, and the

switching frequency transitions smoothly to the frequency of

the external clock. When the external clock signal stops, the

device automatically switches back to the internal clock and

continues to operate.

Note that the internal switching frequency set by the RT pin must

be programmed to a value that is close to the external clock value

for successful synchronization; the suggested frequency differ-

ence is less than ±15% in typical applications.

The SYNC/MODE pin can be configured as a synchronization

clock output by factory fuse or via the I2C interface (Register 10,

HICCUP_CFG). A positive clock pulse with a 50% duty cycle

is generated at the SYNC/MODE pin with a frequency equal to

the internal switching frequency set by the RT pin. There is a

short delay time (approximately 15% of tSW) from the generated

synchronization clock to the Channel 1 switching node.

Figure 47 shows two ADP5050 devices configured for frequency

synchronization mode: one ADP5050 device is configured as

the clock output to synchronize another ADP5050 device. It is

recommended that a 100 kΩ pull-up resistor be used to prevent

logic errors when the SYNC/MODE pin is left floating.

ADP5050

100kΩ

VREG

SYNC/MODE SYNC/MODE

ADP5050

10899-039

Figure 47. Two ADP5050 Devices Configured for Synchronization Mode

In the configuration shown in Figure 47, the phase shift between

Channel 1 of the first ADP5050 device and Channel 1 of the

second ADP5050 device is 0° (see Figure 48).

CH3 5.00V

CH1 2.00V

CH2 5.00V

M400ns A CH1 560mV

10899-148

SW1

AT FI RST

ADP5050

SW1

AT SECO ND

ADP5050

SYNC-OUT

AT FI RST

ADP5050

Figure 48. Waveforms of Two ADP5050 Devices Operating

in Synchronization Mode

Data Sheet ADP5050

Rev. B | Page 23 of 57

SOFT START

The buck regulators in the ADP5050 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

is typically fixed at 2 ms for each buck regulator when the SS12

and SS34 pins are tied to VREG.

To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect

a resistor divider from the SS12 or SS34 pin to the VREG pin and

ground (see Figure 49). This configuration may be required to

accommodate a specific start-up sequence or an application with

a large output capacitor.

LEVEL DETECTOR

AND DECODE R

VREG

TOP

RESISTOR

BOTTOM

RESISTOR

SS12

SS34

ADP5050

10899-041

Figure 49. Level Detector Circuit for Soft Start

The SS12 pin can be used to program the soft start time and

parallel operation for Channel 1 and Channel 2. The SS34 pin

can be used to program the soft start time for Channel 3 and

Channel 4. Table 11 provides the values of the resistors needed

to set the soft start time.

Table 11. Soft Start Time Set by the SS12 and SS34 Pins

Soft Start Time Soft Start Time

RTOP (kΩ)

RBOT (kΩ)

Channel 1 Channel 2 Channel 3 Channel 4

0 N/A 2 ms 2 ms 2 ms 2 ms

100

600

2 ms

Parallel

2 ms

4 ms

200 500 2 ms 8 ms 2 ms 8 ms

300 400 4 ms 2 ms 4 ms 2 ms

400 300 4 ms 4 ms 4 ms 4 ms

500 200 8 ms 2 ms 4 ms 8 ms

600 100 8 ms Parallel 8 ms 2 ms

N/A 0 8 ms 8 ms 8 ms 8 ms

PARALLEL OPERATION

The ADP5050 supports two-phase parallel operation of Channel 1

and Channel 2 to provide a single output with up to 8 A of current.

To configure Channel 1 and Channel 2 as a two-phase single output

in parallel operation, do the following (see Figure 50):

• Use the SS12 pin to select parallel operation as specified

in Table 11.

• Leave the COMP2 pin open.

• Use the FB1 pin to set the output voltage.

• Connect the FB2 pin to ground (FB2 is ignored).

• Connect the EN2 pin to ground (EN2 is ignored).

CHANNEL 1

BUCK REGULAT OR

(4A)

CHANNEL 2

BUCK REGULAT OR

(4A)

FB1

PVIN1 V

OUT

(UP TO 8A)

EN1

EN2

COMP1

SS12

SW1 L1

FB2

SW2 L2

PVIN2

COMP2

VREG

10899-042

Figure 50. Parallel Operation for Channel 1 and Channel 2

When Channel 1 and Channel 2 are operated in the parallel

configuration, configure the channels as follows:

• Set the input voltages and current-limit settings for

Channel 1 and Channel 2 to the same values.

• Operate both channels in forced PWM mode.

Bits pertaining to Channel 2 in the configuration registers

cannot be used. These bits include CH2_ON in Register 1,

VID2 in Register 3, OVP2_ON and SCP2_ON in Register 7,

PHASE2 in Register 8, and PWRG2 in Register 13.

Current balance in parallel configuration is well regulated by

the internal control loop. Figure 51 shows the typical current

balance matching in the parallel output configuration.

0 2 4 6 810

CHANNEL CURRENT (A)

TOTAL OUT P UT LOAD (A)

CH1

CH2

IDEAL

10899-151

Figure 51. Current Balance in Parallel Output Configuration,

VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5050 include a precharged

start-up feature to protect the low-side FETs from damage

during startup. If the output voltage is precharged before the

regulator is turned on, the regulator prevents reverse inductor

current—which discharges the output capacitor—until the

internal soft start reference voltage exceeds the precharged

voltage on the feedback (FBx) pin.

ADP5050 Data Sheet

Rev. B | Page 24 of 57

CURRENT-LIMIT PROTECTION

The buck regulators in the ADP5050 include peak current-limit

protection circuitry to limit the amount of positive current flowing

through the high-side MOSFET. The peak current limit on the

power switch limits the amount of current that can flow from the

input to the output. The programmable current-limit threshold

feature allows for the use of small size inductors for low current

applications.

To configure the current-limit threshold for Channel 1, connect

a resistor from the DL1 pin to ground; to configure the current-

limit threshold for Channel 2, connect another resistor from the

DL2 pin to ground. Table 12 lists the peak current-limit threshold

settings for Channel 1 and Channel 2.

Table 12. Peak Current-Limit Threshold Settings

for Channel 1 and Channel 2

RILIM1 or RILIM2 Typical Peak Current-Limit Threshold

Floating 4.4 A

47 kΩ 2.63 A

22 kΩ 6.44 A

The buck regulators in the ADP5050 include negative current-

limit protection circuitry to limit certain amounts of negative

current flowing through the low-side MOSFET.

FREQUENCY FOLDBACK

The buck regulators in the ADP5050 include frequency fold-

back to prevent output current runaway when a hard short

occurs on the output. Frequency foldback is implemented

as follows:

• If the voltage at the FBx pin falls below half the target

output voltage, the switching frequency is reduced by half.

• If the voltage at the FBx pin falls again to below one-fourth

the target output voltage, the switching frequency is reduced

to half its current value, that is, to one-fourth of fSW.

The reduced switching frequency allows more time for the

inductor current to decrease, but also increases the ripple cur-

rent during peak current regulation. This results in a reduction

in average current and prevents output current runaway.

Pulse Skip Mode Under Maximum Duty Cycle

Under maximum duty cycle conditions, frequency foldback

maintains the output in regulation. If the maximum duty cycle

is reached—for example, when the input voltage decreases—the

PWM modulator skips every other PWM pulse, resulting in a

switching frequency foldback of one-half. If the duty cycle increases

further, the PWM modulator skips two of every three PWM pulses,

resulting in a switching frequency foldback to one-third of the

switching frequency. Frequency foldback increases the effective

maximum duty cycle, thereby decreasing the dropout voltage

between the input and output voltages.

HICCUP PROTECTION

The buck regulators in the ADP5050 include a hiccup mode for

overcurrent protection (OCP). When the peak inductor current

reaches the current-limit threshold, the high-side MOSFET turns

off and the low-side MOSFET turns on until the next cycle.

When hiccup mode is active, the overcurrent fault counter is

incremented. If the overcurrent fault counter reaches 15 and

overflows (indicating a short-circuit condition), both the high-

side and low-side MOSFETs are turned off. The buck regulator

remains in hiccup mode for a period equal to seven soft start

cycles and then attempts to restart from soft start. If the short-

circuit fault has cleared, the regulator resumes normal operation;

otherwise, it reenters hiccup mode after the soft start.

Hiccup protection is masked during the initial soft start cycle to

enable startup of the buck regulator under heavy load conditions.

Note that careful design and proper component selection are

required to ensure that the buck regulator recovers from hiccup

mode under heavy loads. The HICCUPx_OFF bits in Register 10

can be used to disable hiccup protection for each buck regulator.

When hiccup protection is disabled, the frequency foldback feature

is still available for overcurrent protection.

LATCH-OFF PROTECTION

The buck regulators in the ADP5050 have an optional latch-off

mode to protect the device from serious problems such as short-

circuit and overvoltage conditions. Latch-off mode can be enabled

via the I2C interface or by factory fuse.

Short-Circuit Latch-Off Mode

Short-circuit latch-off mode is enabled by factory fuse or by writing

a 1 to the SCPx_ON bit in Register 7, LCH_CFG. When short-

circuit latch-off mode is enabled and the protection circuit detects

an overcurrent status after a soft start, the buck regulator enters

hiccup mode and attempts to restart. If seven continuous restart

attempts are made and the regulator remains in the fault condition,

the regulator is shut down. This shutdown (latch-off) condition is

cleared only by reenabling the channel or by resetting the channel

power supply.

Figure 52 shows the short-circuit latch-off detection function.

OUTPUT

VOLTAGE

TIME

LATCH-OFF

CHx_LCH

LATCH OFF

THIS

REGULATOR

SHORT CI RCUIT DE TECTED

BY COUNTER OVE RFL OW

PWRGD

7 ×

SCP L ATCH-OF F

FUNCTION ENABLED AFT E R

7 REST ART AT TEM P TS

WRITE 1

CHx_LCH BIT

ATTEMPT TO

RESTART

10899-045

Figure 52. Short-Circuit Latch-Off Detection

Data Sheet ADP5050

Rev. B | Page 25 of 57

The short-circuit latch-off status can be read from Register 12,

LCH_STATUS. To clear the status bit, write a 1 to the bit (pro-

vided that the fault no longer persists). The status bit is latched

until a 1 is written to the bit or the part is reset by the internal

VDD power-on reset signal. Note that short-circuit latch-off

mode does not work if hiccup protection is disabled.

Overvoltage Latch-Off Mode

Overvoltage latch-off mode is enabled by factory fuse or by

writing a 1 to the OVPx_ON bit in Register 7, LCH_CFG. The

overvoltage latch-off threshold is 124% of the nominal output

voltage level. When the output voltage exceeds this threshold,

the protection circuit detects the overvoltage status and the regu-

lator shuts down. This shutdown (latch-off) condition is cleared

only by reenabling the channel or by resetting the channel

power supply.

Figure 53 shows the overvoltage latch-off detection function.

OUTPUT

VOLTAGE

TIME

LATCH OFF

THIS

REGULATOR

LATCH-OFF

CHx_LCH WRITE 1

CHx_LCH BI T

124%

NOM I NAL O UTPUT

100%

NOM I NAL O UTPUT

10899-046

CHx ON

Figure 53. Overvoltage Latch-Off Detection

The overvoltage latch-off status can be read from Register 12,

LCH_STATUS. To clear the status bit, write a 1 to the bit (pro-

vided that the fault no longer persists). The status bit is latched

until a 1 is written to the bit or the part is reset by the internal

VDD power-on reset signal.

UNDERVOLTAGE LOCKOUT (UVLO)

Undervoltage lockout circuitry monitors the input voltage level of

each buck regulator in the ADP5050. If any input voltage (PVINx

pin) falls below 3.78 V (typical), the corresponding channel is

turned off. After the input voltage rises above 4.2 V (typical), the

soft start period is initiated, and the corresponding channel is

enabled when the ENx pin is high.

Note that a UVLO condition on Channel 1 (PVIN1 pin) has

a higher priority than a UVLO condition on other channels,

which means that the PVIN1 supply must be available before

other channels can be operated.

POWER-GOOD FUNCTION

The ADP5050 includes an open-drain power-good output

(PWRGD pin) that becomes active high when the selected buck

regulators are operating normally. By default, the PWRGD pin

monitors the output voltage on Channel 1. Other channels can

be configured to control the PWRGD pin when the ADP5050

is ordered (see Table 57).

The power-good status of each channel (PWRGx bit) can be

read back via the I2C interface (Register 13, STATUS_RD). A

value of 1 for the PWRGx bit indicates that the regulated out-

put voltage of the buck regulator is above 90.5% (typical) of its

nominal output. When the regulated output voltage of the buck

regulator falls below 87.2% (typical) of its nominal output for a

delay time greater than approximately 50 µs, the PWRGx bit is

set to 0.

The output of the PWRGD pin is the logical AND of the internal

unmasked PWRGx signals. An internal PWRGx signal must be

high for a validation time of 1 ms before the PWRGD pin goes

high; if one PWRGx signal fails, the PWRGD pin goes low with no

delay. The channels that control the PWRGD pin (Channel 1 to

Channel 4) are specified by factory fuse or by setting the appro-

priate bits in Register 11 (PWRGD_MASK) via the I2C interface.

INTERRUPT FUNCTION

The ADP5050 provides an interrupt output (INT pin) for fault

conditions. During normal operation, the INT pin is pulled

high (an external pull-up resistor should be used). When a fault

condition occurs, the ADP5050 pulls the INT pin low to alert

the I2C host processor that a fault condition has occurred.

Six interrupt sources can trigger the INT pin. By default, no

interrupt sources are configured. To select one or more interrupt

sources to trigger the INT pin, set the appropriate bits to 1 in

When the INT pin is triggered, one or more bits in Register 14

(Bits[5:0]) are set to 1. The fault condition that triggered the INT

pin can be read from Register 14, INT_STATUS (see Table 13).

Table 13. Fault Conditions for Device Interrupt (Register 14)

Interrupt Description

TEMP_INT

Junction temperature has exceeded the con-

figured threshold (selected in Register 9)

LVIN_INT PVIN1 voltage has fallen below the configured

threshold (selected in Register 9)

PWRG4_INT Power-good failure detected on Channel 4

PWRG3_INT

Power-good failure detected on Channel 3

PWRG2_INT Power-good failure detected on Channel 2

PWRG1_INT Power-good failure detected on Channel 1

To clear an interrupt, write a 1 to the appropriate bit in Register 14

(INT_STATUS), take all ENx pins low, or reset the part using the

internal VDD power-on reset signal. Reading the interrupt or

writing a 0 to the bit does not clear the interrupt.

ADP5050 Data Sheet

Rev. B | Page 26 of 57

THERMAL SHUTDOWN

If the ADP5050 junction temperature exceeds 150°C, the thermal

shutdown circuit turns off the IC except for the internal linear

regulators. Extreme junction temperatures can be the result of

high current operation, poor circuit board design, or high ambient

temperature. A 15°C hysteresis is included so that the ADP5050

does not return to operation after thermal shutdown until the

on-chip temperature falls below 135°C. When the part exits ther-

mal shutdown, a soft start is initiated for each enabled channel.

The thermal shutdown status can be read via the I2C interface

(Register 12, LCH_STATUS). When thermal shutdown is detected,

the TSD_LCH bit (Bit 4) is set to 1. To clear the status bit, write a

1 to the bit (provided that the fault no longer persists). The status

bit is latched until a 1 is written to the bit or the part is reset by

the internal VDD power-on reset signal.

OVERHEAT DETECTION

In addition to thermal shutdown protection, the ADP5050

provides an overheat warning function, which compares the

junction temperature with the specified overheat threshold:

105°, 115°, or 125°. The overheat threshold is configured in

detection function sends a warning signal but does not shut

down the part. When the junction temperature exceeds the

overheat threshold, the status bit TEMP_INT in Register 14

is set to 1. The status bit is latched until a 1 is written to the bit,

all ENx pins are taken low, or the part is reset by the internal

VDD power-on reset signal.

The overheat detection function can be used to send a warning

signal to the host processor. After the host processor detects the

overheat warning signal, the processor can take action to prepare

for a possible impending thermal shutdown.

Figure 54 shows the overheat warning function.

JUNCTI ON T E M P E RATURE

TIME

TEMP_INT

(HEAT ST ATUS)

OVERHEAT

CONDITION

DETECTED

NORMAL

TEMPERATURE

115°C

(ADJUSTABLE)

10899-047

Figure 54. Overheat Warning Function

LOW INPUT VOLTAGE DETECTION

In addition to undervoltage lockout (UVLO), the ADP5050

provides a low input voltage detection circuit to monitor PVIN1;

this circuit compares the input voltage with the specified voltage

threshold. The voltage threshold can be set from 4.2 V to 11.2 V

in steps of 0.5 V using Register 9, TH_CFG. Unlike UVLO shut-

down, the low input voltage detection function sends a warning

signal but does not shut down the part. When the PVIN1 input

voltage falls below the threshold, the status bit LVIN_INT in

to the bit, all ENx pins are taken low, or the part is reset by the

internal VDD power-on reset signal.

The low input voltage detection function can be used to send a

warning signal to the host processor. After the host processor

detects the low input voltage warning signal, the processor can

take action to prepare for a possible impending UVLO shutdown.

Figure 55 shows the low input voltage warning function.

INPUT VOLTAGE ON PVIN1

TIME

LVIN_INT

(LVIN STATUS)

LOW INPUT

VOLTAGE

CONDITION

DETECTED

12V INP UT

VOLTAGE

10.7V

(ADJUSTABLE)

10899-048

Figure 55. Low Input Voltage Warning Function (VIN = 12 V)

LDO REGULATOR

The ADP5050 integrates a general-purpose LDO regulator with

low quiescent current and low dropout voltage. The LDO regu-

lator provides up to 200 mA of output current.

The LDO regulator operates with an input voltage of 1.7 V to

5.5 V. The wide supply range makes the regulator suitable for

cascading configurations where the LDO supply voltage is

provided from one of the buck regulators. The LDO output

voltage is set using an external resistor divider (see Figure 56).

LDO FB5

VOUT5

EN5

PVIN5

1µF R

1µF

1.7V TO 5.5V

10899-049

Figure 56. 200 mA LDO Regulator

The LDO regulator provides a high power supply rejection ratio

(PSRR), low output noise, and excellent line and load transient

response using small 1 µF ceramic input and output capacitors.

Data Sheet ADP5050

Rev. B | Page 27 of 57

I2C INTERFACE

The ADP5050 includes an I2C-compatible serial interface for

control of the power management blocks and for readback of

system status (see Figure 57). The I2C interface operates at clock

frequencies of up to 400 kHz.

I2CREGISTER

SCL

SDA

LEVEL

SHIFTER

VDDIO

VDD

VDDIO UVLO_VDDIO

TRIM DAT A

SCP/OVP

VDDIO VDD VDD VDD

VDDIO

10899-051

Figure 57. I2C Interface Block Diagram

Note that the ADP5050 does not respond to general calls. The

ADP5050 accepts multiple masters, but if the device is in read

mode, access is limited to one master until the data transmission

is completed.

The I2C serial interface can be used to access the internal registers

of the ADP5050. For complete information about the ADP5050

registers, see the Register Map section.

SDA AND SCL PINS

The ADP5050 has two dedicated I2C interface pins, SDA and

SCL. SDA is an open-drain line for receiving and transmitting

data. SCL is an input line for receiving the clock signal. Pull up

these pins to the VDDIO supply using external resistors.

Serial data is transferred on the rising edge of SCL. The read

data is generated at the SDA pin in read mode.

I2C ADDRESSES

The default 7-bit I2C chip address for the ADP5050 is 0x48

(1001000 in binary). A different I2C address can be configured

using the optional A0 pin, which can replace the power-good

functionality on Pin 20. (For information about obtaining an

ADP5050 model with Pin 20 functioning as the A0 pin, contact

your local Analog Devices sales or distribution representative.)

The A0 pin allows the use of two ADP5050 devices on the same

I2C communication bus. Figure 58 shows two ADP5050 devices

configured with different I2C addresses using the A0 pin.

10899-050

SCL

VDDIO

C INT E RFACE

CADDRESS = 0x48 I

CADDRESS = 0x49

SDA

SCL

VDDIO

VREG

SDA

Figure 58. Two ADP5050 Devices Configured with Different I2C Addresses

(A0 Function Replaces PWRGD Function on Pin 20)

SELF-CLEAR REGISTER BITS

clear register bits. These bit are cleared automatically when a 1

is written to the status bit. Therefore, it is not necessary to write

a 0 to the status bit to clear it.

ADP5050 Data Sheet

Rev. B | Page 28 of 57

I2C INTERFACE TIMING DIAGRAMS

Figure 59 shows the timing diagram for the I2C write operation.

Figure 60 shows the timing diagram for the I2C read operation.

The subaddress is used to select one of the user registers in the

ADP5050. The ADP5050 sends data to and from the register

specified by the subaddress.

SCL

CHIP ADDRE S S

SDA

A0A1

A2A3

A5A6 A0A1A2A3A4A5A6

0 0001001

D0D1D2D3D4D5D6D7

SUBADDRESS WRI TE DATA

ACK BY SL AV E

WRITE

START

ACK BY SL AV E

R/W

STOP

NOTES

1. M AXIMUM S CL F RE QUENCY IS 400kHz.

2. NO RE S P ONSE TO GENE RAL CALLS.

OUTPUT BY PROCESSOR

OUT P UT BY ADP 5050

10899-052

Figure 59. I2C Write to Register

SCL

CHIP ADDRE S S

SDA

A1A2

A4A5

A6 A0A1

A2A3

A5A6A7

0 0001001

D1D2

D3D4

D6D7

SUBADDRESS CHIP ADDRE S S READ DATA

NOTES

1. M AXIMUM S CL F RE QUENCY IS 400kHz.

2. NO RE S P ONSE TO GENERAL CAL LS.

OUTPUT BY PROCESSOR

OUT P UT BY ADP 5050

ACK BY SL AV E

WRITE

START

ACK BY SL AV E

READ

ACK BY SL AV E

NO ACK BY MAST E R

TO STOP READING

R/W A0

A2A3

A5A6 R/W

STOP

10899-053

Figure 60. I2C Read from Register

Data Sheet ADP5050

Rev. B | Page 29 of 57

APPLICATIONS INFORMATION

ADIsimPower DESIGN TOOL

The ADP5050 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic and bill of materials

and to calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and part count while

taking into consideration the operating conditions and limitations

of the IC and all real external components. The ADIsimPower

tool can be found at www.analog.com/ADIsimPower; the user

can request an unpopulated board through the tool.

PROGRAMMING THE ADJUSTABLE OUTPUT

VOLTAGE

The output voltage of the ADP5050 is externally set by a resistive

voltage divider from the output voltage to the FBx pin. To limit

the degradation of the output voltage accuracy due to feedback

bias current, ensure that the bottom resistor in the divider is not

too large—a value of less than 50 kΩ is recommended.

The equation for the output voltage setting is

VOUT = VREF × (1 + (RTOP/RBOT))

where:

VOUT is the output voltage.

VREF is the feedback reference voltage: 0.8 V for Channel 1 to

Channel 4 and 0.5 V for Channel 5.

RTOP is the feedback resistor from VOUT to FB.

RBOT is the feedback resistor from FB to ground.

No resistor divider is required in the fixed output options. Each

channel has VIDx bits to program the output voltage for a specific

range (see Table 10). If a different fixed output voltage (default

VID code) is required, contact your local Analog Devices sales

or distribution representative.

VOLTAGE CONVERSION LIMITATIONS

For a given input voltage, upper and lower limitations on the

output voltage exist due to the minimum on time and the

minimum off time.

The minimum output voltage for a given input voltage and

switching frequency is limited by the minimum on time. The

minimum on time for Channel 1 and Channel 2 is 117 ns

(typical); the minimum on time for Channel 3 and Channel 4

is 90 ns (typical). The minimum on time increases at higher

junction temperatures.

Note that in forced PWM mode, Channel 1 and Channel 2 can

potentially exceed the nominal output voltage when the mini-

mum on time limit is exceeded. Careful switching frequency

selection is required to avoid this problem.

The minimum output voltage in continuous conduction mode

(CCM) for a given input voltage and switching frequency can be

calculated using the following equation:

VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) ×

IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN (1)

where:

VOUT_MIN is the minimum output voltage.

tMIN_ON is the minimum on time.

fSW is the switching frequency.

RDSON1 is the on resistance of the high-side MOSFET.

RDSON2 is the on resistance of the low-side MOSFET.

IOUT_MIN is the minimum output current.

RL is the resistance of the output inductor.

The maximum output voltage for a given input voltage and

switching frequency is limited by the minimum off time and

the maximum duty cycle. Note that the frequency foldback

feature helps to increase the effective maximum duty cycle by

lowering the switching frequency, thereby decreasing the dropout

voltage between the input and output voltages (see the Frequency

Foldback section).

The maximum output voltage for a given input voltage and switch-

ing frequency can be calculated using the following equation:

VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) ×

IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX (2)

where:

VOUT_MAX is the maximum output voltage.

tMIN_OFF is the minimum off time.

fSW is the switching frequency.

RDSON1 is the on resistance of the high-side MOSFET.

RDSON2 is the on resistance of the low-side MOSFET.

IOUT_MAX is the maximum output current.

RL is the resistance of the output inductor.

As shown in Equation 1 and Equation 2, reducing the switching

frequency eases the minimum on time and off time limitations.

CURRENT-LIMIT SETTING

The ADP5050 has three selectable current-limit thresholds for

Channel 1 and Channel 2. Make sure that the selected current-

limit value is larger than the peak current of the inductor, IPEAK.

See Table 12 for the current-limit configuration for Channel 1

and Channel 2.

ADP5050 Data Sheet

Rev. B | Page 30 of 57

SOFT START SETTING

The buck regulators in the ADP5050 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. To set the soft start

time to a value of 2 ms, 4 ms, or 8 ms, connect a resistor divider

from the SS12 or SS34 pin to the VREG pin and ground (see the

Soft Start section).

INDUCTOR SELECTION

The inductor value is determined by the switching frequency,

input voltage, output voltage, and inductor ripple current. Using

a small inductor value yields faster transient response but degrades

efficiency due to the larger inductor ripple current. Using a large

inductor value yields a smaller ripple current and better efficiency

but results in slower transient response. Thus, a trade-off must be

made between transient response and efficiency. As a guideline,

the inductor ripple current, ΔIL, is typically set to a value from

30% to 40% of the maximum load current. The inductor value

can be calculated using the following equation:

L = [(VIN − VOUT) × D]/(ΔIL × fSW)

where:

VIN is the input voltage.

VOUT is the output voltage.

D is the duty cycle (D = VOUT/VIN).

ΔIL is the inductor ripple current.

fSW is the switching frequency.

The ADP5050 has internal slope compensation in the current

loop to prevent subharmonic oscillations when the duty cycle

is greater than 50%.

The peak inductor current is calculated using the following

equation:

IPEAK = IOUT + (ΔIL/2)

The saturation current of the inductor must be larger than the

peak inductor current. For ferrite core inductors with a fast

saturation characteristic, make sure that the saturation current

rating of the inductor is higher than the current-limit threshold

of the buck regulator to prevent the inductor from becoming

saturated.

The rms current of the inductor can be calculated using the

following equation:

OUT

RMS

II ∆

Shielded ferrite core materials are recommended for low core

loss and low EMI. Table 14 lists recommended inductors.

Table 14. Recommended Inductors

Vendor Part No.

Value

(µH)

ISAT

(A)

IRMS

(A)

DCR

(mΩ)

Size

(mm)

Coilcraft XFL4020-102 1.0 5.4 11 10.8 4 × 4

XFL4020-222 2.2 3.7 8.0 21.35 4 × 4

XFL4020-332 3.3 2.9 5.2 34.8 4 × 4

XFL4020-472 4.7 2.7 5.0 52.2 4 × 4

XAL4030-682

6.8

3.6

3.9

67.4

4 × 4

XAL4040-103 10 3.0 3.1 84 4 × 4

XAL6030-102 1.0 23 18 5.62 6 × 6

XAL6030-222 2.2 15.9 10 12.7 6 × 6

XAL6030-332 3.3 12.2 8.0 19.92 6 × 6

XAL6060-472 4.7 10.5 11 14.4 6 × 6

XAL6060-682 6.8 9.2 9.0 18.9 6 × 6

TOKO FDV0530-1R0 1.0 11.2 9.1 9.4 6.2 × 5.8

FDV0530-2R2 2.2 7.1 7.0 17.3 6.2 × 5.8

FDV0530-3R3

3.3

5.5

5.3

29.6

6.2 × 5.8

FDV0530-4R7 4.7 4.6 4.2 46.6 6.2 × 5.8

OUTPUT CAPACITOR SELECTION

The selected output capacitor affects both the output voltage

ripple and the loop dynamics of the regulator. For example,

during load step transients on the output, when the load is

suddenly increased, the output capacitor supplies the load until

the control loop can ramp up the inductor current, causing an

undershoot of the output voltage.

The output capacitance required to meet the undershoot

(voltage droop) requirement can be calculated using the

following equation:

( )

UVOUTOUT

STEP

UVOUT

VVV

LIK

2∆×−×

×∆×

where:

KUV is a factor (typically set to 2).

ΔISTEP is the load step.

ΔVOUT_UV is the allowable undershoot on the output voltage.

Another example of the effect of the output capacitor on the loop

dynamics of the regulator is when the load is suddenly removed

from the output and the energy stored in the inductor rushes into

the output capacitor, causing an overshoot of the output voltage.

The output capacitance required to meet the overshoot require-

ment can be calculated using the following equation:

()

OUTOUT_OV

OUT

STEP

OVOUT

C−∆+

×∆×

where:

KOV is a factor (typically set to 2).

ΔISTEP is the load step.

ΔVOUT_OV is the allowable overshoot on the output voltage.

Data Sheet ADP5050

Rev. B | Page 31 of 57

The output voltage ripple is determined by the ESR of the output

capacitor and its capacitance value. Use the following equations

to select a capacitor that can meet the output ripple requirements:

RIPPLEOUT

RIPPLEOUT Vf

_8∆××

∆

RIPPLEOUT

ESR I

R∆

∆

where:

ΔIL is the inductor ripple current.

fSW is the switching frequency.

ΔVOUT_RIPPLE is the allowable output voltage ripple.

RESR is the equivalent series resistance of the output capacitor.

Select the largest output capacitance given by COUT_UV, COUT_OV,

and COUT_RIPPLE to meet both load transient and output ripple

requirements.

The voltage rating of the selected output capacitor must be

greater than the output voltage. The minimum rms current

rating of the output capacitor is determined by the following

equation:

rmsC

IOUT

∆

INPUT CAPACITOR SELECTION

The input decoupling capacitor attenuates high frequency noise

on the input and acts as an energy reservoir. Use a ceramic capac-

itor and place it close to the PVINx pin. The loop composed of

the input capacitor, the high-side NFET, and the low-side NFET

must be kept as small as possible. The voltage rating of the input

capacitor must be greater than the maximum input voltage. Make

sure that the rms current rating of the input capacitor is larger

than the following equation:

( )

DDII OUT

rmsC

−××= 1

where D is the duty cycle (D = VOUT/VIN).

LOW-SIDE POWER DEVICE SELECTION

Channel 1 and Channel 2 include integrated low-side MOSFET

drivers, which can drive low-side N-chan nel MOSF E Ts (NFETs ).

The selection of the low-side N-channel MOSFET affects the

performance of the buck regulator.

The selected MOSFET must meet the following requirements:

• Drain-to-source voltage (VDS) must be higher than 1.2 × VIN.

• Drain current (ID) must be greater than 1.2 × ILIMIT_MAX, where

ILIMIT_MAX is the selected maximum current-limit threshold.

• The selected MOSFET can be fully turned on at VGS = 4.5 V.

• Total gate charge (Qg at VGS = 4.5 V) must be less than 20 nC.

Lower Qg characteristics provide higher efficiency.

When the high-side MOSFET is turned off, the low-side MOSFET

supplies the inductor current. For low duty cycle applications, the

low-side MOSFET supplies the current for most of the period.

To achieve higher efficiency, it is important to select a MOSFET

with low on resistance. The power conduction loss for the low-

side MOSFET can be calculated using the following equation:

PFET_LOW = IOUT2 × RDSON × (1 − D)

where:

RDSON is the on resistance of the low-side MOSFET.

D is the duty cycle (D = VOUT/VIN).

Table 15 lists recommended dual MOSFETs for various current-

limit settings. Ensure that the MOSFET can handle thermal

dissipation due to power loss.

Table 15. Recommended Dual MOSFETs

Vendor Part No. VDS (V) ID (A)

RDSON

(mΩ)

(nC)

Size

(mm)

IR IRFHM8363 30 10 20.4 6.7 3 × 3

IRLHS6276

3.4

3.1

2 × 2

Fairchild FDMA1024 20 5.0 54 5.2 2 × 2

FDMB3900 25 7.0 33 11 3 × 2

FDMB3800 30 4.8 51 4 3 × 2

FDC6401 20 3.0 70 3.3 3 × 3

Vishay

Si7228DN

4.1

3 × 3

Si7232DN 20 25 16.4 12 3 × 3

Si7904BDN 20 6 30 9 3 × 3

Si5906DU 30 6 40 8 3 × 2

Si5908DC 20 5.9 40 5 3 × 2

SiA906EDJ 20 4.5 46 3.5 2 × 2

AOS AON7804 30 22 26 7.5 3 × 3

AON7826 20 22 26 6 3 × 3

AO6800 30 3.4 70 4.7 3 × 3

AON2800

4.5

4.1

2 × 2

PROGRAMMING THE UVLO INPUT

The precision enable input can be used to program the UVLO

threshold of the input voltage, as shown in Figure 43. To l imit

the degradation of the input voltage accuracy due to the internal

1 MΩ pull-down resistor tolerance, ensure that the bottom resistor

in the divider is not too large—a value of less than 50 kΩ is

recommended.

The precision turn-on threshold is 0.8 V. The resistive voltage

divider for the programmable VIN start-up voltage is calculated

as follows:

VIN_STARTUP = (0.8 nA + (0.8 V/RBOT_EN)) × (RTOP_EN + RBOT_EN)

where:

RTOP_EN is the resistor from VIN to EN.

RBOT_EN is the resistor from EN to ground.

ADP5050 Data Sheet

Rev. B | Page 32 of 57

COMPENSATION COMPONENTS DESIGN

For the peak current-mode control architecture, the power

stage can be simplified as a voltage controlled current source

that supplies current to the output capacitor and load resistor.

The simplified loop is composed of one domain pole and a zero

contributed by the output capacitor ESR. The control-to-output

transfer function is shown in the following equations:













×π×













×π×

××==

COMP

OUT

)(

OUT

ESR

f×

π×

()

OUT

ESR

CRR

f×

+×π

where:

AVI = 10 A/V for Channel 1 or Channel 2, and 3.33 A/V for

Channel 3 or Channel 4.

R is the load resistance.

RESR is the equivalent series resistance of the output capacitor.

COUT is the output capacitance.

The ADP5050 uses a transconductance amplifier as the error

amplifier to compensate the system. Figure 61 shows the sim-

plified peak current-mode control small signal circuit.

RESR

–

RCCCP

COUT

RTOP

RBOT

–

AVI

VOUT

VCOMP

VOUT

10899-054

Figure 61. Simplified Peak Current-Mode Control Small Signal Circuit

The compensation components, RC and CC, contribute a zero;

RC and the optional CCP contribute an optional pole.

The closed-loop transfer equation is as follows:

)(

)( sG

CCR

sCR

CPC

CPCC

CPC

TOPBOT

BOT











×

××

+×

××+

−

The following guidelines show how to select the compensation

components—RC, CC, and CCP—for ceramic output capacitor

applications.

1. Determine the cross frequency (fC). Generally, fC is between

fSW/12 and fSW/6.

2. Calculate RC using the following equation:

OUTOUT

fCV

R×

×××π

3. Place the compensation zero at the domain pole (fP).

Calculate CC using the following equation:

( )

OUT

ESR

CRR

C×+

4. CCP is optional. It can be used to cancel the zero caused

by the ESR of the output capacitor. Calculate CCP using

the following equation:

OUT

ESR

CP R

C×

POWER DISSIPATION

The total power dissipation in the ADP5050 simplifies to

PD = PBUCK1 + PBUCK2 + PBUCK3 + PBUCK4 + PLDO

Buck Regulator Power Dissipation

The power dissipation (PLOSS) for each buck regulator includes

power switch conduction losses (PCOND), switching losses (PSW),

and transition losses (PTRAN). Other sources of power dissipation

exist, but these sources are generally less significant at the high

output currents of the application thermal limit.

Use the following equation to estimate the power dissipation of

the buck regulator:

PLOSS = PCOND + PSW + PTRAN

Power Switch Conduction Loss (PCOND)

Power switch conduction losses are caused by the flow of output

current through both the high-side and low-side power switches,

each of which has its own internal on resistance (RDSON).

Use the following equation to estimate the power switch

conduction loss:

PCOND = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2

where:

RDSON_HS is the on resistance of the high-side MOSFET.

RDSON_LS is the on resistance of the low-side MOSFET.

D is the duty cycle (D = VOUT/VIN).

Data Sheet ADP5050

Rev. B | Page 33 of 57

Switching Loss (PSW)

Switching losses are associated with the current drawn by the

driver to turn the power devices on and off at the switching

frequency. Each time a power device gate is turned on or off,

the driver transfers a charge from the input supply to the gate,

and then from the gate to ground. Use the following equation

to estimate the switching loss:

PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW

where:

CGATE_HS is the gate capacitance of the high-side MOSFET.

CGATE_LS is the gate capacitance of the low-side MOSFET.

fSW is the switching frequency.

Transition Loss (PTRAN)

Transition losses occur because the high-side MOSFET cannot

turn on or off instantaneously. During a switch node transition,

the MOSFET provides all the inductor current. The source-to-

drain voltage of the MOSFET is half the input voltage, resulting

in power loss. Transition losses increase with both load and input

voltage and occur twice for each switching cycle. Use the following

equation to estimate the transition loss:

PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW

where:

tR is the rise time of the switch node.

tF is the fall time of the switch node.

Thermal Shutdown

Channel 1 and Channel 2 store the value of the inductor current

only during the on time of the internal high-side MOSFET.

Therefore, a small amount of power (as well as a small amount

of input rms current) is dissipated inside the ADP5050, which

reduces thermal constraints.

However, when Channel 1 and Channel 2 are operating under

maximum load with high ambient temperature and high duty

cycle, the input rms current can become very large and cause

the junction temperature to exceed the maximum junction tem-

perature of 125°C. If the junction temperature exceeds 150°C,

the regulator enters thermal shutdown and recovers when the

junction temperature falls below 135°C.

LDO Regulator Power Dissipation

The power dissipation of the LDO regulator is given by the

following equation:

PLDO = [(VIN − VOUT) × IOUT] + (VIN × IGND)

where:

VIN and VOUT are the input and output voltages of the LDO

regulator.

IOUT is the load current of the LDO regulator.

IGND is the ground current of the LDO regulator.

Power dissipation due to the ground current is small in the

ADP5050 and can be ignored.

JUNCTION TEMPERATURE

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to power dissipation, as shown in the following

equation:

TJ = TA + TR

where:

TJ is the junction temperature.

TA is the ambient temperature.

TR is the rise in temperature of the package due to power

dissipation.

The rise in temperature of the package is directly proportional

to the power dissipation in the package. The proportionality

constant for this relationship is the thermal resistance from the

junction of the die to the ambient temperature, as shown in the

following equation:

TR = θJA × PD

where:

TR is the rise in temperature of the package.

θJA is the thermal resistance from the junction of the die to the

ambient temperature of the package (see Table 7).

PD is the power dissipation in the package.

An important factor to consider is that the thermal resistance

value is based on a 4-layer, 4 inch × 3 inch PCB with 2.5 oz. of

copper, as specified in the JEDEC standard, whereas real-world

applications may use PCBs with different dimensions and a

different number of layers.

It is important to maximize the amount of copper used to remove

heat from the device. Copper exposed to air dissipates heat better

than copper used in the inner layers. Connect the exposed pad

to the ground plane with several vias.

ADP5050 Data Sheet

Rev. B | Page 34 of 57

DESIGN EXAMPLE

This section provides an example of the step-by-step design

procedures and the external components required for Channel 1.

Table 16 lists the design requirements for this example.

Table 16. Example Design Requirements for Channel 1

Parameter Specification

Input Voltage VPVIN1 = 12 V ± 5%

Output Voltage VOUT1 = 1.2 V

Output Current IOUT1 = 4 A

Output Ripple ΔVOUT1_RIPPLE = 12 mV in CCM mode

Load Transient ±5% at 20% to 80% load transient, 1 A/µs

Although this example shows step-by-step design procedures

for Channel 1, the procedures apply to all other buck regulator

channels (Channel 2 to Channel 4).

SETTING THE SWITCHING FREQUENCY

The first step is to determine the switching frequency for the

ADP5050 design. In general, higher switching frequencies

produce a smaller solution size due to the lower component

values required, whereas lower switching frequencies result in

higher conversion efficiency due to lower switching losses.

The switching frequency of the ADP5050 can be set to a value

from 250 kHz to 1.4 MHz by connecting a resistor from the RT

pin to ground. The selected resistor allows the user to make

decisions based on the trade-off between efficiency and solution

size. (For more information, see the Oscillator section.) However,

the highest supported switching frequency must be assessed by

checking the voltage conversion limitations enforced by the

minimum on time and the minimum off time (see the Voltage

Conversion Limitations section).

In this design example, a switching frequency of 600 kHz is

used to achieve a good combination of small solution size and

high conversion efficiency. To set the switching frequency to

600 kHz, use the following equation to calculate the resistor

value, RRT:

RRT (kΩ) = [14,822/fSW (kHz)]1.081

Therefore, select standard resistor RRT = 31.6 kΩ.

SETTING THE OUTPUT VOLTAGE

Select a 10 kΩ bottom resistor (RBOT) and then calculate the top

feedback resistor using the following equation:

RBOT = RTOP × (VREF/(VOUT − VREF))

where:

VREF is 0.8 V for Channel 1.

VOUT is the output voltage.

To set the output voltage to 1.2 V, choose the following resistor

values: RTOP = 4.99 kΩ, RBOT = 10 kΩ.

SETTING THE CURRENT LIMIT

For 4 A output current operation, the typical peak current limit

is 6.44 A. For this example, choose RILIM1 = 22 kΩ (see Table 12).

For more information, see the Current-Limit Protection section.

SELECTING THE INDUCTOR

The peak-to-peak inductor ripple current, ΔIL, is set to 35% of

the maximum output current. Use the following equation to

estimate the value of the inductor:

L = [(VIN − VOUT) × D]/(ΔIL × fSW)

where:

VIN = 12 V.

VOUT = 1.2 V.

D is the duty cycle (D = VOUT/VIN = 0.1).

ΔIL = 35% × 4 A = 1.4 A.

fSW = 600 kHz.

The resulting value for L is 1.28 µH. The closest standard

inductor value is 1.5 µH; therefore, the inductor ripple current,

ΔIL, is 1.2 A.

The peak inductor current is calculated using the following

equation:

IPEAK = IOUT + (ΔIL/2)

The calculated peak current for the inductor is 4.6 A.

The rms current of the inductor can be calculated using the

following equation:

OUT

RMS

II ∆

The rms current of the inductor is approximately 4.02 A.

Therefore, an inductor with a minimum rms current rating

of 4.02 A and a minimum saturation current rating of 4.6 A is

required. However, to prevent the inductor from reaching its

saturation point in current-limit conditions, it is recommended

that the inductor saturation current be higher than the maximum

peak current limit, typically 7.48 A, for reliable operation.

Based on these requirements and recommendations, the

TOKO FDV0530-1R5, with a DCR of 13.5 mΩ, is selected

for this design.

Data Sheet ADP5050

Rev. B | Page 35 of 57

SELECTING THE OUTPUT CAPACITOR

The output capacitor must meet the output voltage ripple and

load transient requirements. To meet the output voltage ripple

requirement, use the following equations to calculate the ESR

and capacitance:

RIPPLEOUT

8∆××

∆

RIPPLEOUT

ESR

R∆

∆

The calculated capacitance, COUT_RIPPLE, is 20.8 µF, and the

calculated RESR is 10 mΩ.

To meet the ±5% overshoot and undershoot requirements,

use the following equations to calculate the capacitance:

( )

UVOUTOUT

STEP

UVOUT

VVV

LIK

2∆×−×

×∆×

( )

OUTOUT_OVOUT

STEP

OVOUT

VVV

LIK

C−∆+

×∆×

For estimation purposes, use KOV = KUV = 2; therefore,

COUT_OV = 117 µF and COUT_UV = 13.3 µF.

The ESR of the output capacitor must be less than 13.3 mΩ,

and the output capacitance must be greater than 117 µF. It is

recommended that three ceramic capacitors be used (47 µF,

X5R, 6.3 V), such as the GRM21BR60J476ME15 from Murata

with an ESR of 2 mΩ.

SELECTING THE LOW-SIDE MOSFET

A low RDSON N-channel MOSFET must be selected for high

efficiency solutions. The MOSFET breakdown voltage (VDS)

must be greater than 1.2 × VIN, and the drain current must be

greater than 1.2 × ILIMIT_MAX.

It is recommended that a 20 V, dual N-channel MOSFET—such

as the Si7232DN from Vishay—be used for both Channel 1 and

Channel 2. The RDSON of the Si7232DN at 4.5 V driver voltage is

16.4 mΩ, and the total gate charge is 12 nC.

DESIGNING THE COMPENSATION NETWORK

For better load transient and stability performance, set the cross

frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz;

therefore, fC is set to 60 kHz.

For the 1.2 V output rail, the 47 µF ceramic output capacitor has

a derated value of 40 µF.

Ω=

×µ×

×µ×××π×

=k4.14

A/V10S470V8.0

kHz60F403V2.12

( )

nF51.2

k4.14

F403001.03.0 =

Ω

µ××Ω+Ω

pF3.8

k4.14

F403001.0 =

Ω

µ××Ω

Choose standard components: RC = 15 kΩ and CC = 2.7 n F.

CCP is optional.

Figure 62 shows the Bode plot for the 1.2 V output rail.

The cross frequency is 62 kHz, and the phase margin is 58°.

Figure 63 shows the load transient waveform.

100

–100

–80

–60

–40

–20

120

–180

–150

–120

–90

–60

–30

1k 10k 100k 1M

MAG NITUDE ( dB)

PHASE ( Degrees)

FRE Q UE NCY ( Hz )

CROSS FREQUENCY : 62kHz

PHASE M ARGI N: 58°

10899-161

Figure 62. Bode Plot for 1.2 V Output

CH1 50.0mV

CH4 2.00A Ω

M200µs A CH4 2.32A

OUT

10899-162

Figure 63. 0.8 A to 3.2 A Load Transient for 1.2 V Output

SELECTING THE SOFT START TIME

The soft start feature allows the output voltage to ramp up in a

controlled manner, eliminating output voltage overshoot during

soft start and limiting the inrush current.

The SS12 pin can be used to program a soft start time of 2 ms,

4 ms, or 8 ms and can also be used to configure parallel opera-

tion of Channel 1 and Channel 2. For more information, see the

Soft Start section and Table 11.

SELECTING THE INPUT CAPACITOR

For the input capacitor, select a ceramic capacitor with a mini-

mum value of 10 µF; place the input capacitor close to the PVIN1

pin. In this example, one 10 µF, X5R, 25 V ceramic capacitor is

recommended.

ADP5050 Data Sheet

Rev. B | Page 36 of 57

RECOMMENDED EXTERNAL COMPONENTS

Table 17 lists the recommended external components for 4 A applications used with Channel 1 and Channel 2 of the ADP5050.

Table 18 lists the recommended external components for 1.2 A applications used with Channel 3 and Channel 4.

Table 17. Recommended External Components for Typical 4 A Applications, Channel 1 and Channel 2

(±1% Output Ripple, ±7.5% Tolerance at ~60% Step Transient)

fSW (kHz) IOUT (A) VIN (V) VOUT (V) L (µH) COUT (µF) RTOP (kΩ) RBOT (kΩ) RC (kΩ) CC (pF) Dual FET

300 4 12 (or 5) 1.2 3.3 2 × 1001 4.99 10 10 4700 Si7232DN

12 (or 5) 1.5 3.3 2 × 1001 8.87 10.2 10 4700 Si7232DN

12 (or 5) 1.8 3.3 3 × 472 12.7 10.2 6.81 4700 Si7232DN

12 (or 5) 2.5 4.7 3 × 472 21.5 10.2 10 4700 Si7232DN

12 (or 5) 3.3 6.8 3 × 472 31.6 10.2 10 4700 Si7232DN

12 5.0 6.8 473 52.3 10 4.7 4700 Si7232DN

600

12 (or 5)

1.2

1.5

2 × 47

4.99

2700

Si7232DN

12 (or 5) 1.5 1.5 2 × 472 8.87 10.2 10 2700 Si7232DN

12 (or 5) 1.8 2.2 2 × 472 12.7 10.2 10 2700 Si7232DN

12 (or 5) 2.5 2.2 2 × 472 21.5 10.2 10 2700 Si7232DN

12 (or 5) 3.3 3.3 2 × 472 31.6 10.2 15 2700 Si7232DN

12 5.0 3.3 473 52.3 10 10 2700 Si7232DN

1000 4 5 1.2 1.0 2 × 472 4.99 10 15 1500 Si7232DN

5 1.5 1.0 2 × 472 8.87 10.2 15 1500 Si7232DN

12 (or 5) 1.8 1.0 472 12.7 10.2 10 1500 Si7232DN

12 (or 5) 2.5 1.5 472 21.5 10.2 10 1500 Si7232DN

12 (or 5) 3.3 1.5 472 31.6 10.2 10 1500 Si7232DN

12 5.0 2.2 473 52.3 10 15 1500 Si7232DN

1 100 µF capacitor: Murata GRM31CR60J107ME39 (6.3 V, X5R, 1206).

2 47 µF capacitor: Murata GRM21BR60J476ME15 (6.3 V, X5R, 0805).

3 47 µF capacitor: Murata GRM31CR61A476ME15 (10 V, X5R, 1206).

Table 18. Recommended External Components for Typical 1.2 A Applications, Channel 3 and Channel 4

(±1% Output Ripple, ±7.5% Tolerance at ~60% Step Transient)

fSW (kHz) IOUT (A) VIN (V) VOUT (V) L (µH) COUT (µF) RTOP (kΩ) RBOT (kΩ) RC (kΩ) CC (pF)

300 1.2 12 (or 5) 1.2 10 2 × 221 4.99 10 6.81 4700

12 (or 5) 1.5 10 2 × 221 8.87 10.2 6.81 4700

12 (or 5) 1.8 15 2 × 221 12.7 10.2 6.81 4700

12 (or 5) 2.5 15 2 × 221 21.5 10.2 6.81 4700

12 (or 5) 3.3 22 2 × 221 31.6 10.2 6.81 4700

12 5.0 22 222 52.3 10 6.81 4700

600 1.2 12 (or 5) 1.2 4.7 221 4.99 10 6.81 2700

12 (or 5) 1.5 6.8 221 8.87 10.2 6.81 2700

12 (or 5) 1.8 6.8 221 12.7 10.2 6.81 2700

12 (or 5) 2.5 10 221 21.5 10.2 6.81 2700

12 (or 5) 3.3 10 221 31.6 10.2 6.81 2700

12 5.0 10 222 52.3 10 6.81 2700

1000 1.2 5 1.2 2.2 221 4.99 10 10 1800

12 (or 5) 1.5 3.3 221 8.87 10.2 10 1800

12 (or 5) 1.8 4.7 221 12.7 10.2 10 1800

12 (or 5)

2.5

4.7

21.5

10.2

1800

12 (or 5)

3.3

6.8

31.6

10.2

1800

12 5.0 6.8 222 52.3 10 15 1800

1 22 µF capacitor: Murata GRM188R60J226MEA0 (6.3 V, X5R, 0603).

2 22 µF capacitor: Murata GRM219R61A226MEA0 (10 V, X5R, 0805).

Data Sheet ADP5050

Rev. B | Page 37 of 57

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential to obtain the best perfor-

mance from the ADP5050 (see Figure 65). Poor layout can affect

the regulation and stability of the part, as well as the electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) performance. Refer to the following guidelines for a good

PCB layout.

• Place the input capacitor, inductor, MOSFET, output

capacitor, and bootstrap capacitor close to the IC.

• Use short, thick traces to connect the input capacitors

to the PVINx pins, and use dedicated power ground to

connect the input and output capacitor grounds to

minimize the connection length.

• Use several high current vias, if required, to connect

PVINx, PGNDx, and SWx to other power planes.

• Use short, thick traces to connect the inductors to the

SWx pins and the output capacitors.

• Ensure that the high current loop traces are as short and

wide as possible. Figure 64 shows the high current path.

• Maximize the amount of ground metal for the exposed

pad, and use as many vias as possible on the component

side to improve thermal dissipation.

• Use a ground plane with several vias connecting to the com-

ponent side ground to further reduce noise interference on

sensitive circuit nodes.

• Place the decoupling capacitors close to the VREG and

VDD pins.

• Place the frequency setting resistor close to the RT pin.

• Place the feedback resistor divider close to the FBx pin. In

addition, keep the FBx traces away from the high current

traces and the switch node to avoid noise pickup.

• Use Size 0402 or 0603 resistors and capacitors to achieve

the smallest possible footprint solution on boards where

space is limited.

OUT

PVINx

ENx GND

BSTx

SWx

ADP5050

DLx

FBx

10899-055

Figure 64. Typical Circuit with High Current Traces Shown in Blue

10899-163

Figure 65. Typical PCB Layout for the ADP5050

ADP5050 Data Sheet

Rev. B | Page 38 of 57

TYPICAL APPLICATION CIRCUITS

VREG

CHANNEL 2

BUCK REGULAT OR

(1.2A/2.5A/4A)

CHANNEL 3

BUCK REGULAT OR

(1.2A)

OSCILLATOR

INT VREG

100mA

5V REG

SYNC/MODE

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

BST3

SW3

FB3

PGND3

ALERT

10µH

4.7µH

2.2µH

SiA906EDJ

(46mΩ)

31.6kΩ

6.81kΩ

2.7nF

6.81kΩ

2.7nF

6.81kΩ

2.7nF

6.81kΩ

2.7nF

BST4

SW4

FB4

PGND4

VREG

PVIN1

COMP1

EN1

PVIN2

COMP2

EN2

PVIN3

SS34

COMP3

EN3

VDDIO

OPTIONAL

C INT E RFACE

PVIN4

COMP4

EN4

SCL

SDA

10µF

1.0µF

47µF

0.1µF

10µF

0.1µF

47µF

10µF

C10

22µF

C11

10µF

C12

0.1µF

C13

22µF

12V

VOUT1

VOUT2

VDDIO

PROCESSOR

3.3V/2.5A

2.85V/100mA

1.5V/1.2A

4.0V TO 4.5V/1. 2A

(DVS)

1.1V TO 1.3V/2. 5A

(DVS)

DDR

TERM. LDO

DDR

MEMORY

RFPA

TRANSCEIVER

nINT

VCORE

I/O

VOUT3

VOUT4

PWRGD

5V REG

EXPOSED PAD

SS12

VREG

1.0µF

VDD

CHANNEL 5

200mA LDO

REGULATOR FB5

EN5 VOUT5

PVIN5

C15

1µF

10kΩ

47kΩ

C14

1µF

VOUT5

ADP5050

CHANNEL 1

BUCK REGULAT OR

(1.2A/2.5A/4A)

CHANNEL 4

BUCK REGULAT OR

(1.2A)

VREG

OPTIONAL

INTERFACE

SCL

SDA SCL

SDA

10899-056

CINT

Figure 66. Typical Femtocell Application, 600 kHz Switching Frequency, Fixed Output Model

Data Sheet ADP5050

Rev. B | Page 39 of 57

VREG

CHANNEL 2

BUCK REGULAT OR

(1.2A/2.5A/4A)

CHANNEL 3

BUCK REGULAT OR

(1.2A)

OSCILLATOR

INT VREG

100mA

SYNC/MODE

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

BST3

SW3

FB3

PGND3

ALERT

10µH

6.8µH

2.2µH

1.5µH

BST4

SW4

FB4

PGND4

VREG

PVIN1

COMP1

EN1

PVIN2

COMP2

EN2

PVIN3

SS34

COMP3

EN3

VDDIO

OPTIONAL

C INTERF ACE

PVIN4

COMP4

EN4

SCL

SDA

10µF

1.0µF

47µF

0.1µF

10µF

0.1µF C7

47µF

10µF C9

0.1µF

C10

22µF

C11

10µF

C12

0.1µF

C13

22µF

12V

VOUT1

VOUT2

FPGA

2.5V/4A

1.2V/100mA

1.5V/1.2A

3.3V/1.2A

1.2V/4A

DDR

TERM. LDO DDR

MEMORY

FLASH

MEMORY

VCORE

I/ O BANK 1

I/ O BANK 0

I/ O BANK 2

VOUT3

VOUT4

22kΩ

31.6kΩ

22kΩ

PWRGD

SS12

VREG

1.0µF

VDD

CHANNEL 5

200mA LDO

REGULATOR FB5

EN5 VOUT5

PVIN5

C15

1µF

C14

1µF

VOUT5

ADP5050

CHANNEL 1

BUCK REGULAT OR

(1.2A/2.5A/4A)

CHANNEL 4

BUCK REGULAT OR

(1.2A)

C16

47µF

C17

47µF

VREG

MGTs

I/ O BANK 3

AUXILIARY

VOLTAGE

10899-057

EXPOSED PAD

Si7232DN

(16.4mΩ)

5V REG

6.81kΩ

2.7nF

10kΩ

2.7nF

10kΩ

2.7nF

6.81kΩ

10kΩ

10.2kΩ

31.6kΩ

10.2kΩ

8.87kΩ

10.2kΩ

4.99kΩ

10kΩ

21.5kΩ

14kΩ

2.7nF

INT

Figure 67. Typical FPGA Application, 600 kHz Switching Frequency, Adjustable Output Model

ADP5050 Data Sheet

Rev. B | Page 40 of 57

VREG

CHANNEL 2

BUCK REGULAT OR

(1.2A/2.5A/4A)

CHANNEL 3

BUCK REGULAT OR

(1.2A)

OSCILLATOR

INT VREG

100mA

1.5µH

6.8µH

10µH

5V REG

SYNC/MODE

FB1

BST1

SW1

DL1

PGND

DL2

SW2

BST2

FB2

VREG

BST3

SW3

FB3

PGND3

ALERT

BST4

SW4

FB4

PGND4

VREG

PVIN1

COMP1

EN1

PVIN2

COMP2

EN2

PVIN3

SS34

COMP3

EN3

VDDIO

PVIN4

COMP4

EN4

SCL

SDA

10µF

2.7nF 10kΩ

100kΩ

600kΩ

31.6kΩ

2.7nF 6.81kΩ

1.0µF

100µF

0.1µF

10µF

0.1µF

10µF C9

0.1µF

C10

22µF

C11

10µF

C12

0.1µF

C13

22µF

C14

1µF

C15

1µF

12V

VOUT1

VOUT3

1.2V/8A

1.5V/1.2A

3.3V/1.2A

2.5V/200mA

VOUT4

22kΩ

I2C

OPTIONAL

I2C INT E RFACE PWRGD

5V REG

EXPOSED PAD

SS12

1.0µF

VDD

CHANNEL 5

200mA LDO

REGULATOR FB5

EN5 VOUT5

VOUT5

ADP5050

CHANNEL 1

BUCK REGULAT OR

(1.2A/2.5A/4A)

CHANNEL 4

BUCK REGULAT OR

(1.2A)

C16

100µF

VREG

PVIN5

4.99kΩ

10kΩ

8.87kΩ

31.6kΩ

40.2kΩ

10.2kΩ

10kΩ

Si7232DN

(16.4mΩ)

10899-165

INT

Figure 68. Typical Channel 1/Channel 2 Parallel Output Application, 600 kHz Switching Frequency, Adjustable Output Model

Data Sheet ADP5050

Rev. B | Page 41 of 57

Table 19. Register Map

Address

Name

Reg. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0x00 Reserved Reserved

1 0x01 PCTRL Reserved CH5_ON CH4_ON CH3_ON CH2_ON CH1_ON

2 0x02 VID1 Reserved VID1[4:0]

3 0x03 VID23 Reserved VID3[2:0] Reserved VID2[2:0]

4 0x04 VID4 Reserved VID4[4:0]

0x05

DVS_CFG

Reserved

DVS4_ON

DVS4_INTVAL[1:0]

Reserved

DVS1_ON

DVS1_INTVAL[1:0]

6 0x06 OPT_CFG DSCG4_ON DSCG3_ON DSCG2_ON DSCG1_ON PSM4_ON PSM3_ON PSM2_ON PSM1_ON

7 0x07 LCH_CFG OVP4_ON OVP3_ON OVP2_ON OVP1_ON SCP4_ON SCP3_ON SCP2_ON SCP1_ON

8 0x08 SW_CFG FREQ3 FREQ1 PHASE4[1:0] PHASE3[1:0] PHASE2[1:0]

9 0x09 TH_CFG Reserved TEMP_TH[1:0] LVIN_TH[3:0]

10 0x0A HICCUP_CFG SYNC_OUT Reserved HICCUP4_

OFF

HICCUP3_

OFF

HICCUP2_

OFF

HICCUP1_

OFF

11 0x0B PWRGD_MASK Reserved MASK_CH4 MASK_CH3 MASK_CH2 MASK_CH1

12 0x0C LCH_STATUS Reserved TSD_LCH CH4_LCH CH3_LCH CH2_LCH CH1_LCH

13 0x0D STATUS_RD Reserved PWRG4 PWRG3 PWRG2 PWRG1

14 0x0E INT_STATUS Reserved TEMP_INT LVIN_INT PWRG4_INT PWRG3_INT PWRG2_INT PWRG1_INT

15 0x0F INT_MASK Reserved MASK_TEMP MASK_LVIN MASK_

PWRG4

MASK_

PWRG3

MASK_

PWRG2

MASK_

PWRG1

16 0x10 Reserved Reserved

17 0x11 DEFAULT_SET DEFAULT_SET[7:0]

ADP5050 Data Sheet

Rev. B | Page 42 of 57

DETAILED REGISTER DESCRIPTIONS

This section describes the bit functions of each register used by

the ADP5050. To reset a register, the internal VDD power-on

reset signals must be low, unless otherwise noted.

ADDRESS 0x01

channel. The on or off status of a channel is controlled by the

CHx_ON bit in this register and the external hardware enable

pin for the channel (logical AND). The default value of the

CHx_ON bit, 1, means that the channel enable is controlled by

the external hardware enable pin. The channel can be disabled

or enabled via the I2C interface only when the ENx pin is high.

Pulling the ENx pin low resets the corresponding CHx_ON bit

to the default value (1) to allow another valid startup when the

ENx pin is high again.

Table 20. Register 1 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved CH5_ON CH4_ON CH3_ON CH2_ON CH1_ON

Table 21. PCTRL Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:5] Reserved R/W Reserved.

4 CH5_ON R/W 0 = disable Channel 5 (EN5 pin must be high).

1 = enable Channel 5 (default).

3 CH4_ON R/W 0 = disable Channel 4 (EN4 pin must be high).

1 = enable Channel 4 (default).

2 CH3_ON R/W 0 = disable Channel 3 (EN3 pin must be high).

1 = enable Channel 3 (default).

1 CH2_ON R/W 0 = disable Channel 2 (EN2 pin must be high).

1 = enable Channel 2 (default).

0 CH1_ON R/W 0 = disable Channel 1 (EN1 pin must be high).

1 = enable Channel 1 (default).

Table 22. Register 2 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved VID1[4:0]

Table 23. VID1 Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:5]

Reserved

R/W

Reserved.

[4:0] VID1[4:0] R/W These bits set the output voltage for Channel 1. The default value is programmed by factory fuse.

00000 = 0.8 V (adjustable).

00001 = 0.85 V.

00010 = 0.875 V.

00011 = 0.9 V.

…

00111 = 1.0 V.

…

10011 = 1.3 V.

…

11011 = 1.5 V.

…

11110 = 1.575 V.

11111 = 1.6 V.

Data Sheet ADP5050

Rev. B | Page 43 of 57

Table 24. Register 3 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved VID3[2:0] Reserved VID2[2:0]

Table 25. VID23 Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

7 Reserved R/W Reserved.

[6:4] VID3[2:0] R/W These bits set the output voltage for Channel 3. The default value is programmed by factory fuse.

000 = 0.8 V (adjustable).

001 = 1.2 V.

010 = 1.3 V.

011 = 1.4 V.

100 = 1.5 V.

101 = 1.6 V.

110 = 1.7 V.

111 = 1.8 V.

3 Reserved R/W Reserved.

[2:0] VID2[2:0] R/W These bits set the output voltage for Channel 2. The default value is programmed by factory fuse.

000 = 0.8 V (adjustable).

001 = 3.3 V.

010 = 3.6 V.

011 = 3.9 V.

100 = 4.2 V.

101 = 4.5 V.

110 = 4.8 V.

111 = 5.0 V.

Table 26. Register 4 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved

VID4[4:0]

Table 27. VID4 Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:5] Reserved R/W Reserved.

[4:0] VID4[4:0] R/W These bits set the output voltage for Channel 4. The default value is programmed by factory fuse.

00000 = 0.8 V (adjustable).

00001 = 2.5 V.

00010 = 2.6 V.

…

00110 = 3.0 V.

…

10000 = 4.0 V.

…

11010 = 5.0 V.

…

11110 = 5.4 V.

11111 = 5.5 V.

ADP5050 Data Sheet

Rev. B | Page 44 of 57

Register 5 is used to configure dynamic voltage scaling (DVS) for Channel 1 and Channel 4 (see the Dynamic Voltage Scaling (DVS) section).

Table 28. Register 5 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved DVS4_ON DVS4_INTVAL[1:0] Reserved DVS1_ON DVS1_INTVAL[1:0]

Table 29. DVS_CFG Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

7 Reserved R/W Reserved.

6 DVS4_ON R/W 0 = disable DVS for Channel 4 (default).

1 = enable DVS for Channel 4.

[5:4] DVS4_INTVAL[1:0] R/W These bits configure the DVS interval for Channel 4.

00 = 62.5 µs (default).

01 = 31.2 µs.

10 = 15.6 µs.

11 = 7.8 µs.

3 Reserved R/W Reserved.

2 DVS1_ON R/W 0 = disable DVS for Channel 1 (default).

1 = enable DVS for Channel 1.

[1:0] DVS1_INTVAL[1:0] R/W These bits configure the DVS interval for Channel 1.

00 = 62.5 µs (default).

01 = 31.2 µs.

10 = 15.6 µs.

11 = 7.8 µs.

Data Sheet ADP5050

Rev. B | Page 45 of 57

OUTPUT DISCHARGE FUNCTION CONFIGURATION),

ADDRESS 0x06

discharge switch setting for Channel 1 to Channel 4. The

PSMx_ON bit setting for each channel is in effect when the

SYNC/MODE pin is high (or when SYNC/MODE is configured

as a clock input or output). When the SYNC/MODE pin is low,

all channels are forced to work in automatic PWM/PSM mode,

and the PSMx_ON settings in this register are ignored. The default

value for the output discharge function can be programmed by

factory fuse (output discharge function enabled or disabled for

all four buck regulators).

Table 30. Register 6 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DSCG4_ON DSCG3_ON DSCG2_ON DSCG1_ON PSM4_ON PSM3_ON PSM2_ON PSM1_ON

Table 31. OPT_CFG Register, Bit Function Descriptions

Bits Bit Name Access Description

7 DSCG4_ON R/W The default value is programmed by factory fuse.

0 = disable output discharge function for Channel 4.

1 = enable output discharge function for Channel 4.

6 DSCG3_ON R/W The default value is programmed by factory fuse.

0 = disable output discharge function for Channel 3.

1 = enable output discharge function for Channel 3.

5 DSCG2_ON R/W The default value is programmed by factory fuse.

0 = disable output discharge function for Channel 2.

1 = enable output discharge function for Channel 2.

4 DSCG1_ON R/W The default value is programmed by factory fuse.

0 = disable output discharge function for Channel 1.

1 = enable output discharge function for Channel 1.

3 PSM4_ON R/W This bit is ignored when the SYNC/MODE pin is low.

0 = enable forced PWM mode for Channel 4 (default).

1 = enable automatic PWM/PSM mode for Channel 4.

2 PSM3_ON R/W This bit is ignored when the SYNC/MODE pin is low.

0 = enable forced PWM mode for Channel 3 (default).

1 = enable automatic PWM/PSM mode for Channel 3.

1 PSM2_ON R/W This bit is ignored when the SYNC/MODE pin is low.

0 = enable forced PWM mode for Channel 2 (default).

1 = enable automatic PWM/PSM mode for Channel 2.

0 PSM1_ON R/W This bit is ignored when the SYNC/MODE pin is low.

0 = enable forced PWM mode for Channel 1 (default).

1 = enable automatic PWM/PSM mode for Channel 1.

ADP5050 Data Sheet

Rev. B | Page 46 of 57

AND OVERVOLTAGE LATCH-OFF CONFIGURATION),

ADDRESS 0x07

short-circuit protection (SCP) and overvoltage protection (OVP).

When the SCP or OVP latch-off function is enabled, the

CHx_LCH bit in Register 12 is set after an error condition

occurs (see the Latch-Off Protection section). The default value

for the SCP latch-off and OVP latch-off functions can be

programmed by factory fuse (SCP or OVP latch-off function

enabled or disabled for all four buck regulators).

Table 32. Register 7 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OVP4_ON OVP3_ON OVP2_ON OVP1_ON SCP4_ON SCP3_ON SCP2_ON SCP1_ON

Table 33. LCH_CFG Register, Bit Function Descriptions

Bits Bit Name Access Description

7 OVP4_ON R/W The default value is programmed by factory fuse.

0 = disable the OVP latch-off function for Channel 4.

1 = enable the OVP latch-off function for Channel 4.

6 OVP3_ON R/W The default value is programmed by factory fuse.

0 = disable the OVP latch-off function for Channel 3.

1 = enable the OVP latch-off function for Channel 3.

5 OVP2_ON R/W The default value is programmed by factory fuse.

0 = disable the OVP latch-off function for Channel 2.

1 = enable the OVP latch-off function for Channel 2.

4 OVP1_ON R/W The default value is programmed by factory fuse.

0 = disable the OVP latch-off function for Channel 1.

1 = enable the OVP latch-off function for Channel 1.

3 SCP4_ON R/W The default value is programmed by factory fuse.

0 = disable the SCP latch-off function for Channel 4.

1 = enable the SCP latch-off function for Channel 4.

2 SCP3_ON R/W The default value is programmed by factory fuse.

0 = disable the SCP latch-off function for Channel 3.

1 = enable the SCP latch-off function for Channel 3.

1 SCP2_ON R/W The default value is programmed by factory fuse.

0 = disable the SCP latch-off function for Channel 2.

1 = enable the SCP latch-off function for Channel 2.

0 SCP1_ON R/W The default value is programmed by factory fuse.

0 = disable the SCP latch-off function for Channel 1.

1 = enable the SCP latch-off function for Channel 1.

Data Sheet ADP5050

Rev. B | Page 47 of 57

Register 8 is used to configure the switching frequency for Channel 1 and Channel 3 and to configure the phase shift for Channel 2,

Channel 3, and Channel 4 with respect to Channel 1 (0˚). The default values for the Channel 1 and Channel 3 switching frequencies

can be programmed by factory fuse.

Table 34. Register 8 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FREQ3 FREQ1 PHASE4[1:0] PHASE3[1:0] PHASE2[1:0]

Table 35. SW_CFG Register, Bit Function Descriptions

Bits Bit Name Access Description

7 FREQ3 R/W The default value can be programmed by factory fuse.

0 = switching frequency for Channel 3 is the same as the master frequency set by the RT pin.

1 = switching frequency for Channel 3 is half the master frequency set by the RT pin.

6 FREQ1 R/W The default value can be programmed by factory fuse.

0 = switching frequency for Channel 1 is the same as the master frequency set by the RT pin.

1 = switching frequency for Channel 1 is half the master frequency set by the RT pin.

[5:4] PHASE4[1:0] R/W These bits configure the phase shift for Channel 4 with respect to Channel 1 (0°).

00 = 0° phase shift.

01 = 90° phase shift.

10 = 180° phase shift (default).

11 = 270° phase shift.

[3:2] PHASE3[1:0] R/W These bits configure the phase shift for Channel 3 with respect to Channel 1 (0°).

00 = 0° phase shift (default).

01 = 90° phase shift.

10 = 180° phase shift.

11 = 270° phase shift.

[1:0] PHASE2[1:0] R/W These bits configure the phase shift for Channel 2 with respect to Channel 1 (0°).

00 = 0° phase shift.

01 = 90° phase shift.

10 = 180° phase shift (default).

11 = 270° phase shift.

ADP5050 Data Sheet

Rev. B | Page 48 of 57

ADDRESS 0x09

Register 9 is used to configure the junction temperature overheat detection threshold and the low input voltage detection threshold.

When these thresholds are enabled, the TEMP_INT and LVIN_INT status bits in Register 14 are set if the thresholds are exceeded.

Table 36. Register 9 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved TEMP_TH[1:0] LVIN_TH[3:0]

Table 37. TH_CFG Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[7:6] Reserved R/W Reserved.

[5:4] TEMP_TH[1:0] R/W These bits set the junction temperature overheat threshold.

00 = temperature warning function disabled (default).

01 = 105°C.

10 = 115°C.

11 = 125°C.

[3:0] LVIN_TH[3:0] R/W These bits set the low input voltage detection threshold.

0000 = 4.2 V (default).

0001 = 4.7 V.

0010 = 5.2 V.

0011 = 5.7 V.

0100 = 6.2 V.

0101 = 6.7 V.

0110 = 7.2 V.

0111 = 7.7 V.

1000 = 8.2 V.

1001 = 8.7 V.

1010 = 9.2 V.

1011 = 9.7 V.

1100 = 10.2 V.

1101 = 10.7 V.

1110 = 11.2 V.

1111 = low input voltage warning function disabled.

Data Sheet ADP5050

Rev. B | Page 49 of 57

Register 10 is used to configure the SYNC/MODE pin as a synchronization input or output and to configure hiccup protection for each

channel. The default value for hiccup protection can be programmed by factory fuse (hiccup function enabled or disabled for all four

buck regulators).

Table 38. Register 10 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SYNC_OUT Reserved HICCUP4_OFF HICCUP3_OFF HICCUP2_OFF HICCUP1_OFF

Table 39. HICCUP_CFG Register, Bit Function Descriptions

Bits Bit Name Access Description

7 SYNC_OUT R/W The default value can be programmed by factory fuse.

0 = configure the SYNC/MODE pin as a clock synchronization input if a clock is connected (default).

1 = configure the SYNC/MODE pin as a clock synchronization output.

[6:4] Reserved R/W Reserved.

3 HICCUP4_OFF R/W The default value can be programmed by factory fuse.

0 = enable hiccup protection for Channel 4.

1 = disable hiccup protection for Channel 4 (short-circuit protection is disabled automatically).

2 HICCUP3_OFF R/W The default value can be programmed by factory fuse.

0 = enable hiccup protection for Channel 3.

1 = disable hiccup protection for Channel 3 (short-circuit protection is disabled automatically).

1 HICCUP2_OFF R/W The default value can be programmed by factory fuse.

0 = enable hiccup protection for Channel 2.

1 = disable hiccup protection for Channel 2 (short-circuit protection is disabled automatically).

0 HICCUP1_OFF R/W The default value can be programmed by factory fuse.

0 = enable hiccup protection for Channel 1.

1 = disable hiccup protection for Channel 1 (short-circuit protection is disabled automatically).

ADP5050 Data Sheet

Rev. B | Page 50 of 57

CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B

Channel 1 to Channel 4; when unmasked, a power-good failure

on any of these channels triggers the PWRGD pin. The output

of the PWRGD pin represents the logical AND of all unmasked

PWRGD signals; that is, the PWRGD pin is pulled low by any

PWRGD signal failure. There is a 1 ms validation delay time

before the PWRGD pin goes high. The default value for the

power-good mask configuration can be programmed by factory

fuse (mask function enabled or disabled for all four buck

regulators).

Table 40. Register 11 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved MASK_CH4 MASK_CH3 MASK_CH2 MASK_CH1

Table 41. PWRGD_MASK Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

[7:4] Reserved R/W Reserved.

3 MASK_CH4 R/W The default value can be programmed by factory fuse.

0 = mask power-good status of Channel 4.

1 = output power-good status of Channel 4 to the PWRGD pin.

2 MASK_CH3 R/W The default value can be programmed by factory fuse.

0 = mask power-good status of Channel 3.

1 = output power-good status of Channel 3 to the PWRGD pin.

1 MASK_CH2 R/W The default value can be programmed by factory fuse.

0 = mask power-good status of Channel 2.

1 = output power-good status of Channel 2 to the PWRGD pin.

0 MASK_CH1 R/W The default value can be programmed by factory fuse.

0 = mask power-good status of Channel 1.

1 = output power-good status of Channel 1 to the PWRGD pin.

Data Sheet ADP5050

Rev. B | Page 51 of 57

Register 12 contains latched fault flags for thermal shutdown and channel latch-off caused by an OVP or SCP condition. Latched flags are not

reset when the fault disappears but are cleared only when a 1 is written to the appropriate bit (provided that the fault no longer persists).

Table 42. Register 12 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved TSD_LCH CH4_LCH CH3_LCH CH2_LCH CH1_LCH

Table 43. LCH_STATUS Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:5] Reserved R/W Reserved.

4 TSD_LCH Read/

self-clear

0 = no thermal shutdown has occurred.

1 = thermal shutdown has occurred.

3 CH4_LCH Read/

self-clear

0 = no short-circuit or overvoltage latch-off has occurred on Channel 4.

1 = short-circuit or overvoltage latch-off has occurred on Channel 4.

2 CH3_LCH Read/

self-clear

0 = no short-circuit or overvoltage latch-off has occurred on Channel 3.

1 = short-circuit or overvoltage latch-off has occurred on Channel 3.

1 CH2_LCH Read/

self-clear

0 = no short-circuit or overvoltage latch-off has occurred on Channel 2.

1 = short-circuit or overvoltage latch-off has occurred on Channel 2.

CH1_LCH

Read/

self-clear

0 = no short-circuit or overvoltage latch-off has occurred on Channel 1.

1 = short-circuit or overvoltage latch-off has occurred on Channel 1.

The read-only Register 13 indicates the real-time status of the power-good signals for Channel 1 to Channel 4.

Table 44. Register 13 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved PWRG4 PWRG3 PWRG2 PWRG1

Table 45. STATUS_RD Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:4] Reserved R Reserved.

3 PWRG4 R 0 = Channel 4 power-good status is low (default).

1 = Channel 4 power-good status is high.

2 PWRG3 R 0 = Channel 3 power-good status is low (default).

1 = Channel 3 power-good status is high.

1 PWRG2 R 0 = Channel 2 power-good status is low (default).

1 = Channel 2 power-good status is high.

0 PWRG1 R 0 = Channel 1 power-good status is low (default).

1 = Channel 1 power-good status is high.

ADP5050 Data Sheet

Rev. B | Page 52 of 57

READBACK), ADDRESS 0x0E

junction temperature overheat warning, low input voltage warn-

ing, and power-good signal failure on Channel 1 to Channel 4.

When any of these unmasked events occur, the INT pin is

pulled low to indicate a fault condition. (Masking of these events

is configured in Register 15.) To determine the cause of the fault,

read this register. Latched flags are not reset when the fault dis-

appears but are cleared only when a 1 is written to the appropriate

bit or when all ENx pins = 0.

Table 46. Register 14 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved TEMP_INT LVIN_INT PWRG4_INT PWRG3_INT PWRG2_INT PWRG1_INT

Table 47. INT_STATUS Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:6] Reserved R/W Reserved.

5 TEMP_INT Read/

self-clear

This bit indicates whether the junction temperature threshold has been exceeded.

0 = junction temperature has not exceeded the threshold.

1 = junction temperature has exceeded the threshold.

4 LVIN_INT Read/

self-clear

This bit indicates whether the low voltage input threshold has been exceeded.

0 = low voltage input has not fallen below the threshold.

1 = low voltage input has fallen below the threshold.

3 PWRG4_INT Read/

self-clear

The power-good interrupt is masked when the part is initialized and during a normal shutdown.

0 = no power-good failure has been detected on Channel 4.

1 = power-good failure has been detected on Channel 4.

2 PWRG3_INT Read/

self-clear

The power-good interrupt is masked when the part is initialized and during a normal shutdown.

0 = no power-good failure has been detected on Channel 3.

1 = power-good failure has been detected on Channel 3.

1 PWRG2_INT Read/

self-clear

The power-good interrupt is masked when the part is initialized and during a normal shutdown.

0 = no power-good failure has been detected on Channel 2.

1 = power-good failure has been detected on Channel 2.

0 PWRG1_INT Read/

self-clear

The power-good interrupt is masked when the part is initialized and during a normal shutdown.

0 = no power-good failure has been detected on Channel 1.

1 = power-good failure has been detected on Channel 1.

Data Sheet ADP5050

Rev. B | Page 53 of 57

Register 15 is used to mask or unmask various warnings for use by the interrupt (INT) pin. When any bit in this register is masked, the

associated event does not trigger the INT pin.

Table 48. Register 15 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved MASK_TEMP MASK_LVIN MASK_PWRG4 MASK_PWRG3 MASK_PWRG2 MASK_PWRG1

Table 49. INT_MASK Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:6] Reserved R/W Reserved.

5 MASK_TEMP R/W 0 = temperature overheat warning does not trigger the interrupt pin (default).

1 = temperature overheat warning triggers the interrupt pin.

4 MASK_LVIN R/W 0 = low voltage input warning does not trigger the interrupt pin (default).

1 = low voltage input warning triggers the interrupt pin.

3 MASK_PWRG4 R/W 0 = power-good warning on Channel 4 does not trigger the interrupt pin (default).

1 = power-good warning on Channel 4 triggers the interrupt pin.

2 MASK_PWRG3 R/W 0 = power-good warning on Channel 3 does not trigger the interrupt pin (default).

1 = power-good warning on Channel 3 triggers the interrupt pin.

MASK_PWRG2

R/W

0 = power-good warning on Channel 2 does not trigger the interrupt pin (default).

1 = power-good warning on Channel 2 triggers the interrupt pin.

0 MASK_PWRG1 R/W 0 = power-good warning on Channel 1 does not trigger the interrupt pin (default).

1 = power-good warning on Channel 1 triggers the interrupt pin.

The write-only Register 17 is used to reset all registers to their default values.

Table 50. Register 17 Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DEFAULT_SET[7:0]

Table 51. DEFAULT_SET Register, Bit Function Descriptions

Bits Bit Name Access Description

[7:0] DEFAULT_SET[7:0] W To reset all registers to their default values, write 0x7F to this register.

ADP5050 Data Sheet

Rev. B | Page 54 of 57

FACTORY PROGRAMMABLE OPTIONS

Table 52 through Table 65 list the options that can be programmed into the ADP5050 when it is ordered from Analog Devices. For a list

of the default options, see Table 66. To order a device with options other than the default options, contact your local Analog Devices sales

or distribution representative.

Table 52. Output Voltage Options for Channel 1 (Fixed Output Options: 0.85 V to 1.6 V in 25 mV Increments)

Option Description

Option 0 0.8 V adjustable output (default)

Option 1 0.85 V fixed output

Option 2 0.875 V fixed output

… …

Option 30 1.575 V fixed output

Option 31 1.6 V fixed output

Table 53. Output Voltage Options for Channel 2 (Fixed Output Options: 3.3 V to 5.0 V in 300 mV/200 mV Increments)

Option Description

Option 0 0.8 V adjustable output (default)

Option 1 3.3 V fixed output

Option 2 3.6 V fixed output

Option 3 3.9 V fixed output

Option 4 4.2 V fixed output

Option 5 4.5 V fixed output

Option 6 4.8 V fixed output

Option 7 5.0 V fixed output

Table 54. Output Voltage Options for Channel 3 (Fixed Output Options: 1.2 V to 1.8 V in 100 mV Increments)

Option Description

Option 0 0.8 V adjustable output (default)

Option 1 1.2 V fixed output

Option 2 1.3 V fixed output

Option 3 1.4 V fixed output

Option 4 1.5 V fixed output

Option 5

1.6 V fixed output

Option 6 1.7 V fixed output

Option 7 1.8 V fixed output

Table 55. Output Voltage Options for Channel 4 (Fixed Output Options: 2.5 V to 5.5 V in 100 mV Increments)

Option

Description

Option 0 0.8 V adjustable output (default)

Option 1 2.5 V fixed output

Option 2 2.6 V fixed output

… …

Option 30 5.4 V fixed output

Option 31 5.5 V fixed output

Table 56. Pin 20—PWRGD/A0 Pin Options

Option Description

Option 0 PWRGD pin for power-good output (default)

Option 1 A0 pin for I2C address setting

Data Sheet ADP5050

Rev. B | Page 55 of 57

Table 57. PWRGD Output Options

Option Description

Option 0 No monitoring of any channel

Option 1 Monitor Channel 1 output (default)

Option 2 Monitor Channel 2 output

Option 3 Monitor Channel 1 and Channel 2 outputs

Option 4 Monitor Channel 3 output

Option 5 Monitor Channel 1 and Channel 3 outputs

Option 6 Monitor Channel 2 and Channel 3 outputs

Option 7 Monitor Channel 1, Channel 2, and Channel 3 outputs

Option 8 Monitor Channel 4 output

Option 9 Monitor Channel 1 and Channel 4 outputs

Option 10 Monitor Channel 2 and Channel 4 outputs

Option 11 Monitor Channel 1, Channel 2, and Channel 4 outputs

Option 12 Monitor Channel 3 and Channel 4 outputs

Option 13 Monitor Channel 1, Channel 3, and Channel 4 outputs

Option 14 Monitor Channel 2, Channel 3, and Channel 4 outputs

Option 15

Monitor Channel 1, Channel 2, Channel 3, and Channel 4 outputs

Table 58. Output Discharge Functionality Options

Option Description

Option 0 Output discharge function disabled for all four buck regulators

Option 1 Output discharge function enabled for all four buck regulators (default)

Table 59. Switching Frequency Options for Channel 1

Option

Description

Option 0 1 × switching frequency set by the RT pin (default)

Option 1 ½ × switching frequency set by the RT pin

Table 60. Switching Frequency Options for Channel 3

Option Description

Option 0 1 × switching frequency set by the RT pin (default)

Option 1 ½ × switching frequency set by the RT pin

Table 61. Pin 43—SYNC/MODE Pin Options

Option

Description

Option 0 Forced PWM/automatic PWM/PSM mode setting with the ability to synchronize to an external clock (default)

Option 1 Generate a clock signal equal to the master frequency set by the RT pin

Table 62. Hiccup Protection Options for the Four Buck Regulators

Option Description

Option 0 Hiccup protection enabled for overcurrent events (default)

Option 1 Hiccup protection disabled; frequency foldback protection only for overcurrent events

Table 63. Short-Circuit Latch-Off Options for the Four Buck Regulators

Option Description

Option 0 Latch-off function disabled for output short-circuit events (default)

Option 1

Latch-off function enabled for output short-circuit events

ADP5050 Data Sheet

Rev. B | Page 56 of 57

Table 64. Overvoltage Latch-Off Options for the Four Buck Regulators

Option Description

Option 0 Latch-off function disabled for output overvoltage events (default)

Option 1 Latch-off function enabled for output overvoltage events

Table 65. I2C Address Options

Option

Description

Option 0 0x48 (default)

Option 1 0x58

Option 2 0x68

Option 3 0x78

FACTORY DEFAULT OPTIONS

Table 66 lists the factory default options programmed into the ADP5050 when the device is ordered (see the Ordering Guide). To order

the device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 52

through Table 65 list all available options for the device.

Table 66. Factory Default Options

Option Default Value

Channel 1 Output Voltage 0.8 V adjustable output

Channel 2 Output Voltage 0.8 V adjustable output

Channel 3 Output Voltage 0.8 V adjustable output

Channel 4 Output Voltage 0.8 V adjustable output

PWRGD Pin (Pin 20) Function PWRGD pin for power-good output

PWRGD Pin (Pin 20) Output Monitor Channel 1 output

Output Discharge Function Enabled for all four buck regulators

Switching Frequency on Channel 1 1 × switching frequency set by the RT pin

Switching Frequency on Channel 3 1 × switching frequency set by the RT pin

SYNC/MODE Pin (Pin 43) Function Forced PWM/automatic PWM/PSM mode setting with the ability to synchronize to an external clock

Hiccup Protection Enabled for overcurrent events

Short-Circuit Latch-Off Function Disabled for output short-circuit events

Overvoltage Latch-Off Function Disabled for output overvoltage events

C Address

0x48

Data Sheet ADP5050

Rev. B | Page 57 of 57

OUTLINE DIMENSIONS

0.50

BSC

BOTTOM VIEW

TOP VIEW

PIN 1

INDICATOR

EXPOSED

PAD

PIN 1

INDICATOR

*5.70

5.60 SQ

5.50

0.50

0.40

0.30

SEATING

PLANE

0.80

0.75

0.70 0. 05 MAX

0.02 NO M

0.203 REF

COPLANARITY

0.08

0.30

0.25

0.20

10-24-2013-D

7.10

7.00 SQ

6.90

FOR PRO P E R CONNECTI ON OF

THE EXPOSED PAD, REFER TO

THE PIN CO NFI GURAT ION AND

FUNCTION DES CRIPTIONS

SECTION OF THIS DATA SHEET.

0.20 M IN

*COM P LIANT T O JEDE C S TANDARDS M O -220-W KKD- 2

WIT H THE EXCEPTIO N OF T HE EXPOSED PAD DIMENSION.

Figure 69. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

7 mm × 7 mm Body, Very Very Thin Quad

(CP-48-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option2

ADP5050ACPZ-R7 −40°C to +125°C 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-48-13

ADP5050-EVALZ Evaluation Board

1 Z = RoHS Compliant Part.

2 Table 66 lists the factory default options for the device. For a list of factory programmable options, see the Factory Programmable Options section. To order a device

with options other than the default options, contact your local Analog Devices sales or distribution representative.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D10899-0-9/15(B)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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ADP5050ACPZ-R7 ADP5050-EVALZ