INTEGRATED CIRCUITS DATA SHEET For 4 complete data sheet, bisase also download: es The iOO8 7ahC/NCT/NCU/NCMOS Logic Farnly Specifications s The [O06 74h T/NCLYNCMOS Logic Package Information e The 106 74hCHOTNCUVNCMOS Logic Package Quilines 74HC/HCT40103 8-bit synchronous binary down counter Product specification 1998 Jul 08 Supersedes data of December 1990 File under Integrated Circuits, ICO6 CAE ctor & PHILIPSPhilips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 FEATURES Cascadable Synchronous or asynchronous preset Output capability: standard leg category: MSI GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the 40103 of the 4000B series. They are specified in compliance with JEDEG standard no. 7A. The 74HC/HGCT40103 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The 40103 contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; th = = 6 ns Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock pericd. When the synchronous preset enable input (PE) is LOW, data at the jam input (Pg to Pz) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (Pg to Pz) is asynchronously forced into the counter regardless of the state of PE, TE, or GP. The jam inputs (Po to Pz) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table. if all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. The 40103 may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. TYPICAL SYMBOL | PARAMETER CONDITIONS UNIT Hc HCT tpH/ tpt | propagation delay CP to TC CL=15pF; Vec=5V 30 30 ns Fax maximum clock frequency 32 31 MHz C| input capacitance 3.5 3.5 pF Cpp power dissipation capacitance per package | notes 1 and 2 24 27 pF Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in wW): Pp = Cep x Veo? x ff HE (CL x Voc? x fo} where: fj = input frequency in MHz fo = output frequency in MHz E (CL x Veco? x fp) = sum of outputs C_ = output load capacitance in pF Voc = supply voltage in V For HC the condition is V; = GND to Vee For HCT the condition is V) = GND to Veg 1.5V nm 1998 Jul 08Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION 74HC40103N; DIP16 | plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HGT40103N 74HC40103D; SO16 = | plastic small cutline package; 16 leads; body width 3.9 mm SOT109-14 74HGT40103D 74HC40103DB; | SSOP16 | plastic shrink small outline package; 16 leads; body width 5.38 mm SOT338-1 74HGT40103DB 74HC40103PW; | TSSOP16| plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 CP clock input (LOW-to-HIGH, edge-triggered} 2 MR asynchronous master reset input (active LOW} 3 TE terminal enable input 4,5,6,7,10,11,12,13 | Po to Pz jam inputs 8 GND ground (9 V) g PL asynchronous preset enable input (active LOW) 14 TC terminal count output (active LOW} 15 PE synchronous preset enable input (active LOW) 16 Voc positive supply voltage 1a3 2 cTRa inter. crf U 18] Yee Lod one. _ cP PL TE 15 MAL 2 15 | PE 4p Day a2 5] , 2 ent TE} 3 14] Tc Bm Py oa \Za- Po ic rag] 7 2 2c3 q 40103 Pa pif] a] Ps rolea TC }o 14 Fo [| 11] Ps 11 -4 Ps 8 7 3 QI 19} *4 a1" 10 | SET serao palt 1g9]P7 tt cno [a | nin PE OMA a Feas7aa ba ? it 7 15 2 7Z939740 rrsagt Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEG logic symbol. 1998 Jul 08Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 cP ml o las jw ju an El |e fr | cs] > Po {Py Po [Ps [Pa [Pa Pe jP7 7zea7al 4 (5 Fig.4 Functional diagram. FUNCTION TABLE CONTROL INPUTS PRESET MODE | ACTION MR PL PE TE H H H H inhibit counter H H H L synchronous count down H H L x preset on next LOW-to HIGH clock transition H L x x preset asynchronously asynchronous - L Xx x X clear to maximum count Note 1. Clock connected to GP. Synchronous operation: changes occur on the LOW-to-HIGH GP transition. Jam inputs: MSD = P;, LSD = Pp. H = HIGH voltage level L = LOW voltage level X = don't care APPLICATIONS Divide-by-n counters Programmable timers Interrupt timers Cycle/program counters 1998 Jul 08Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 7 7 =? 8 sa | [TT Te To avin 7 i Vv f # ae FEaIa?.3 L Py | Py | Po Pa Pa Ps Pa Py al COUNT | 255 | 254 a 2 ' 0 255 | 254 | 254 |253 a ? 6 5 4 255 | 284 | 263 | 252 7Z9374 Fig.6 Timing diagram. 1998 Jul 08 5Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 DC CHARACTERISTICS FOR 74HC tet Lee ES iesieek For the DC characteristics see 744I0HC PAMCUAICMOS Lowe Farviy Soecticagtons Output capability: standard log category: MS! AC CHARACTERISTICS FOR 74HC GND =0V; t, =f =6 ns; C_ = 50 pF Tamb (C) TEST CONDITIONS T4HC SYMBOL | PARAMETER UNIT Voc WAVEFORMS +25 40 to +85 | 40 to +125 (V) min. | typ. | max. | min. | max. | min. | max. tpHL/ tpLH | propagation delay 96 | 300 375 450 [ns 2.0 | Fig.7 CP to TC 35 |60 75 90 45 28 [51 64 vi 6.0 tpHi/ tpl | propagation delay 50 |175 220 265 [ns 2.0 | Fig. 8 TE to TG 18 [35 44 53 45 14 |30 37 45 6.9 tpHL/ tpLH | propagation delay 102 |315 395 475 |ns 2.0 | Fig.S PL to TC 37 |63 79 95 45 30 | 53 40 81 6.0 tPHL propagation delay 83 | 275 345 415 |ns 2.0 | Figg MR to TC 30 |55 69 83 45 24 |47 59 71 6.0 tro trLH | output transition time 19 | 75 95 110 ns 2.0 | Figs 7 and 8 7 16 19 22 4.5 6 13 16 19 6.0 tw clock pulse width 165 | 22 205 250 ns 2.0 | Fig.7 HIGH or LOW 33 3 41 50 45 28 6 35 43 6.0 tw master reset pulse width [125 | 39 155 190 ns 2.0 | Fig.9 LOW 25 | 14 31 38 45 21 11 26 32 6.0 tw preset enable pulse width | 125 | 33 155 190 ns 2.0 | Fig. PL, LOW 25 | 12 31 38 45 21 10 26 32 6.9 trem removal time __ 50 14 65 75 ns 2.0 | Fig.10 MRtoCPorPLtoCP |yq |5 13 15 45 9g 4 11 13 6.0 teu set-up time 75 | 22 95 110 ns 2.0 | Fig.11 PE to GP 15 |8 19 22 45 13 1/6 16 19 6.9 1998 Jul 08 6Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT Voc WAVEFORMS 425 40 to +85 | 40 to +125 (Vv) min. | typ. | max. | min. | max. | min. | max. tsu setup time 150 | 44 190 225 ns 2.0 | Fig.11 TE to CP 30 |16 38 45 45 26 13 33 38 6.0 tsu setup time 75 | 22 95 110 ns 2.0 | Fig.12 Pn to CP 15 |8 19 22 45 13 6 16 19 6.0 th hold time 0 14 0 0 ns 2.0 | Fig.11 PE to CP 0 |-5 0 0 45 0 4 0 0 6.0 th hold time 0 30 0 0 ns 2.0 | Fig.11 TE to CP 0 |-11 0 0 45 0 9 0 0 6.0 th hold time 0 -17 0 0 ns 2.0 | Fig.12 P, to CP o |-6 0 0 45 0 5 0 0 6.0 frax maximum clock pulse 3.0 | 10 24 2.0 MHz |2.0 | Fig.7 frequency 15 |29 12 10 45 18 |35 14 12 6.0 1998 Jul 08 7Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 744I0HC PAMCUAICMOS Lowe Farviy Soecticagtons Output capability: standard log category: MS! Note to HCT types The value of additional quiescent supply current (Alcc) for a unit load of 1 is given in the family specifications. To determine Alcc per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT CP PE 1.50 MR 1.00 TE 0.80 PL 0.35 P, 0.25 AC CHARACTERISTICS FOR 74HCT GND =0V; t, =t =6 ns; C_ = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT Voc WAVEFORMS +25 40 to +85 | 40 to +125 (Vv) min. | typ. | max. | min. | max. | min. | max. tpHL/ tpLH | propagation delay 35 | 60 75 90 ns 45 |Fig.7 CP to TC teu tpt propagation delay 23 | 40 50 60 ns 45 |Fig.8 TE to TG tpHL/ tel | propagation delay 44 |75 94 112 ns 45 |Fig9 PL to TC tPHL propagation delay 29 | 55 69 83 ns 45 | Figg MR to TG tro/trty | output transition time 7 15 19 22 ns 45 |Figs. 7 and 8 ty clock pulse width 33 10 41 50 ns 45 |Fig7 HIGH or LOW tw master reset pulse width | 30 16 38 45 ns 45 | Figg LOW tw preset enable pulse width |}38 | 22 48 57 ns 45 | Figg PL; LOW trem removal time __ 10 1 13 15 ns 45 | Fig.10 MR to GP or PLto CP tsu set-up time 20 11 25 30 ns 45 | Fig.11 PE to GP tsu set-up time 40 |20 50 60 ns 45 | Fig.11 TE te CP 1998 Jul 08 8Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | y,, | WAVEFORMS +25 40 to +85 | 40 to +125 (Vv) min. | typ. | max. | min. | max. | min. | max. tsu setup time 20 11 25 30 ns 45 |Fig.12 P, to GP th hold time 2 -3 2 2 ns 45 |Fig.11 PE to GP th hold time 0 10 0 0 ns 45 |Fig.11 TE to CP th hold time 0 5 0 0 ns 45 |Fig.12 P, to GP Fmax maximum clock pulse 15 |28 12 10 MHz |4.5 | Fig.7 frequency 1998 Jul 08 9Philips Semiconductors 8-bit synchronous binary down counter AC WAVEFORMS Product specification 74HC/HCT 40103 cP INPUT Te oUTeUT TEBA744 THLE (1) HC : Vu = 50%; Vi = GND to Vee. HOT: Vy = 1.3 V; Vj = GND to 3 V. Fig.? Waveforms showing the clock input (CP) to TC propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. TE INPUT E outeut TZGITAG (1) HG : Vy = 50%: V) = GND to Voc. HCT: Vy = 1.3 VV) =GND to3 V. Fig.8 Waveforms showing the TE to TC propagation delays. Py PL. MR INPUT Te OUTPUT F2OS EF (1) HG : Vy = 50%; V, = GND to Vee. HOT: Vy = 1.3 V; V)= GND to 3 V. Fig.9 Waveforms showing PL, MR, P,to TC PL, MA INPUT Vigil jo ty oP GUTPUT Vy? PESTIIGT (1) HG : Vy = 50%; V) = GND to Voc. HOT: Vy =1.3 V: V; = GND to3 V. Fig.10 Waveforms showing removal time for TE of PE INPUT vy atte bg oy {_,}- CP INPUT yi TZ93748 (1) HC : Vy = 50%; V, = GND to Vee. HCT: Vy = 1.3 V; V)= GND to 3 V. Fig.11 Waveforms showing hold and set-up times for MR or PE to CP. propagation delays. MR and PL. LH Pg a Py Maat? able Yj INPUTS d PE INPUT a ty ee GP INPUT f Ve 7z93740 The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HO : Vy = 50%; V| = GND to Vec. HOT: Vy = 1.3 V; V| = GND to 3 V. tn Fig.12 Waveforms showing hold and set-up times for Ph, PE te CP. 1998 Jul 08 10Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 APPLICATION INFORMATION Vee Veco Fo Tc 10% TE FE | time-out N ; PL | t baa : _ : MR start F cP L GND tim - ft re2zeis Fig.18 Programmable timer. oc _Ip To i. 2 JIN 0 OUT ~ N+I ~ TE _ PE N= 40103 pp L4 _ MRE P, cP tin GND MGA836 ern Fig.14 Divide-by-N counter. 1998 Jul 08 11Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 PACKAGE OUTLINES DIP 16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 at D oo > Mp _ | seating plane 1 1 I I 1 4 od | < i? pin 1 index 1 8 0 5 10mm daa scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ao 43 1} zy UNIT | ay | omin. | mie b by c pi E! e e L Me | My w ex. 140 | 053 | 0.32 | 21.8 | 648 39 8.25 95 mm 47) O51 37 | 444 | o38 | o23 | 214 | 620 | 254 | 782 | 34 | 790 | 33 | 0754 |) 22 . 0.055 | 0.021 | 0.013 | o86 | o26 015 | 0.32 | 0.37 inches | 0.19 | 0.020] 0.15 | Kare | gois | ooog | os4 | ona | 219 | 939 | ys | ost | ggg | 201 | 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT36-1 050G09 MO-001 AE on seat 1998 Jul 08 12Philips Semiconductors 8-bit synchronous binary down counter $016: plastic small outline package; 16 leads; body width 3.9 mm Product specification 74HC/HCT 40103 $SOT109-1 |? 16 AAA AA po LN ef | _ _ _ _ |p Ap | pin 1 index t { | Ly 7 et OL p H H f f | H H H H. Lo oo [a] be ool Lew p 0 2.5 5mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | wax. | MH Az | As bp c pM) | EM) | e He L Lp Q v w y | Zz) ao 0.25 | 1.45 049 | 0.25 | 100] 40 6.2 1.0 | 07 0.7 mm 1-75) gig | 12519 | oss} o19| a8 | 38 | 17 | 58) 1] o4 | o6 | 975) 975) 91 | 3 | go . 0.010 | 0.057 0.019 /0.0100] 0.39 | 0.16 0.244 0.039 | 0.028 0.028] inches | 0.069 | 9 494 | 9.049 | 9-9! | 0.014 /0.0075| 0.38 | 0.15 | 259] 0.208 | 9-41 | gore | o.020 | 9-07 | 9-01 | 0.004) 4 gy, Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC EIAJ -95-04-23- SOT109-1 076E07S MS-012AC E} or one 13 1998 Jul 08Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm $0T333-1 ________ p ___ + E ~p> a) al 7 of \ T \ | t \ MY _ | c r = ly He rl+[s ae) Fa ARARA AAA ! I | | 1 | : | : | ios ----+---F Ay Pt (Aa) A a | 4 pin 1 index + t 1 | h8 Cy IL | f | P T |_| HHH UI HWE ' | Le a + Ww (M) p 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) UNIT mo Ay | Ay | Ag | bp | c | DM) EM | e@ | He | L | bp | @ v w y | z) 9 0.21 | 1.80 0.38 | 0.20 | 64 | 54 79 1.03 | og 1.00 | 98 mm) 20) gos | 165 9 | o25 | o09 | 60 | 52 | 288) 76 [175 | oes] o7 | OF 913] OT | ges | go Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC FIAJ PROJECTION ISSUE DATE SOT338-1 MO-150AC } oe ee od 1998 Jul 08 14Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm $OT403-1 D - 4 ___ +p {a I a __ (EEE I NX uw Oly] He Fle fe] v OA ALAA ual fH | f {|} ha FS yr Ho TS, | | Loe I << | 1 1 8 detail X le | ewe . Qo 2.5 5mm La | scale DIMENSIONS (mm are the original dimensions) A UNIT | way. | Ar | Az | As | Bp e pM) | 2) | He L Lp Qa v w y Z| 49 015 | 0.95 0.30 0.2 5.1 45 66 0.75 o4 0.40 & mm 1.10 0.05 | 0.80 0.25 0.19 o4 4.9 43 0.65 6.2 1.0 0.50 0.3 0.2 0.13 o4 0.06 a Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION pRovecTION | 'SSUE DATE IEC JEDEC EIAJ SOT403-1 MO-153 Et 95-04-04 1998 Jul 08 15Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook 1C26; Integrated Circuit Packages (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T sig max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Jul 08 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). * Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.Philips Semiconductors Product specification 8-bit synchronous binary down counter 74HC/HCT 40103 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jul 08 17