PRELIMINARY CY62137V MoBLTM 128K x 16 Static RAM disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Features * Low voltage range: -- 1.8V-3.3V * Ultra-low active, standby power * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O15) is written into the location specified on the address pins (A0 through A16). Functional Description The CY62137V is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBLTM) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselectected (CE HIGH) or when CE is LOW and both BLE and BHE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62137V MoBL SRAM has an extremely wide operating voltage range. This data sheet has been specified to accurately describe the device behavior at three common voltage ranges (3.3-2.7, 2.7-2.3, 2.3-1.8) The CY62137V is available in 48-ball FBGA and standard 44-pin TSOP Type II (forward pinout) packaging. Logic Block Diagram Pin Configurations TSOP II (Forward) Top View SENSE AMPS A9 A8 A7 A6 A5 A4 A3 A2 ROW DECODER DATA IN DRIVERS 128K x 16 RAM Array A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 I/O0 - I/O7 I/O8 - I/O15 A1 A0 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 62137V-2 CE Power Down Circuit BHE BLE A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 62137V-1 MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 July 29, 1999 PRELIMINARY CY62137V MoBL Pin Configuration 48-Ball FBGA 1 2 3 Top View 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H 62137V-3 DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. -65C to +150C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied ............................................... 55C to +125C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V Ambient Temperature VCC -40C to +85C 1.8V to 3.3V Industrial Product Portfolio Power Dissipation (Commercial) Product VCC Range Operating(Icc) Min. Typ.[2] Speed Typ.[2] Max. CY62137V 2.7V 3.0V CY62137V 2.3V 2.5V 3.3V 70 ns 2.7V 85 ns CY62137V 1.8V 2.0V 2.3V 100 ns Shaded area contains advance information. 2 Standby (ISB2) Max. Typ.[2] Max 7 15mA 1 A 15 A 5 10mA 12 A 3 7mA 10 A PRELIMINARY CY62137V MoBL Electrical Characteristics Over the Operating Range CY62137V Parameter VOH VOL VIH VIL Description Test Conditions Output HIGH Voltage Output LOW Voltage Min. Typ.[2] Max. Unit IOH = -1.0 mA VCC = 2.7V 2.4 V IOH = -0.1 mA VCC = 2.3V 2.0 V IOH = -0.1 mA VCC = 1.8V 1.5 V IOL = 2.1 mA VCC = 2.7V 0.4 V IOL = 0.1 mA VCC = 2.3V 0.4 V IOL = 0.1 mA VCC = 1.8V 0.2 V Input HIGH Voltage Input LOW Voltage VCC = 3.3V 2.2 VCC +0.5V V VCC = 2.7V 2.0 VCC +0.5V V VCC = 2.3V 1.4 VCC +0.3V V VCC = 2.7V -0.5 0.8 V VCC = 2.3V -0.5 0.6 V VCC = 1.8V -0.5 0.4 V IIX Input Load Current GND < VI < VCC -1 +1 +1 A IOZ Output Leakage Current GND < VO < VCC, Output Disabled -1 +1 +1 A ICC VCC Operating Supply Current IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels VCC = 3.3V 7 15 mA VCC = 2.7V 5 10 mA VCC = 2.3V 3 7 mA 1 2 mA 100 uA IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current-- CMOS Inputs CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMAX ISB2 Automatic CE Power-Down Current-- CMOS Inputs CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 L 1 50 uA VCC = 3.3V LL 1 15 uA VCC= 2.7V LL 1 12 uA VCC = 2.3V LL 1 10 uA 9 Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. Unit 6 pF 8 pF Shaded areas contains advance information. Note: 1. VIL(min) = -2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25C. 3. Tested initially and after any design or process changes that may affect these parameters. 3 PRELIMINARY CY62137V MoBL AC Test Loads and Waveforms R1 R1 VCC ALL INPUT PULSES VCC OUTPUT VCC Typ OUTPUT INCLUDING JIG AND SCOPE Equivalent to: R2 5 pF R2 30 pF 10% GND < 5 ns < 5 ns INCLUDING JIG AND SCOPE (a) 90% 10% 90% (b) C62137V-5 C62137V-4 THEVENIN EQUIVALENT RTH OUTPUT V Parameters 3.0V 2.5V 2.0V UNIT R1 1105 16670 15294 Ohms R2 1550 15380 11300 Ohms RTH 645 8000 6500 Ohms VTH 1.75V 1.2V 0.85V Volts Shaded areas contain advance information. Data Retention Characteristics (Over the Operating Range) Parameter Conditions[4] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR Operation Recovery Time Min. Typ.[2] 1.0 VCC = 1.0V CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V No input may exceed VCC+0.3v L/ LL 0.1 Max. Unit 3.3 V 1 A 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 1.6V VDR > 1.0 V 1.6V tR tCDR CE C62137V-6 Note: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30 pF load capacitance. 4 PRELIMINARY CY62137V MoBL Switching Characteristics Over the Operating Range[4] (2.7V-3.3V Operation) Parameter Description Min. Max. (2.3V-2.7V Operation) Min. Max. (1.8V-2.3V Operation) Min. Max. Unit READ CYCLE tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 85 100 ns tDOE OE LOW to Data Valid 35 50 75 ns [5 tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[5, 6] tLZCE [5] CE LOW to Low Z 85 70 10 100 85 10 5 10 25 ns 50 10 ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 70 85 100 ns tDBE BHE / BLE LOW to Data Valid 70 85 100 ns tLZBE BHE / BLE LOW to Low Z tHZBE BHE / BLE HIGH to High Z 0 35 ns ns 5 35 10 [5, 6] 100 10 5 25 ns 0 10 0 10 25 50 ns 10 35 ns ns 50 ns WRITE CYCLE[7, 8] tWC Write Cycle Time 70 85 100 ns tSCE CE LOW to Write End 60 75 90 ns tAW Address Set-Up to Write End 60 75 90 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 50 65 80 ns tSD Data Set-Up to Write End 30 50 60 ns tHD Data Hold from Write End 0 0 0 ns WE LOW to High Z [5, 6] tLZWE WE HIGH to Low Z [5] tBW BHE / BLE LOW to End of Write tHZWE 25 35 50 ns 10 10 10 ns 60 75 90 ns Shaded areas contain advance information. Notes: 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. t HZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 PRELIMINARY CY62137V MoBL Switching Waveforms Read Cycle No. 1 [9, 10] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID C62137V-7 Read Cycle No. 2 [10, 11] tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB C62137V-8 Notes: 9. Device is continuously selected. OE, CE=VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 6 PRELIMINARY CY62137V MoBL Switching Waveforms (continued) [7, 12, 13] Write Cycle No. 1 (WE Controlled) tWC ADDRESS CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O NOTE 14 tHD DATAIN VALID tHZOE Write Cycle No. 2 (CE Controlled) C62137V-9 [7, 12, 13] tWC ADDRESS tSCE CE tSA tAW BHE/BLE WE tHA tBW tPWE tSD DATA I/O tHD DATAIN VALID C62137V-10 Notes: 12. Data I/O is high impedance if OE = VIH. 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 7 PRELIMINARY CY62137V MoBL Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [8, 13] tWC ADDRESS CE tAW tBW BHE/BLE WE tHA tSA tSD DATA I/O tHD DATAIN VALID NOTE 14 tLZWE tHZWE C62137V-11 Note: 14. During this period, the I/Os are in output state and input signals should not be applied. 8 PRELIMINARY CY62137V MoBL Typical DC and AC Characteristics NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE STANDBY CURRENT vs. AMBIENT TEMPERATURE 1.0 1.4 3.0 I CC 0.8 0.6 VIN =VCC typ. TA =25C 0.4 2.5 TA =25C 0.75 0.5 ISB 1.5 1.0 0.5 0.25 0.2 0.0 0 0.0 1.7 2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 -0.5 -55 3.7 NORMALIZED STANDBY CURRENT vs. SUPPLY VOLTAGE NORMALIZED I CC vs. CYCLE TIME NORMALIZED ICC 1.2 ISB2 1.0 0.8 VIN =VCC typ. TA =25C 0.4 105 1.50 1.4 0.6 25 AMBIENT TEMPERATURE (xC) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) NORMALIZED ISB VCC =VCC typ. VIN =VCC typ. 2.0 ISB2 mA 1.0 NORMALIZED t AA NORMALIZED ICC , 1.2 VCC =3.3V TA =25C 1.00 0.50 0.2 0.0 1.0 0.10 3.7 2.8 1.9 5 1 15 10 CYCLE FREQUENCY (MHz) SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE H X X X X High Z Inputs/Outputs Deselect/Power-Down L X X H H High Z Deselect/Power-Down Standby (ISB) Standby (ISB) L H L L L Data Out (I/OO-I/O15) Read Active (ICC) L H L H L Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8-I/O 15); I/O0 -I/O7 in High Z Read Active (ICC) L H H L L High Z Deselect/Output Disabled Active (ICC) L H H H L High Z Deselect/Output Disabled Active (ICC) L H H L H High Z Deselect/Output Disabled Active (ICC) L L X L L Data In (I/OO-I/O15) Write Active (ICC) L L X H L Data In (I/OO-I/O7); I/O8 - I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Write Active (ICC) 9 Mode Power PRELIMINARY CY62137V MoBL Ordering Information Speed (ns) 70 70 Ordering Code CY62137VL-70ZI Package Name Z44 CY62137VL-70BAI BA48 CY62137VLL-70ZI Z44 CY62137VLL-70BAI BA48 Operating Range Package Type 44-Pin TSOP II Industrial 48-Ball Fine Pitch BGA 44-Pin TSOP II 48-Ball Fine Pitch BGA Shaded areas contain advance information. Document #: 38-00738-** Package Diagrams 48-Ball (7.00 mm x 7.00 mm) Mini-BGA BA48 51-85096-A 10 PRELIMINARY CY62137V MoBL Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.