128K x 16 Static RAM
CY62137V MoBL™
PRELIMINARY
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 29, 1999
Features
• Low vol t age range :
—1.8V–3.3V
• U ltra-l ow acti ve, st andby power
• Easy memory expansi on wit h CE and OE features
• TTL-compat ible inputs and outputs
• Automat ic power -down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62137V is a high-perfor mance CMO S static RAM or-
ganiz ed as 131,072 wor ds b y 16 bit s. Thi s devi ce feat ures ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
powe r cons umption b y 99% when addr esses are not toggli ng.
The device ca n also be put int o standby mode when deselec-
tect ed (C E HIGH) or when CE is LO W and both BLE and BHE
are HIGH. The input/output pins (I/O0 through I/O15) are
placed in a high impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LO W, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) i nputs LOW. If Byte Low Enable
(BLE) i s LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIG H. If Byte Low Enable (BLE) is LOW,
then data from the memory locati on specif ied by the address
pins will appear on I /O0 to I/O 7. If Byte High Enable (BHE) is
LO W, then data f rom memory will app ear on I/ O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62137V MoBL SRAM has an e xtremely wi de operating
vol tage range . This data sh eet has been speci fied to accur ate-
ly describe the de vice beha vior at thr ee common vo ltage rang -
es (3.3–2.7, 2.7– 2.3, 2.3–1.8)
The CY62137V is available in 48-ball FBGA and standard
44-pin TSOP Type I I (forward pi nout) packaging.
Logic Block Diagram Pin Configurations
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top Vie w
12
13
41
44
43
42
16
15 29
30
VCC
A16
A15
A14
A13 NC
A4
A3
OE
VSS
A5
I/O15
A2
CE
I/O2
I/O0
I/O1
BHE
NC
A1
A0
18
17
20
19
I/O3
27
28
25
26
22
21 23
24
VSS
I/O6
I/O4
I/O5
I/O7
A6
A7
BLE
VCC
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
62137V–2
TSOP II (Forward)
128K x 16
RAM Array I/O0 – I/O7
ROW DECODER
A9
A7
A6
A5
A0
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A8
I/O8 – I/O15
CE
WE
BLE
BHE
A10
62137V–1
A16
A12
Power Down
Circuit
A3
A2
A1
BHE
BLE
CE
MoBL and More Battery Lif e are t rademarks of Cypress Semiconductor Corp oration.
CY62137V MoBL
2
PRELIMINARY
Maximum Ratings
(Above which the useful l ife ma y be impaired. F or user guide-
li nes, not tested .)
Storage Temperature ... .. .......... .. ..... .. .........–65°C to +15 0 °C
Ambient Temperat ure with
Power Applied...............................................55°C to +12 5 °C
Supply Voltage to Ground Potential
(Pi n 2 8 to Pi n 14)... ... .............. ............... ........ –0.5V to +4.6V
DC Vol tage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1]................................ –0 .5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ...... .. .. ..... .. .................... .. ... >2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current...... .. .. ........ ..... .. ..... .. ..... .. ..... .. ...... >200 mA
Pin Configuration
48-Ball FBG A
WE
VCC
A11
A10
NC
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O
12
I/O
14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
62137V–3
3
26
5
41
D
E
B
A
C
F
G
H
Top View
A16
Operating Range
Range Ambient Temperature VCC
Industrial –40°C to +85°C 1.8V to 3.3V
Produc t Por tfolio
Product VCC Range
P ower Dissipation (Comm ercial)
Operating(Icc)Standb y (I SB2)
Min. Typ.[2] Max. Speed Typ.[2] Max. Typ.[2] Max
CY62137V 2.7V 3.0V 3.3V 70 ns 715mA 1 µA15 µA
CY62137V 2.3V 2.5V 2.7V 85 ns 510mA 12 µA
CY62137V 1.8V 2.0V 2.3V 100 ns 37mA 10 µA
Shaded area contains advance information.
CY62137V MoBL
3
PRELIMINARY
9
Electrical Characteristics O ver the Operating Range
CY62137V
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Output HI GH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 V
IOH = –0.1 mA VCC = 2.3V 2.0 V
IOH = –0.1 mA VCC = 1.8V 1.5 V
VOL Outpu t LOW Vol tage IOL = 2.1 mA VCC = 2.7V 0.4 V
IOL = 0.1 mA VCC = 2.3V 0.4 V
IOL = 0.1 mA VCC = 1.8V 0.2 V
VIH Input HIGH Vol ta ge VCC = 3.3V 2.2 VCC
+0.5V V
VCC = 2.7V 2.0 VCC
+0.5V V
VCC = 2.3V 1.4 VCC
+0.3V V
VIL Input LOW Voltage VCC = 2.7V –0.5 0.8 V
VCC = 2.3V –0.5 0.6 V
VCC = 1.8V –0.5 0.4 V
IIX Input Load Current GND < V I < VCC –1 +1 +1 µA
IOZ Outpu t Leakage Current GND < VO < VCC, Output
Disabled –1 +1 +1 µA
ICC VCC Operating Supply
Cur ren t IOUT = 0 mA,
f = fMAX = 1/tRC, CMOS
levels
VCC = 3.3V 715 mA
VCC = 2.7V 510 mA
VCC = 2.3V 3 7 mA
IOUT = 0 mA, f = 1 MHz, C MOS Le v els 1 2 mA
ISB1 Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC - 0.3V ,
VIN > VCC - 0.3V or
VIN < 0.3V, f = fMAX
100 uA
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC - 0.3V
VIN > VCC - 0.3V
or VIN < 0.3V, f = 0
L 1 50 uA
VCC =
3.3V LL 115 uA
VCC=
2.7V LL 112 uA
VCC =
2.3V LL 110 uA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C, f = 1 MHz,
VCC = 3.0V 6pF
COUT Outpu t Capacitance 8pF
Shaded areas contains advance information.
Note:
1. VIL(min) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C.
3. Tested initially and after any design or process changes that may affect these parameters.
CY62137V MoBL
4
PRELIMINARY
AC Test Loads and Waveforms
VCC Typ
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
C62137V–4C62137V–5
RTH
R1 VCC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE (b)
R1
R2
(a)
Parameters 3.0V 2.5V 2.0V UNIT
R1 1105 16670 15294 Ohms
R2 1550 15380 11300 Ohms
RTH 645 8000 6500 Ohms
VTH 1.75V 1.2V 0.85V Volts
Shaded areas contain advance information.
Data Reten ti o n Char acter i stic s (Over the Operating Range)
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC for Data Retention 1.0 3.3 V
ICCDR Data Retention Current VCC = 1.0V
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3v
L/
LL 0.1 1µA
tCDR[3] Chip Deselect to Data
Retention Time 0ns
tROperation Recovery Time tRC ns
Data Retention Waveform
Note:
4. Test conditions assume signal transition time of 5 ns or less, timing reference lev els of 1.5V, input levels of 0 to VCC typ., and output loading of the specified
IOL/IOH and 30 pF load capacitance.
C62137V–6
1.6V1.6V
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
CE
VCC
CY62137V MoBL
5
PRELIMINARY
Switching Characteristics Ov er the Operating Range[4]
(2.7V–3.3V
Operation) (2.3V–2. 7V
Operation) (1.8V–2.3V
Operation)
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycl e Time 70 85 100 ns
tAA Address to Data Valid 70 85 100 ns
tOHA Data Hold from Address Change 10 10 10 ns
tACE CE L OW to Da ta Va lid 70 85 100 ns
tDOE OE LOW to Data Valid 35 50 75 ns
tLZOE OE LOW to Low Z[5 5 5 5 ns
tHZOE OE HIGH to High Z[5 , 6] 25 35 50 ns
tLZCE CE LOW to Low Z[5] 10 10 10 ns
tHZCE CE HIGH to High Z[5, 6] 25 35 50 ns
tPU CE LOW to Po we r- U p 0 0 0 ns
tPD CE HIGH to Power-Down 70 85 100 ns
tDBE BHE / BLE LO W to Dat a Vali d 70 85 100 ns
tLZBE BHE / BL E LOW to Lo w Z 10 10 10 ns
tHZBE BHE / BLE HIGH to High Z 25 35 50 ns
WRITE CYCLE[7, 8]
tWC W ri t e Cycle Ti m e 70 85 100 ns
tSCE CE LOW to Write End 60 75 90 ns
tAW Address Set-Up to Write End 60 75 90 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE WE Pulse Widt h 50 65 80 ns
tSD Data Set-Up to Write End 30 50 60 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE WE LOW to High Z[5, 6] 25 35 50 ns
tLZWE WE HIGH to Low Z[5] 10 10 10 ns
tBW BHE / BL E LOW to End of Write 60 75 90 ns
Shaded areas contain advance information.
Notes:
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less th an t LZOE, and tHZWE is less t han t LZWE f or any given device.
6. tHZOE, tHZCE, and tHZWE are s pecifi ed with C L = 5 pF as in pa rt (b) of AC Test Loads . Transiti on is measu red ±500 mV fr om steady- state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LO W. Both si gnals mus t be L O W to ini t iate a write an d ei th er si gnal can terminate
a write b y goi ng HIGH . The data i nput set -up and hol d timing s hould b e ref ere nced to t he risi ng edg e of t he signal that termina tes the w rite .
8. The minimum write cycle time for write cycle #3 (W E control led, OE LO W) is the s um of tHZWE and t SD.
CY62137V MoBL
6
PRELIMINARY
Swi tchi n g Wavef o rms
Notes:
9. Device is continuously selected. OE, C E=VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LO W.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C62137V–7
Read Cycle No. 1
[9, 10]
50%
50%
DATA VALID
tRC
tACE
tDBE
tLZBE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
C62137V–8
Read Cycle No. 2 [10, 11]
tHZBE
BHE/BLE
tDOE
tLZOE
CY62137V MoBL
7
PRELIMINARY
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goes HIG H simu ltaneous ly wi th WE H IGH, t he outp ut r emains i n a hig h-impe dance state .
Swi tchi n g Wavef o rms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE C62137V–9
DATAIN VALID
NOTE
Write Cycl e No. 1 (WE Controlled) [7, 12, 13 ]
14
BHE/BLE tBW
tWC
tAW
tSA tHA
tHD
tSD
tSCE
WE
DATA I/O
ADDRESS
CE
C62137V–10
DATA
IN VALID
Write Cycl e No. 2 (CE Controlled) [7 , 1 2, 13]
BHE/BLE tBW
tPWE
CY62137V MoBL
8
PRELIMINARY
Note:
14. During this period, the I/Os are in output state and input signals should not be applied.
Swi tchi n g Wavef o rms (continued)
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
CE
WE
tHZWE C62137V–11
DATAIN VALID
Write Cycl e No. 3 (WE Controlled, OE LOW) [8 , 1 3]
NOTE 14
BHE/BLE tBW
CY62137V MoBL
9
PRELIMINARY
Typi cal DC an d AC Ch ar acte r i stics
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X Hi gh Z Deselect/Power-Down S tandby (ISB)
L X X H H High Z Deselect/Power-Down St a ndby ( I SB)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 i n High Z Read Activ e (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0 –I/O7 in High Z Read Activ e (ICC)
L H H L L Hi gh Z Deselect/Output Disabled Activ e (ICC)
L H H H L Hi gh Z Deselect/Output Disabled Activ e (ICC)
L H H L H High Z Deselect/Output Disabled Activ e (ICC)
L L X L L Data In (I/OO–I/O15)Write Activ e (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8 - I/O 15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z Write Active (ICC)
1.2
1.4
1.0
0.6
0.4
0.2
1.7 2.2 2.7 3.2 3.7
SUP PLY VOL TAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.0
0.8
1.0
0.5
0.25
1.7 2.2 2.7 3.2 3.7
NORMALIZED t
SUPPLYVOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
NORMALIZED I ,
CC
ICC
TA=25°C
0
AA
0.75
VIN =VCC typ.
TA=25°C
-55 25 105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
A MBIENT TEM PERATUR E (×C)
1.0
0.5
0.0
-0.5
ISB
3.0
STANDBY
VCC =VCC ty p.
VIN =VCC ty p.
ISB2 mA
1.50
1.00
0.50
115
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs. CYCLETIME
0.10
VCC =3.3V
TA=25°C
1.2
1.4
1.0
0.6
0.4
0.2
1.0 1.9 2.8 3.7
SUP PLY VOL TAGE (V)
NORMALIZED STANDBY CURRENT
vs. SUPPLY VOLTAGE
0.0
0.8
NORMALIZED ISB
ISB2
VIN =VCC typ.
TA=25°C
10
5
CY62137V MoBL
10
PRELIMINARY
Orde ring Information
Speed
(ns) Orde ring Code Package
Name Package Ty pe Operating
Range
70 CY62137VL-70ZI Z44 44-Pin TSOP II Industrial
CY62137VL-70BAI BA48 48-Ball Fine Pitch BG A
70 CY62137VLL-70ZI Z44 44-Pin TSOP II
CY62137VLL-70BAI BA48 48-Ball Fine Pitch BGA
Shaded areas contain advance information.
Document #: 38–00738–**
Package D i ag r ams
48-Ball (7.00 mm x 7.00 mm) Mini -BGA BA48
51-85096-A
CY62137V MoBL
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than ci rcuitry embodi ed in a Cypress Semiconduc tor produ ct. Nor does it convey or imply any license under patent or other rights. Cypr ess Semiconductor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag r ams (continued)
44-Pin TSOP II Z44
51-85087-A
