7955 Security Accelerator Data Sheet ......................................... DS-0114-01, (c) 2003, Hi/fn(R), Inc. All rights reserved. 12/03 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Hi/fn, Inc. ("Hifn") Licensing and Government Use Any Hifn software ("Licensed Programs") described in this document is furnished under a license and may be used and copied only in accordance with the terms of such license and with the inclusion of this copyright notice. Distribution of this document or any copies thereof and the ability to transfer title or ownership of this document's contents are subject to the terms of such license. Such Licensed Programs and their documentation have been developed at private expense and no part of such Licensed Programs is in the public domain. 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Specific testing of all parameters, with the exception of those mandated by government requirements, of each product is not necessarily performed. Certain applications using Hifn products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). Hifn products are not designed, intended, authorized, or warranted to be suitable for use in life saving, or life support applications, devices or systems or other critical applications. Inclusion of Hifn products in such critical applications is understood to be fully at the risk of the customer. Questions concerning potential risk applications should be directed to Hifn through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals," should be validated for each customer application by the customer's technical experts. Hifn does not warrant that its products are free from infringement of any patents, copyrights or other proprietary rights of third parties. In no event shall Hifn be liable for any special, incidental or consequential damages arising from infringement or alleged infringement of any patents, copyrights or other third party intellectual property rights. The use of this product in stateful compression protocols (for example, PPP or multi-history applications) with certain configurations may require a license from Motorola. In such cases, a license agreement for the right to use Motorola patents may be obtained through Hifn or directly from Motorola. Patents May include one or more of the following United States patents: 4,701,745; 5,003,307; 5,016,009; 5,126,739; 5,146,221; 5,414,425; 5,463,390; 5,506,580; and 5,5532,694. Other patents pending. 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Contents List of Figures...........................................................................................................................v List of Tables.......................................................................................................................... vii Preface...................................................................................................................................... ix About This Document............................................................................................................................. ix Audience .................................................................................................................................................. ix Prerequisite............................................................................................................................................. ix Document Conventions........................................................................................................................... ix Customer Support.................................................................................................................................... x Web Site ................................................................................................................................................... x 1 Product Description .......................................................................................................... 1 2 Features................................................................................................................................ 3 3 4 5 6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 High Performance ......................................................................................................................... 3 Major Security and Compression Protocol Support.................................................................... 3 Multiple Host Bus Interface Modes ............................................................................................. 3 Low Host Overhead....................................................................................................................... 4 Advanced Cryptographic Engines................................................................................................ 4 Software Support .......................................................................................................................... 4 Other Features .............................................................................................................................. 4 Performance Summary..................................................................................................... 5 3.1 3.2 3.3 Symmetric Key Processing Units................................................................................................. 5 Protocol Performance .................................................................................................................... 6 Public Key...................................................................................................................................... 6 Block Diagram .................................................................................................................... 9 4.1 Operation ....................................................................................................................................... 9 4.2 Security Processing ..................................................................................................................... 10 4.2.1 Muting Table ........................................................................................................................ 11 4.2.2 Public Key Processing.......................................................................................................... 11 Configuration Options ....................................................................................................13 5.1 Core Clock Configuration ........................................................................................................... 13 5.2 EEPROM and Hardware Configuration.................................................................................... 13 5.2.1 EEPROM Memory Map....................................................................................................... 15 5.2.2 Configuration without EEPROM........................................................................................ 16 5.3 Endianness Configuration ......................................................................................................... 16 5.3.1 Device Endianness Configuration....................................................................................... 17 5.3.2 Device Endianness Configuration Examples ..................................................................... 19 Signal Description ...........................................................................................................21 6.1 Signal Overview .......................................................................................................................... 21 ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 iii Contents ......................................... 6.1.1 PCI Signal Overview............................................................................................................ 21 6.1.2 PowerQuicc I Signal Overview............................................................................................ 22 6.2 Detailed Signal Description........................................................................................................ 23 7 8 9 Timing Specifications .....................................................................................................27 7.1 7.2 7.3 7.4 7.5 AC Operating Conditions............................................................................................................ 27 Host Bus Interface Clock ............................................................................................................ 27 PCI Timing .................................................................................................................................. 28 PowerQuicc_I Timing.................................................................................................................. 29 EEPROM ..................................................................................................................................... 31 DC Specifications.............................................................................................................33 8.1 8.2 8.3 8.4 Absolute Maximum Ratings ....................................................................................................... 33 Power Sequencing ....................................................................................................................... 33 Recommended Operating Conditions ........................................................................................ 34 DC Characteristics ...................................................................................................................... 34 Thermal Specifications...................................................................................................37 9.1 9.2 Heat Sink Requirements ............................................................................................................ 37 Junction Temperature Specifications ........................................................................................ 37 10 Pin List ...............................................................................................................................39 10.1 PCI-Mode Pin List ................................................................................................................... 39 10.2 PCI-Mode Pin List (by Category)............................................................................................ 40 10.3 PCI Mode Pinout ..................................................................................................................... 41 10.3.1 PQI-Mode Pin List ............................................................................................................ 42 10.3.2 PQI Mode Pin List (by Category) ..................................................................................... 43 10.4 PQI Mode Pinout ..................................................................................................................... 44 11 Physical Specifications...................................................................................................45 11.1 I LQFP 144-pin Plastic Quad Flatpack .................................................................................... 45 Errata..................................................................................................................................47 I.1 Document Revision 01 ................................................................................................................ 47 II Specification Clarifications...........................................................................................49 II.1 Document Revision 01 ................................................................................................................ 49 III Document Changes/Revisions.......................................................................................51 III.1 ...... iv Document Revision 01............................................................................................................. 51 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Example System Concept, MPC versus PCI Interface Mode............................................... 1 Block Diagram ........................................................................................................................ 9 Hardware Configuration Options ........................................................................................ 14 Endianness Transfer Modes................................................................................................. 18 PCI Host Bus Interface Signals ........................................................................................... 21 PowerQuicc_I Host Bus Interface Signals .......................................................................... 22 Input Bus Clock Timing ....................................................................................................... 27 Read/Write Timing (PQI bus) .............................................................................................. 30 EEPROM Timing .................................................................................................................. 31 PCI Mode Pinout Drawing ................................................................................................... 41 PQI Mode Pinout Drawing ................................................................................................... 44 144 LQFP Package ............................................................................................................... 45 ...... 7955 -Security Accelerator - Data Sheet, DS-0114-01 v .List . .of. Figures ..................................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... vi 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Ordering Information ................................................................................................................ 4 Processing Unit Performance ................................................................................................... 5 Protocol Processing Performance ............................................................................................. 6 IKE Performance ....................................................................................................................... 6 Public Key Performance (133 MHz Operation) ....................................................................... 6 Description of the functional units ......................................................................................... 10 EEPROM Memory Map .......................................................................................................... 15 Host Bus Mode Configuration without EEPROM................................................................. 16 Host Bus Endian Configuration without EEPROM.............................................................. 16 PCI Register Configuration without EEPROM .................................................................. 16 7955 Endianness Configuration .......................................................................................... 17 Endianness Mapping of System Data ................................................................................. 17 64-bit Host Data Endianness Control ................................................................................. 19 PCI Signals............................................................................................................................ 23 PowerQuicc_I Signals ........................................................................................................... 23 Hardware Configuration and EEPROM Signals ................................................................ 24 PLL Signals........................................................................................................................... 25 JTAG signals ......................................................................................................................... 25 Power and Ground signals ................................................................................................... 26 AC Operating Conditions ..................................................................................................... 27 PCI_CLK Timing .................................................................................................................. 27 PQI_CLK Timing .................................................................................................................. 28 PLL_REF Clock..................................................................................................................... 28 PCI 66MHz and 33MHz Timing Parameters...................................................................... 28 Read/Write Timing (PQI bus) .............................................................................................. 29 EEPROM Timing .................................................................................................................. 31 Absolute Maximum Ratings................................................................................................. 33 Recommended Operating Conditions .................................................................................. 34 DC Electrical Characteristics .............................................................................................. 34 Thermal Specifications ......................................................................................................... 37 Thermal Resistance .............................................................................................................. 37 PCI-Mode Pin List (Numeric) .............................................................................................. 39 PCI-Mode Pin List (Signal Category) .................................................................................. 40 PQI-Mode Pin List (Numeric) .............................................................................................. 42 PQI-Mode Pin List (Signal Category).................................................................................. 43 ...... 7955 -Security Accelerator - Data Sheet, DS-0114-01 vii .List . .of. Tables ..................................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... viii 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... Preface Welcome to the Data Sheet for the Hifn 7955 network security processors family. This document provides feature, performance, and interface information and specifications for the 7955. The reader is assumed to have a general knowledge of Hifn 795x architecture. The 7955 is the newest members of the 795x family of algorythm accelerators, which began with the Hifn 7951. For register descriptions, definitions of data structures, and general usage information, refer to the 7954/7955/7956 Hardware Users Guide (UG-0034). About This Document This document assumes you are already familiar with the chip technology and terminology. Audience This document is intended for integrators and application developers responsible for and familiar with software and hardware architecture of a target system. Prerequisite None Document Conventions The following conventions will be used throughout this document: ! Italic typeface indicates file names, book titles, new words or terms, words to be emphasized. ! SIGNAL names appear in Bold Small Caps. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 ix Preface ......................................... Customer Support For technical support about this product, please contact your local Hifn sales office, representative, or distributor. Web Site For general information about Hifn and Hifn products refer to: www.hifn.com. ...... x 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 1 Product Description High Performance- The Hifn TM 7955 Security Accelerator supports multi-protocol algorithm processing. Optimized for OC3/T3 Applications, 7955 Security Accelerator achieves over 250 Mbps full-duplex sustained performance with simultaneous encryption, compression, and authentication of large packets (1500 Bytes). Highly Integrated- All major security/compression protocols are supported. The 7955 is an ideal security solution for VPN enabled routers, remote access concentrators, VPN gateways, firewalls, and WAN switches. The 7955's integrated high-speed compression engines also makes it ideal for wireless applications. IPSec algorithms include AES-128, AES-192, AES-256, DES, 3DES, and ARC4 encryption. The 7955 supports SHA-1 and MD5 authentication, LZS and MPPC compression. AES Support- The 7955 fully supports the new Advanced Encryption Standard, AES, with key lengths of 128, 192 & 256-bits. It also supports AES counter-mode. Integrated Public-Key Processing- The 7955 contains an on-chip public-key subsystem. SSL, TLS, and IKE algorithms include RSA, DSA, and Diffie-Hellman operations. Host Bus Interface- The 7955 is equipped with a configurable PCI-2.2 compliant interface, enabling direct connection to any PCI host system. The 7955 also offers a glueless interface to the MPC860 bus. Compatibility- The 7955 is software-compatible with the Hifn 79xx family. WAN Ports WAN/LAN Ports System Memory LAN Ports 7955 7955 PCI Host Bus (32/64-bit @ 66 MHz ) MPC CPU (860) PowerQuicc I Bus (32-bit @ 40 MHz ) Figure 1 System Memory System Controller CPU Example System Concept, MPC versus PCI Interface Mode ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 1 1. .Product . . . . Description ................................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... 2 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 2 Features 2.1 High Performance ! Supports IPSec processing at OC3 and higher data rates (for 1500-byte packets) ! Processes entire packet (compression, encryption, and authentication) in a single pass ! Supports concurrent Public-Key and Symmetric Key processing ! Integrated Public Key processor # IPSec performance; 75 Diffie-Hellmann quick-mode connections/s (1024-bit) # SSL performance; 40 RSA signatures/s (1024-bit) ! Compression engine runs at over 250 Mbps and increases effective throughput ! Supports 128 Security Associations (SA) on-chip, and unlimited in host memory. 2.2 Major Security and Compression Protocol Support ! 128/192/256-bit AES (Advanced Encryption Standard), DES, 3DES, and ARC4 encryption (ARC4 is fully compatible with RSA's RC4TM algorithm) ! SHA-1 and MD5 hashing and authentication ! LZS and MPPC compression ! Public-key support includes RSA, DSA, SSL, IKE, and Diffie-Hellman ! Supports up to 3072-bit modular arithmetic and exponentiation ! True Hardware Random Number Generator 2.3 Multiple Host Bus Interface Modes ! Bus mastering PCI-2.2 Interface at 33 or 66 MHz ! Efficient scatter/gather DMA engines handle fragmented host memory ! Programmable bus arbitration/utilization for PCI bandwidth control ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 3 .2. .Features ...................................... ! 64-byte FIFO input and output buffers support high-speed burst transfers ! Optional external serial EEPROM enables customized PCI configurations ! Direct MPC860/850 PowerQuicc bus (32-bit GPCM) interface, up to 4 word burst 2.4 Low Host Overhead ! Security context (encryption keys and other stateful parameters) may be stored in on-chip memory to reduce host overhead ! Descriptor Based DMA engine (supports data scatter / gather) in PCI mode ! On-chip memory used to buffer control data packets 2.5 Advanced Cryptographic Engines ! Support for ECB, CBC, and CTR block-cipher modes of operation ! Multi-mode automatic padding ! Programmable mutable field MAC support for handling AH, IPv4, IPv6, and others 2.6 Software Support ! Supported by standard 79xx Hifn API ! API supports the full feature set of Hifn 79xx products ! API works with a wide variety of host architectures 2.7 Other Features ! Architecture compatibility with other Hifn 79xx Security Accelerators ! Supports low-cost implementation with 144-pin LQFP package ! JTAG support ! Reference hardware design ! 1.5V core with 3.3V I/O ! Typical dissipation <1W Table 1 Ordering Information Part Number 7955PT6 ...... 4 Speed 66 MHz Description 144-pin LQFP 7955 Network Security Accelerator 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 3 Performance Summary The figures in this section summarize the performance of the 7955 Security Accelerator functional units. Performance of the 7955 Security Accelerator when multiple engines are used (for example, the compression, MAC and encryption engines are all engaged) can be approximated by using throughput of the slowest engine. The MAC and encryption engine speeds are accelerated (effectively multiplied) by the actual compression ratio achieved by the compression engine. For example, if the achieved compression ratio is 2:1, then the MAC and encryption engine speeds are effectively doubled and the compression engine would be the slowest engine. This performance data reflects the following conditions: ! 66 MHz maximum internal core frequency ! 1500-byte packets. ! Single session or security association. ! Encoded text throughput 3.1 Table 2 Symmetric Key Processing Units Processing Unit Performance Protocol Performance @ 66 MHz (Mbps) AES-128, 192, 256 3DES ARC4 SHA-1 MD5 365, 420, 460 340 210 325 360 LZS Compression LZS Decompression MPPC Compression MPPC Decompression Note Stateless Stateful 510 455 505 420 450 395 460 425 All performance numbers are based on simulation results. Text from the United States Constitution was arbitrarily selected for the compression and decompression simulations. The compression ratio is approximately 2:1. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 5 .3. .Performance . . . . . . .Summary ............................... 3.2 Table 3 Protocol Performance Protocol Processing Performance Protocol IPSec (Tunnel; 3DES-CBC, SHA-1 HMAC) IPSec (Tunnel; AES-256, SHA-1 HMAC) IPSec (AH Tunnel; SHA-1 HMAC) 3-DES, SHA-1, Stateless LZS PPTP (RC4, MPPC) Note Performance @ 66 MHz Throughput Packets/Sec (Mbps) 325 27K 330 27K 320 370 360 27K 31K 30K All performance numbers are based on simulation results. Text from the United States Constitution was arbitrarily selected for the compression and decompression simulations. The compression ratio is approximately 2:1. 3.3 Table 4 Public Key IKE Performance IKE Handshake Two 1024-bit Diffie-Hellman operations (Quick Mode) Two 1024-bit Diffie-Hellman operations, 1 RSA sign, 2 RSA verifies (Main Mode) Four 1024-bit Diffie-Hellman operations, 1 RSA sign, 2 RSA verifies (Main Mode + Quick Mode) Note Connections/Sec @ 133 MHz 70 24 38 180-bit exponent. The number of connections/sec is based on simulation results. Table 5 Public Key Performance (133 MHz Operation) Operation @ 66 MHz RSA private key RSA public key (3-bit exponent) Diffie-Hellman (180-bit exponent) Diffie-Hellman (exponent = key size) DSA sign DSA verify ...... 6 Completion Time (ms) vs. Key Length (bits) 2048 1024 768 82.75 11.88 4.69 .45 .12 .07 27.13 7.25 4.81 308 41.25 20.50 12.94 19.41 7.78 11.66 512 1.75 .03 2.06 5.88 3.75 5.63 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Performance . . . . . . .Summary ..... Note Performance numbers assume a uniform distribution of ones and zeros in the exponent. Actual performance varies with the Hamming weight of the exponent. Performance numbers assume that the public key module has unrestricted access to memory. Actual performance varies with the memory usage of other system components. These numbers are only estimates and have not been experimentally verified. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 7 .3. .Performance . . . . . . .Summary ............................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... 8 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 4 4.1 Block Diagram Operation The 7955 Security Accelerator contains several processing units - Public Key encryption, symmetric key encryption, compression, padding, authentication, and Random Number Generator,. The symmetric key encryption, compression, padding, and authentication units are combined into a single functional block called the Packet Engine. The 7955 Security Accelerator also contains two programmable DMA engines with time-multiplex capability to transfer control and traffic data, source and destination FIFOs, PCI and PowerQuicc-I Host Interface. JTAG PK Engine PK Operand RAM (4KB) RNG EEPROM Optional EEPROM Interface Fetch FIFOs Algorithm Algorithm Engines Engines Context RAM (32KB) Encryption Data Path DMA (PCI) Memory Ctrl Interrupt and Control Registers Pipeline uControl Compression Authentication Post FIFOs Host Bus Interface (PCI or PQI) PLL PCI Rev 2.2 64/32-bits 66/33MHz Master MPC PowerQuicc I Slave PLL_REF Figure 2 ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 Block Diagram 9 .4. Block . . . Diagram .................................... Table 6 Description of the functional units Block Packet Engine Public-Key Processor Context RAM Inbound/Outbound DMA Units PCI Interface PowerQuicc_I 7955 Security Accelerator Registers EEPROM / Hardware Configuration Interface 4.2 Description The packet engine consist of the security, compression, padding, and MAC (not shown) processors. The packet engine contains pipelined compression, encryption, padding and authentication units, along with hardware for computing checksums, CRCs, and LCBs. The packet engine is configured by a command message prior to the start of each packet or task. The public-key processor incorporates enhanced features, providing hardware acceleration of public-key or symmetric key calculations on keys of up to 3,072 bits. The public-key processor also contains a hardware true-random number generator. It is accessible from both the PCI or MPC interfaces. The 32KB local memory is used for the storage of information such as descriptor, command, or per-session security context data. It may also contain I/O packet buffers. When the 7955 Security Accelerator is operating in PCI-bus mode, the inbound and outbound DMA units are special-purpose blocktransfer engines controlled by the 7955 Security Accelerator. The inbound DMA unit transfers commands and unprocessed packets from PCI to the 7955 Security Accelerator's security processing core, while the outbound DMA unit transfers processed packets and status information from security core to PCI. Fragmented buffers are supported through scatter/gather features in the DMA hardware. Internal FIFOs provide buffering to allow high-speed burst transfers. When the 7955 Security Accelerator is operating in slave-bus MPC mode, the PCI portion of the inbound/outbound DMA unit is disabled, and the PowerQuicc_I logic is enabled. The PCI interface is both an efficient bus master and an efficient bus target. It becomes a bus master for either the inbound DMA unit, or the outbound DMA unit. As a PCI slave, it services requests by the PCI host to access 7955 Security Accelerator registers and private memory. The PowerQuicc_I interface is an alternate I/O interface supporting direct host interface to MPC860/850.The MPC interface shares pins with the PCI interface, so both cannot be active in the same design. The 7955 Security Accelerator registers control the operation of the subsystem. They are memory-mapped to both the MPC and PCI. This interface supports an optional serial EEPROM used to configure the device registers at reset. If no EEPROM is used, the interface can be used to select default configuration, including host bus interface mode. Security Processing The 7955 DMA channels and associated controller are designed to off-load the host from having to move numerous copies of data and associated context for each iteration of security processing. Locally accessible descriptor, command and context further relieve the host from having to move ...... 10 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block . . . Diagram ..... multiple control data packets between the host and target to perform necessary security related processing. 4.2.1 Muting Table An on-board muting table memory provides the mask that controls the input to the MAC processor. The mask nulls specific segments of the data packet prior to being submitted to the MAC processor. The masks are programmable through the host bus & are selected by the MAC descriptor. 4.2.2 Public Key Processing 7955 uses an enhanced PK processor. To further optimize the PK acceleration, 7955 PK processor is equipped with a 16 Opcode FIFO and access to intermediate results is provided. PK processor operates on a batch of modular arithmetic instructions (up to 16) and issues an interrupt once the operand FIFO is empty. Since each modular arithmetic instruction (nano instruction) execution is host independent, the host is only expected to setup the PK engine and retrieve the result upon reception of PK interrupt. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 11 .4. Block . . . Diagram .................................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... 12 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 5 Configuration Options The 7955 Security Accelerator supports a five-pin configuration interface that is used during hardware reset to select the host bus mode and to set up critical register values. This configuration information may be contained in a serial EEPROM attached to the interface. Otherwise, a default configuration can be selected by the applying a value to the interface during hardware reset. 5.1 Core Clock Configuration When the 7955 comes out of reset the core logic is directly driven by the host bus interface clock, HBI_CLK (PCI_CLK or PQI_CLK depending on the bus mode selected). During register intialization, the on-chip PLL is enabled and programmed appropriately if a multiple of one of the input clocks (host bus interface or PLL_REF) is needed to maximize the 7955's performance. The clock configuration circuit provides maximum flexibility allowing the 7955 to be clocked synchronously or asynchronously to its host bus interface. Refer to the PLL Configuration Register section in the 7954/7955/7956 Hardware Users Guide (UG-0034) for details on configuring the clock circuit. Note The PLL_REF input signal may not be required in some systems to achieve maximum performance (see Table 17 for more information on use of this input signal). Care must be exercised in configuring the clock circuit to prevent the core logic from being over-clocked. 5.2 EEPROM and Hardware Configuration This section describes how the 5-pin serial EEPROM interface is used to configure the 7955 as it comes out of reset. The 7955 is designed so that the use of an external serial EEPROM is optional. When the 7955 comes out of reset (rising edge of the RST# signal), the EEPROM_EN signal is sampled to determine if an exteranl EEPROM is present or not. If EEPROM_EN is tied high, the 7955 will determine that an EEPROM is present and begin loading configuration register values from it. Aside from internal register logic, the remainder of the 7955, including the host interface, is held in a reset state for 20K clock cycles (the time it takes to load register values from EEPROM). If EEPROM_EN is tied low, the 7955 will determine that there is no external EEPROM present as the device comes out of reset. However, in non-EEPROM configurations, the remaining 4 EEPROM signals are designed to be individually tied high and low (see section 5.2.2) on the PCB to enable additional 7955 configuration options. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 13 .5. .Configuration . . . . . . . Options ............................... 7955 EEPROM_EN Security Accelerator EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO 7955 EEPROM_EN Security Accelerator EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO Figure 3 ...... 14 Hardware Configuration Option Flag EEPROM Local Configuration Memory Hardware Configuration Options 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . .Options .... 5.2.1 Table 7 EEPROM Memory Map EEPROM Memory Map EEPROM Address (H) Bit Field Name 0x00 1:0 HBI Select 0x00 3:2 reserved 0x00 4 HBI_SWAP8* 0x00 5 HBI_SWAP32* 0x00 15:6 reserved 0x01 15:0 PCI Vendor ID 0x02 15:0 PCI Device ID 0x03 15:0 PCI Class Code [23:8] 0x04 15:8 PCI Class Code [7:0] 0x04 7:0 RESERVED 0x05 15:8 PCI Revision ID 0x05 7:0 RESERVED 0x06 15:8 PCI BIST 0x06 7:0 RESERVED 0x07 15:8 PCI Header Type 0x07 7:0 RESERVED 0x08 15:0 PCI Subsystem ID 0x09 15:0 PCI Subsystem Vendor ID 0x0A 15:8 PCI Max_Lat 0x0A 7:0 PCI Min_Gnt 0x0B 15:8 PCI Interrupt Pin 0x0B 7:0 RESERVED 0x0C 15:0 RESERVED 0x0D 15:0 RESERVED 0x0E 15:0 RESERVED 0x0F 15:0 RESERVED 0x10 0 PQ_ADD_DEcODE_EN 0x10 1 RESERVED 0x10 15:2 RESERVED 0x11 15:0 PQ_Base_ADD 0x12 15:0 RESERVED 0x1F 0x20 15:0 RESERVED 0x2F 0x30 15:0 RESERVED 0x3F Notes: * Refer to Section 5.3 for endianness control. Host Bus Interface Select Endian Byte Swap Endian Double-Word Swap Address decode enable Base address Default Value (H) 0x0 0x0 0x0 0x0 0x0 0x13A3 0x0020 0x0B40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0 0x0 0x0000 0x0000 0x0000 0x0000 0x0000 ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 Description 15 .5. .Configuration . . . . . . . Options ............................... 5.2.2 Configuration without EEPROM If the EEPROM_EN input is tied low, the EEPROM interface signals are used as simple configuration inputs. EEPROM_CS and EEPROM_SK select the Host Bus mode, while EEPROM_DI and EEPROM_DO select the endian settings. Table 8 Host Bus Mode Configuration without EEPROM EEPROM_CS EEPROM_SK Host Bus Mode 0 0 1 1 0 1 0 1 PCI Bus Mode Reserved PowerQuicc-I Bus Mode Asynchronous SRAM Bus Mode Table 9 Host Bus Endian Configuration without EEPROM EEPROM_DI EEPROM_DO Host Bus Endian Mode 0 0 1 1 0 1 0 1 SWAP[32,8] = 00 SWAP[32,8] = 01 SWAP[32,8] = 10 SWAP[32,8] = 11 Table 10 PCI Register Configuration without EEPROM Field Vendor ID Device ID Class Code Class Code Revision ID BIST Subsystem ID Subsystem Vendor ID 5.3 Size in bits 16 16 16 8 8 8 16 16 Default Value 0x13A3 0x0020 0x0B40 0x00 0x01 0x00 0x0000 0x0000 Endianness Configuration The internal data endianness format of the 7955 is 64-bit Little-Endian. However, the 7955 is capable of functioning with four different host interface modes; 64-bit PCI-2.2 and 32-bit PowerQuicc-I. Endianness configuration is controlled for the following data paths: Target access to Registers (EEPROM Memory Map) ! Target access to Local-RAM (DMA Configuration Register #1) ! Target access to PKRAM (DMA Configuration Register #2) ...... 16 ! 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . .Options .... ! Initiator access to external descriptors (DMA Configuration Register #1) ! Initiator access to external data (Descriptor Structures) Initiator access to Local-RAM for internal descriptors and data is always in Little-Endian format. Target access to Local-RAM must be configured appropriately to preserve internal Little-Endian format. 5.3.1 Device Endianness Configuration Independent 2-bit fields will determine the endianness of each of these 5 data paths. The 2-bit field comprise of SWAP8 bit, which controls byte transposition of a 32-bit entity, and SWAP32 bit that controls swapping within a 64-bit entity. To the extent possible, these two bits are adjacent and the SWAP32 bit is the significant bit position. Table 11 7955 Endianness Configuration Endianness Configuration HBI_SWAP32 HBI_SWAP8 System Data Format 32-bit 0 0 Little-Endian 0 1 Big-Endian 1 0 1 1 64-bit RESERVED Little-Endian Big-Endian (Double-Word Swapped) Little-Endian (DoubleWord Swapped) Big-Endian Table 12 Endianness Mapping of System Data System Endianness Mode 32-bit LittleEndian 32-bit BigEndian 64-bit LittleEndian 64-bit LittleEndian (DW swapped) 64-bit BigEndian 64-bit BigEndian (DW swapped) System Data Format Byte[7] Byte[6] Byte[5] Byte[4] RESERVED Byte[3] Byte[2] Byte[1] Byte[0] Byte[3] Byte[2] Byte[1] Byte[0] Byte[0] Byte[1] Byte[2] Byte[3] Byte[7] Byte[6] Byte[5] Byte[4] Byte[3] Byte[2] Byte[1] Byte[0] Byte[3] Byte[2] Byte[1] Byte[0] Byte[7] Byte[6] Byte[5] Byte[4] Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] Byte[7] Byte[4] Byte[5] Byte[6] Byte[7] Byte[0] Byte[1] Byte[2] Byte[3] ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 17 .5. .Configuration . . . . . . . Options ............................... 32-bit Little-Endian 32-bit Big-Endian B3 B2 B1 B0 B0 B1 B2 B3 B3 B2 B1 B0 B3 B2 B1 B0 64-bit Little-Endian 64-bit Big-Endian B7 B6 B5 B4 B3 B2 B1 B0 B0 B1 B2 B3 B4 B5 B6 B7 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 64-bit Big-Endian (Double-Word Swapped) 64-bit Little-Endian (Double-Word Swapped) B3 B2 B1 B0 B7 B6 B5 B4 B4 B5 B6 B7 B0 B1 B2 B3 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 Figure 4 ...... 18 Endianness Transfer Modes 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . .Options .... 5.3.2 Device Endianness Configuration Examples Table 13 64-bit Host Data Endianness Control Endianness Configuration HBI_SWAP32 HBI_SWAP8 0 0 0 1 1 0 1 1 System Data Format 32-bit Mode Transferred Data 0 1 6 7 RESERVED 4 5 2 3 64-bit Mode Transferred Data 6 7 0 1 0 1 8 9 E F 6 7 2 3 A B C D 4 5 4 5 C D A B 2 3 6 7 E F 8 9 0 1 8 9 6 7 6 7 E F A B 4 5 4 5 C D C D 2 3 2 3 A B E F 0 1 0 1 8 9 ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 2 3 4 5 19 .5. .Configuration . . . . . . . Options ............................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... 20 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 6 Signal Description The 7955 Security Accelerator supports two different Host Bus Interface modes; PCI 2.2 and PowerQuicc I. All other signals are used for configuration and testing. 6.1 Signal Overview 6.1.1 PCI Signal Overview 7955 PCI_CLK PCI_RST# PCI 2.2 Host Bus Interface PCI_IDSEL 32 32 8 Security Accelerator (PCI mode) AVD AVS PLL_REF Core Clock PLL PCI_GNT# PCI_AD[31:0] PCI_AD[63:32] PCI_PAR PCI_PAR64 PCI_CBE#[7:0] PCI_FRAME# PCI_TRDY# EEPROM_CS EEPROM_SK EEPROM_DI EEPROM_DO EEPROM Config Interface EEPROM_EN PCI_IRDY# PCI_DEVSEL# TEST_EN Tied Low PCI_STOP# PCI_PERR# PCI_SERR# PCI_ACK64# PCI_REQ# PCI_REQ64# JTDI JTDO JTMS JTCK JTAG Test Interface JTRST# PCI_INTA# Figure 5 PCI Host Bus Interface Signals ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 21 .6. .Signal . . . Description ................................... 6.1.2 PowerQuicc I Signal Overview 7955 P Q I_C LK 32 32 P Q I_R S T # P Q I_C S # A VD A VS P LL_R EF P Q I_A [0:31] P Q I_B U R ST # P Q I_D [0:31] P Q I_R D /W R # P Q I_T A# 2 Security Accelerato r (Po w erQ uicc_I m o d e) P Q I_T EA # P Q I_T S# P Q I_T SIZ [0:1] P Q I_IN T # EE PR O M _C S EEP R O M _S K EEP R O M _D I E EPR O M _D O EE PR O M _EN T ES T_EN JTD I JT D O JT M S JT C K JT R ST # Figure 6 ...... 22 PowerQuicc_I Host Bus Interface Signals 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal . . . .Description ...... 6.2 Detailed Signal Description The 7955 provides a PCI 2.2 compliant interface mode. The following PCI signals are supported. Table 14 PCI Signals PCI Signals PCI_CLK PCI_RST# PCI_IDSEL PCI_REQ# PCI_GNT# PCI_AD[63:0] PCI_PAR I/O (Buffer type) Input (I-PCI) Input (I-PCI) Input (I-PCI) Output (TS-PCI) Input (I-PCI) I/O (I/O-PCI) I/O (I/O-PCI) PCI_PAR64 I/O (I/O-PCI) PCI_CBE#[7:0] PCI_FRAME# PCI_TRDY# PCI_IRDY# PCI_DEVSEL# PCI_STOP# PCI_PERR# PCI_SERR# PCI_ACK64# I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) I/O (I/O-PCI) Output (TS-PCI) I/O (I/O-PCI) PCI_REQ64# I/O (I/O-PCI) PCI_INTA# Output (TS-PCI) Description PCI clock PCI reset. Master reset for 7954. PCI initialization device select. PCI bus request. PCI bus grant. PCI address/data bus. PCI Parity signal; even parity across PCI_AD[31:0] and PCI_CBE#[3:0] PCI Parity Upper DWORD signal for PCI_AD[63:32] and PCI_CBE#[7:4]. The PCI_PAR64 port is used only when the interface is configured with a 64-bit AD bus. PCI bus command/byte-enable bits. PCI cycle frame. PCI target ready. PCI initiator ready. PCI device select. PCI stop. PCI parity error. PCI system error. PCI Acknowledge 64-Bit Transfer signal. The PCI_ACK64# is used only when the interface is configured with a 64-bit AD bus. PCI Request 64-Bit Transfer signal. The PCI_REQ64# is used only when the interface is configured with a 64-bit AD bus. PCI interrupt request. Notes: Buffer Type: I-PCI=PCI input, I/O-PCI=PCI Bidirectional, TS-PCI=PCI Tri-State output Table 15 PowerQuicc_I Signals PowerQuicc_I Signal PQI_CLK PQI_RST# PQI_CS# I/O (Buffer type) Input (I-PQ) Input (I-PQ) Input (I-PQ) PQI_A[0:31] Input (I/O-PQ) PQI_BURST# PQI_D[0:31] PQI_RD/WR# PQI_TA# Input (I/O-PQ) I/O (I/O-PQ) Input (I/O-PQ) Tri-state Output (I/O-PQ) Tri-state Output (TS-PQ) PQI_TEA# PowerQuicc_I transfer acknowledge PowerQuicc_I transfer error acknowledge ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 Description Clock input, for the PowerQuicc_I interface bus clock Chip reset. Master reset for 7954. External space chip-select. Active-low chip-select for memory space. PowerQuicc_I address bus. Only 32-bit word aligned addresses are supported and PQI_TEA# will be asserted if PQI_A[31:30] are not held low during the transfer. PowerQuicc_I transfer burst PowerQuicc_I data bus PowerQuicc_I read/write enable 23 .6. .Signal . . . Description ................................... PQI_TS# PQI_TSIZ[0:1] Input (I-PQ) Input (I/O-PQ) PowerQuicc_I transfer start PowerQuicc_I transfer size PQI_TSIZ[0:1] 00 00 PQI_INT# Notes: Buffer Type: output Open-Drain Output (TS-PQ) PQI_BURST# 1 0 Burst Size 4 bytes 16 bytes PowerQuicc_I interrupt request I-PQ=PQ input, I/O-PQ=PQ Bi-directional, TS-PQ=PQ Tri-State Table 16 Hardware Configuration and EEPROM Signals EEPROM Signal TEST_EN EEPROM_EN I/O (Buffer type) Input (I) Input (I) EEPROM_CS I/O (I/O-O4) EEPROM_DI I/O (I) EEPROM_DO I/O (I/O-O4) EEPROM_SK I/O (I/O-O4) Description Test mode enable. It is normally tied low at all times Hardware configuration selectors to indicate PCI BARs, memory size, etc. EEPROM configuration is selected when this inputs is forced low. EEPROM chip select / HW Configuration Address bit[0] EEPROM serial data in / HW Configuration Address bit[1] EEPROM serial data out / HW Configuration Address bit[2] EEPROM clock / HW Configuration Address bit[3] Notes: Buffer Type: I=Input, I/O-O4=I/O with 4mA output driver ...... 24 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal . . . .Description ...... Table 17 PLL Signals PLL Signal PLL_REF I/O Description Input (CI) PLL reference clock input or system clock (7955 Security Accelerator). This signal is completely asynchronous to the host bus interface, HBI_CLK, (PQI_CLK and PCI_CLK). On 7955 Security Accelerator, this signal is the input to a clockmultiplier PLL, which provides the clock for the packet engine and PK processor subsystems. Note The 7955 requires a clock source to drive the PLL_REF input pin in all configurations. This clock input pin must not be grounded when register to a 0b0 to select the HBI_CLK as the PLL source will fail unless PLL the HBI_CLK (PQI_CLK or PCI_CLK) is used to drive the internal PLL. Programming bit 0 (PLL_REF_SEL) of the PLL Configuration _REF is driven by a clock source. Once the PLL Configuration register has been programmed, the PLL_REF input requires four rising edges to complete the PLL clock source reconfiguration. Once the four clocks have been completed, the PLL lock time, as specified in the Timing Specifications shown in Table 22 for PLL_REF, will begin. When using PLL_REF as the clock source to the PLL, all timing requirements as stated in Table 22 must be met. When using PLL_REF to reconfigure the PLL source to the HBI_CLK, the clock frequency still must not exceed the values specified in Table 22 but the minimum frequency doesn't apply. Any source that will provide the required four clocks can be used. One solution for customers that use an EEPROM (EEPROM_EN=0b1) to configure the device is to connect the EEPROM_SK signal to the PLL_REF input pin as well as to the EEPROM. In this case, the PLL clock source is guaranteed to be configured to the HBI_CLK within 2050 PCI clock periods after writing to the PLL Configuration register. Note: Buffer Type: CI=clock input Table 18 JTAG signals Test Signal JTDI JTDO JTMS JTCK JTRST# I/O (Buffer type) Input (PI) Output (TS-O4) Input (PI) Input (PI) Input (PI) Description JTAG test data in JTAG test data out JTAG test mode select JTAG test clock JTAG test mode reset. This should not be tied to the system reset signal. It is normally tied low at all times except JTAG testing. Note: Buffer Type: PI-Input with pull-up resistor, TS-O4=Tri-State with 4mA output driver ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 25 .6. .Signal . . . Description ................................... Table 19 Power and Ground signals I/O Description VSS Ground VSS2 Ground VDDC VDDS Power Power VDDS2 Power VDDS12 Power AVS AVD RESERVED_VSS RESERVED_NC Ground Power Input Output Digital ground for output buffers Digital ground for input buffers, internal arrays & pre-buffers Power for 1.5 V internal logic Power for 3.3 V output buffers Power for 3.3 V input buffers & preTie these buffers together Power for 3.3 V input & output buffers & pre-buffers PLL Analog ground PLL 1.5 V Analog supply Must be tied to VSS (series resistor is optional) Must not be connected ...... 26 Misc. Signal 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 7 Timing Specifications 7.1 AC Operating Conditions Table 20 AC Operating Conditions Symbol Parameter Conditions* VDDC Supply voltage - Core 1.5V 5% VDDS Supply voltage - I/O 3.3V 10% VSS Ground potential 0V TA Ambient operating temperature Note: (*) See derating information below for other load conditions. 7.2 0C to +70C Host Bus Interface Clock 4 5 2 3 1 Figure 7 Table 21 Input Bus Clock Timing PCI_CLK Timing Number Description 1 Clock frequency Clock period Clock width high Clock width low Clock rise time from VIL to VIH Clock fall time from VIH to VIL 2 3 4 5 Max 66.67 15 2 2 Units MHz ns ns ns ns ns ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 Min DC Infinite 6 6 27 .7. .Timing . . . .Specifications .................................. Table 22 PQI_CLK Timing Number Description 1 Clock frequency Clock period Clock width high Clock width low Clock rise time from VIL to VIH Clock fall time from VIH to VIL 2 3 4 5 Min DC Infinite 6 6 Max 40 25 Units MHz ns ns ns ns ns 2 2 Table 23 PLL_REF Clock Number Description Min Max Units 1 Clock frequency Clock Period Clock width high Clock width low Clock rise time from VIL to VIH Clock fall time from VIH to VIL Duty cycle Jitter (peak to peak) PLL lock time 20 50 4.5 4.5 100 10 MHz ns ns ns ns ns % ps usec 2 3 4 2 5 2 n/a 45 55 n/a 100 n/a 100*n Note: n = (PLL_ND+1)*2 (see the PLL Configuration Register description in the 7954/7955/7956 Hardware Users Guide (UG-0034) for more information on the PLL_ND setting). 7.3 PCI Timing Table 24 PCI 66MHz and 33MHz Timing Parameters Symbol Parameter Tval PCI_CLK to Signal Valid Delay - bused signals PCI_CLK to Signal Valid Delay - point to point signals Float to Active Delay Active to Float Delay Initial setup time to PCI_CLK - bused signals Initial setup time to PCI_CLK - point to point signals Input Hold time from PCI_CLK Reset Active Time after power stable Reset Active Time after PCI_CLK stable Tval (ptp) Ton Toff Tsu Tsu (ptp) Th Trst Trst-clk ...... 28 66MHz Min 2 2 Max 6 6 2 33MHz Min 2 2 Max 11 Units ns 12 ns 28 2 3 7 ns ns ns 5 10,12 ns 0 0 ns 1 1 ms 100 100 ms 14 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Timing . . . .Specifications ....... Trst-off Reset Active to output float delay PCI_REQ64# to PCI_RST# setup time PCI_RST# to PCI_REQ# hold time PCI_RST# high to first Configuration access PCI_RST# high to first PCI_FRAME# assertion Trrsu trrh Trhfa Trhff 40 10Tcyc 0 40 ns 10Tcyc 50 ns 0 ns 50 2 2 clocks 5 5 clock Notes: These specifications are taken from the PCI 2.2 Standard, section 7.6.4.2. PCI_REQ# and PCI_GNT# are point to point signals and have different input setup times than do bused signals. 7.4 PowerQuicc_I Timing Table 25 Read/Write Timing (PQI bus) Number 1 2 3 4 5 6 7 8 9 Description PQI_A[0:31], PQI_TS#, PQI_CS#, PQI_TSIZ[0:1], PQI_RD/WR# setup PQI_A[0:31], PQI_TS#, PQI_CS#, PQI_TSIZ[0:1], PQI_RD/WR# hold Write data setup Write data hold PQI_TA# high-z to low (assertion delay) PQI_TA# low to high (deassertion delay) PQI_TA# high to high-z Read data output valid delay (high-z to 0/1) Read data output invalid delay (0/1 to high-z) Min Max Units 3 ns 0 ns 3 0 2 2 2 2 2 ns ns ns ns ns ns ns 7 7 7 7 7 Notes All signals are synchronous to PQI_CLK. Max values are for a 50 pF load and Min values are for a 2 pF load. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 29 .7. .Timing . . . .Specifications .................................. PQI_CLK PQI_TS# 1 2 PQI_A[0:31] 1 2 PQI_CS# 1 2 PQI_TSIZ[0:1] 1 2 PQI_TA# 5 7 6 Write Operation PQI_RD/WR# 1 2 PQI_D[0:31] 3 4 Read Operation PQI_RD/WR# PQI_D[0:31] 2 1 8 Figure 8 ...... 30 9 Read/Write Timing (PQI bus) 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Timing . . . .Specifications ....... 7.5 EEPROM The EEPROM interface signal timing is derived from the PCI_CLK divided by 256. Table 26 EEPROM Timing Number Symbol 1 2 3 4 5 6 7 8 9 10 11 12 Fsk Tskh Tskl Tsks Tcs Tcss Tdh Tdis Tcsh Tdih Tpd0 Tpd1 Min Max Units 256 tPCI_CLK ns ns ns ns ns ns ns ns ns ns ns ns 128 tPCI_CLK - 5 128 tPCI_CLK - 5 128 tPCI_CLK - 5 256 tPCI_CLK - 5 128 tPCI_CLK - 10 0 128 tPCI_CLK - 10 0 127 tPCI_CLK - 10 127 tPCI_CLK - 10 127 tPCI_CLK - 10 Synchronous Data Timing EEPROM_CS VIH 5 1 VIL 4 EEPROM_SK 6 2 9 3 VIH VIL EEPROM_DO VIH 8 10 VIL 11 EEPROM_DI VOH VOL 12 7 7 Figure 9 ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 EEPROM Timing 31 .7. .Timing . . . .Specifications .................................. THIS PAGE INTENTIONALLY LEFT BLANK. ...... 32 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 8 DC Specifications 8.1 Absolute Maximum Ratings Table 27 Absolute Maximum Ratings DC Supply Voltage (VDDS, VDDS2, VDDS12) DC Supply Voltage (VDDC, AVD) DC Input Voltage (Signals) Storage Temperature Delay between asserting +1.5V (VDDC & AVD) and +3.3V (VDDS, VDDS2, VDDS12) power supplies -0.3V to +5.0V -0.3V to +3.3V -0.3V to VDDS+0.3 -40C to +125C 0-500ms Warning Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 8.2 Power Sequencing The +1.5V and +3.3V power supply voltages must be asserted at the same time. Otherwise, the device may be damaged by reverse currents. To prevent damage to the device, these voltages must be enabled within the time given in the absolute maximum ratings. The power supply should be designed to assert power within the time limits given under the recommended operating conditions. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 33 .8. .DC. .Specifications .................................... 8.3 Recommended Operating Conditions Table 28 Recommended Operating Conditions DC Supply Voltage (VDDS, VDDS2, VDDS12) DC Supply Voltage (VDDC, AVD) Delay between asserting +1.5V (VDDC & AVD) and +3.3V (VDDS, VDDS2, VDDS12) power supplies Operating Temperature 8.4 +3.0V to +3.6V +1.425V to +1.575V 0 - 100ms 0C to +70C DC Characteristics Table 29 DC Electrical Characteristics Symbol Parameter VIL Low level input voltage (I, PI, I/O-O4) Conditions I-PCI, I/O-PCI, I-PQ, I/O-PQ Min Typ -0.5 IIL 2.0 I-PCI, I/O-PCI, I-PQ, I/O-PQ 1.425 Clock Input (CI) 2.4 VIN = VSS VDDS = 3.6V With pull-up (PI) I-PCI, I/O-PCI, I-PQ, I/O-PQ IIH High level input current (I, I/O-O4) VOL Low level output voltage VIN = VDDS VDDS = 3.6V I-PCI, I/O-PCI, I-PQ, I/O-PQ (O4) V 4.1 -10 10 10 200 -10 10 -10 10 -10 10 VDDS = 3.0V High level output voltage (O4) High impedance output leakage current IDD Quiescent supply current CIN Input capacitance (I, PI) 0.36 VDDS = 3.0V IOH = -4mA V 2.4 2.7 VO = VSS or VDDS VDDS = 3.6V -10 A 300 VDDS = 3.3V 2.4 I-PCI, I/O-PCI, I-PQ, I/O-PQ A pF 10 PCI_IDSEL 8 PCI_CLK, PQI_CLK 5 12 COUT Output capacitance (TS-O4) VDDS = 3.3V 5.6 pF CI/O I/O capacitance (I/O-O4) VDDS = 3.3V 6.6 pF ...... 34 A 0.4 I/O-PCI, TS-PCI, I/O-PQ, TS-PQ IOZ A V IOL = 4mA I/O-PCI, TS-PCI, I/O-PQ, TS-PQ VOH V 0.72 High level input voltage (I, PI, I/O-O4) Low level input current (I, I/O-O4) Units 0.8 1.17 Clock Input (CI) VIH Max 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC. .Specifications ....... Symbol Parameter Conditions IDD core Active Supply Current (VDDC) IDD I/O Active Supply Current (VDDS) IAVD PLL analog power supply current AVD = 1.575V Min Typ Max Units VDDC=1.575V 166 178 mA VDDS = 3.6V 115 165 mA 6 mA Notes: Host Bus pins are shared between 32-bit PowerQuicc I and the 64-bit PCI. Buffer Type: I=input, I/O-O4=Bi-directional with 4mA output driver, CI=Clock input, PI-Input with pull-up resistor, TS-O4=Tri-State with 4mA output driver, I-PCI=PCI input, I/O-PCI=PCI Input/Output, TS-PCI=PCI Tri-State output, I-PQ=PQ input, I/O-PQ=PQ Input/Output, TSPQ=PQ Tri-State output ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 35 .8. .DC. .Specifications .................................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... 36 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 9 Thermal Specifications Table 30 Thermal Specifications Parameter Min Typ Max Units Junction Temperature (Tj) 0 100* 125* C Ambient Operating Temperature (Ta) 0 70 C Storage Temperature -40 125 C Power Dissipation (P) @ VDDS = 3.6V 0.638 0.885 W * For proper operation, the maximum junction temperature must not exceed 125 C. However, the life of the part may be shortened if the average operating junction temperature is allowed to exceed 100 C. Table 31 Thermal Resistance Parameter Thermal Resistance, Junction to Ambient (ja) Thermal Resistance, Junction to Ambient (jma at 1 m/s) Internal Thermal Resistance (jc) Temperature Correlation, Center Top of Pkg to Junction (jt) Max 44.4 38.5 12 TBD Units C/W C/W C/W C/W 9.1 Heat Sink Requirements Refer to the 7954/7955/7956 Thermal Characteristics Application Note for additional information to help determine the heat sink requirements. 9.2 Junction Temperature Specifications The maximum operating junction temperature is 125 C. Above this temperature, operating the part is not guaranteed. For maximum operating life the junction temperature in the device should be no more than 100 C. Worst case device dissipation should be used when performing thermal calculations. Refer to Thermal Management Application Note, AN-0038 for additional information to help determine application specific junction temperatures and heat sink requirements. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 37 .9. .Thermal . . . . Specifications .................................. THIS PAGE INTENTIONALLY LEFT BLANK. ...... 38 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 10 Pin List 10.1 PCI-Mode Pin List Table 32 PCI-Mode Pin List (Numeric) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PCI_INTA# PCI_RST# VDDS PCI_CLK PCI_GNT# VDDC PCI_REQ# PCI_AD31 PCI_AD30 PCI_AD29 VSS PCI_AD28 PCI_AD27 PCI_AD26 VDDS PCI_AD25 PCI_AD24 VDDS2 PCI_CBE#3 PCI_IDSEL PCI_AD23 VSS2 VDDC PCI_AD22 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name PCI_AD21 PCI_AD20 PCI_AD19 VDDS PCI_AD18 PCI_AD17 PCI_AD16 VSS PCI_CBE#2 PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# VDDS PCI_PERR# VSS VSS2 VDDS2 PCI_SERR# PCI_PAR VDDC PCI_CBE#1 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 VSS PCI_AD11 VDDS PCI_AD10 PCI_AD9 PCI_AD8 PCI_CBE#0 PCI_AD7 PCI_AD6 Name VSS2 PCI_AD5 PCI_AD4 VSS PCI_AD3 VDDS VDDS2 PCI_AD2 PCI_AD1 PCI_AD0 PCI_ACK64# PCI_REQ64# PCI_CBE#7 PCI_CBE#6 PCI_CBE#5 VSS PCI_CBE#4 VDDS12 PCI_PAR64 VDDC PCI_AD63 VSS2 PCI_AD62 PCI_AD61 PCI_AD60 PCI_AD59 PCI_AD58 PCI_AD57 VDDS2 VSS PCI_AD56 VDDS PCI_AD55 PCI_AD54 PCI_AD53 PCI_AD52 Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 VSS2 VDDS PCI_AD47 VSS PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 VDDC PCI_AD40 VDDS2 VDDS PCI_AD39 VSS PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 VSS2 RESERVED_nc VDDS AVS AVD VSS JTMS JTDI PLL_REF ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 39 .10 . . .Pin. .List ................................... 10.2 PCI-Mode Pin List (by Category) Table 33 PCI-Mode Pin List (Signal Category) Pin 140 139 8 10 7 5 9 3 143 2 142 4 83 82 81 80 77 75 74 72 71 69 68 67 65 63 62 61 60 43 42 41 39 38 37 36 ...... 40 Name AVD AVS EEPROM_CS EEPROM_DI EEPROM_DO EEPROM_EN EEPROM_SK JTCK JTDI JTDO JTMS JTRST# PCI_ACK64# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 Pin 33 29 28 26 25 24 22 21 20 135 134 133 132 131 130 129 127 124 122 121 120 119 118 117 115 112 111 110 109 108 107 106 105 103 100 99 Name PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_AD32 PCI_AD33 PCI_AD34 PCI_AD35 PCI_AD36 PCI_AD37 PCI_AD38 PCI_AD39 PCI_AD40 PCI_AD41 PCI_AD42 PCI_AD43 PCI_AD44 PCI_AD45 PCI_AD46 PCI_AD47 PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 PCI_AD56 PCI_AD57 PCI_AD58 Pin 98 97 96 95 93 70 59 45 31 89 87 86 85 16 49 46 17 32 13 47 57 91 52 19 84 14 56 50 48 144 137 1 12 18 35 58 Name PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_CBE#4 PCI_CBE#5 PCI_CBE#6 PCI_CBE#7 PCI_CLK PCI_DEVSEL# PCI_FRAME# PCI_GNT# PCI_IDSEL PCI_INTA# PCI_IRDY# PCI_PAR PCI_PAR64 PCI_PERR# PCI_REQ# PCI_REQ64# PCI_RST# PCI_SERR# PCI_STOP# PCI_TRDY# PLL_REF RESERVED_NC TEST_EN VDDC VDDC VDDC VDDC Pin 92 123 15 27 40 51 66 78 104 114 126 138 90 6 30 55 79 101 125 23 44 53 64 76 88 102 116 128 141 11 34 54 73 94 113 136 Name VDDC VDDC VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS12 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Pin . .List .. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 VDDS PCI_AD56 VSS VDDS2 PCI_AD57 PCI_AD58 PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 VSS2 PCI_AD63 VDDC PCI_PAR64 VDDS12 PCI_CBE#4 VSS PCI_CBE#5 PCI_CBE#6 PCI_CBE#7 PCI_REQ64# PCI_ACK64# PCI_AD0 PCI_AD1 PCI_AD2 VDDS2 VDDS PCI_AD3 VSS PCI_AD4 PCI_AD5 VSS2 10.3 PCI Mode Pinout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PCI_AD6 PCI_AD7 PCI_CBE#0 PCI_AD8 PCI_AD9 PCI_AD10 VDDS PCI_AD11 VSS PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_CBE#1 VDDC PCI_PAR PCI_SERR# VDDS2 VSS2 VSS PCI_PERR# VDDS PCI_STOP# PCI_DEVSEL# PCI_TRDY# PCI_IRDY# PCI_FRAME# PCI_CBE#2 VSS PCI_AD16 PCI_AD17 PCI_AD18 VDDS PCI_AD19 PCI_AD20 PCI_AD21 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PCI_INTA# PCI_RST# VDDS PCI_CLK PCI_GNT# VDDC PCI_REQ# PCI_AD31 PCI_AD30 PCI_AD29 VSS PCI_AD28 PCI_AD27 PCI_AD26 VDDS PCI_AD25 PCI_AD24 VDDS2 PCI_CBE#3 PCI_IDSEL PCI_AD23 VSS2 VDDC PCI_AD22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PCI_AD51 PCI_AD50 PCI_AD49 PCI_AD48 VSS2 VDDS PCI_AD47 VSS PCI_AD46 PCI_AD45 PCI_AD44 PCI_AD43 PCI_AD42 PCI_AD41 VDDC PCI_AD40 VDDS2 VDDS PCI_AD39 VSS PCI_AD38 PCI_AD37 PCI_AD36 PCI_AD35 PCI_AD34 PCI_AD33 PCI_AD32 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF Figure 10 PCI Mode Pinout Drawing ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 41 .10 . . .Pin. .List ................................... 10.3.1 PQI-Mode Pin List Table 34 PQI-Mode Pin List (Numeric) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ...... 42 Name TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PQI_INT# PQI_RST# VDDS PQI_CLK PQI_TS# VDDC RESERVED_NC PQI_A0 PQI_A1 PQI_A2 VSS PQI_A3 PQI_A4 PQI_A5 VDDS PQI_A6 PQI_A7 VDDS2 PQI_TSIZ1 PQI_CS# PQI_A8 VSS2 VDDC PQI_A9 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name PQI_A10 PQI_A11 PQI_A12 VDDS PQI_A13 PQI_A14 PQI_A15 VSS PQI_TSIZ0 RESERVED_VDD PQI_BURST# RESERVED_VSS RESERVED_VSS RESERVED_VSS VDDS PQI_TA# VSS VSS2 VDDS2 PQI_TEA# RESERVED_VSS VDDC RESERVED_VSS PQI_A16 PQI_A17 PQI_A18 PQI_A19 VSS PQI_A20 VDDS PQI_A21 PQI_A22 PQI_A23 RESERVED_VSS PQI_A24 PQI_A25 Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name VSS2 PQI_A26 PQI_A27 VSS PQI_A28 VDDS VDDS2 PQI_A29 PQI_A30 PQI_A31 RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS VSS PQI_RW# VDDS12 RESERVED_VSS VDDC PQI_D0 VSS2 PQI_D1 PQI_D2 PQI_D3 PQI_D4 PQI_D5 PQI_D6 VDDS2 VSS PQI_D7 VDDS PQI_D8 PQI_D9 PQI_D10 PQI_D11 Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name PQI_D12 PQI_D13 PQI_D14 PQI_D15 VSS2 VDDS PQI_D16 VSS PQI_D17 PQI_D18 PQI_D19 PQI_D20 PQI_D21 PQI_D22 VDDC PQI_D23 VDDS2 VDDS PQI_D24 VSS PQI_D25 PQI_D26 PQI_D27 PQI_D28 PQI_D29 PQI_D30 PQI_D31 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF 7955- Security Accelerator - Data Sheet, DS-0114-01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Pin . .List .. 10.3.2 PQI Mode Pin List (by Category) Table 35 PQI-Mode Pin List (Signal Category) Pin Name Pin Name Pin Name Pin Name 140 139 8 10 7 5 9 3 143 2 142 4 144 20 21 22 24 25 26 28 29 33 36 37 38 39 41 42 43 60 61 62 63 65 67 68 AVD AVS EEPROM_CS EEPROM_DI EEPROM_DO EEPROM_EN EEPROM_SK JTCK JTDI JTDO JTMS JTRST# PLL_REF PQI_A0 PQI_A1 PQI_A2 PQI_A3 PQI_A4 PQI_A5 PQI_A6 PQI_A7 PQI_A8 PQI_A9 PQI_A10 PQI_A11 PQI_A12 PQI_A13 PQI_A14 PQI_A15 PQI_A16 PQI_A17 PQI_A18 PQI_A19 PQI_A20 PQI_A21 PQI_A22 69 71 72 74 75 77 80 81 82 47 16 32 93 95 96 97 98 99 100 103 105 106 107 108 109 110 111 112 115 117 118 119 120 121 122 124 PQI_A23 PQI_A24 PQI_A25 PQI_A26 PQI_A27 PQI_A28 PQI_A29 PQI_A30 PQI_A31 PQI_burst# PQI_CLK PQI_CS# PQI_D0 PQI_D1 PQI_D2 PQI_D3 PQI_D4 PQI_D5 PQI_D6 PQI_D7 PQI_D8 PQI_D9 PQI_D10 PQI_D11 PQI_D12 PQI_D13 PQI_D14 PQI_D15 PQI_D16 PQI_D17 PQI_D18 PQI_D19 PQI_D20 PQI_D21 PQI_D22 PQI_D23 127 129 130 131 132 133 134 135 13 14 89 52 56 17 45 31 19 46 85 86 87 59 70 48 49 50 57 83 84 91 137 1 12 18 35 58 PQI_D24 PQI_D25 PQI_D26 PQI_D27 PQI_D28 PQI_D29 PQI_D30 PQI_D31 PQI_INT# PQI_RST# PQI_rw# PQI_TA# PQI_tea# PQI_Ts# PQI_tsiz0 PQI_tsiz1 RESERVED_NC RESERVED_VDD RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_NC TEST_EN VDDC VDDC VDDC VDDC 92 123 15 27 40 51 66 78 104 114 126 138 90 6 30 55 79 101 125 23 44 53 64 76 88 102 116 128 141 11 34 54 73 94 113 136 VDDC VDDC VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS12 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VDDS2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 43 .10 . . .Pin. .List ................................... 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PQI_D11 PQI_D10 PQI_D9 PQI_D8 VDDS PQI_D7 VSS VDDS2 PQI_D6 PQI_D5 PQI_D4 PQI_D3 PQI_D2 PQI_D1 VSS2 PQI_D0 VDDC RESERVED_VSS VDDS12 PQI_RW# VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS RESERVED_VSS PQI_A31 PQI_A30 PQI_A29 VDDS2 VDDS PQI_A28 VSS PQI_A27 PQI_A26 VSS2 10.4 PQI Mode Pinout 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PQI_A25 PQI_A24 RESERVED_VSS PQI_A23 PQI_A22 PQI_A21 VDDS PQI_A20 VSS PQI_A19 PQI_A18 PQI_A17 PQI_A16 RESERVED_VSS VDDC RESERVED_VSS PQI_TEA# VDDS2 VSS2 VSS PQI_TA# VDDS RESERVED_VSS RESERVED_VSS RESERVED_VSS PQI_BURST# RESERVED_VDD PQI_TSIZ0 VSS PQI_A15 PQI_A14 PQI_A13 VDDS PQI_A12 PQI_A11 PQI_A10 TEST_EN JTDO JTCK JTRST# EEPROM_EN VDDS2 EEPROM_DO EEPROM_CS EEPROM_SK EEPROM_DI VSS2 VDDC PQI_INT# PQI_RST# VDDS PQI_CLK PQI_TS# VDDC RESERVED_NC PQI_A0 PQI_A1 PQI_A2 VSS PQI_A3 PQI_A4 PQI_A5 VDDS PQI_A6 PQI_A7 VDDS2 PQI_TSIZ1 PQI_CS# PQI_A8 VSS2 VDDC PQI_A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PQI_D12 PQI_D13 PQI_D14 PQI_D15 VSS2 VDDS PQI_D16 VSS PQI_D17 PQI_D18 PQI_D19 PQI_D20 PQI_D21 PQI_D22 VDDC PQI_D23 VDDS2 VDDS PQI_D24 VSS PQI_D25 PQI_D26 PQI_D27 PQI_D28 PQI_D29 PQI_D30 PQI_D31 VSS2 RESERVED_NC VDDS AVS AVD VSS JTMS JTDI PLL_REF Figure 11 PQI Mode Pinout Drawing ...... 44 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... 11 Physical Specifications 11.1 LQFP 144-pin Plastic Quad Flatpack 2 2 .0 0 .2 M 0~10 0.145 +0.055 -0.04 5 0.0 8 1.7 MAX 0.0 8 +0.05 -0.04 1.40.05 0.5 0.10.05 0.2 2 1 .25 T YP 22.00.2 20.00.1 2 0.0 0.1 0 .45 m in , 0 .7 5m a x All u nits in m illim e ters Figure 12 144 LQFP Package ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 45 .11 . . .Physical . . . . .Specifications ................................ THIS PAGE INTENTIONALLY LEFT BLANK. ...... 46 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... I Errata Errata are design defects or errors. Errata may cause the product behavior to deviate from published specifications. I.1 Document Revision 01 None. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 47 .Errata ........................................ THIS PAGE INTENTIONALLY LEFT BLANK. ...... 48 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... II Specification Clarifications Specification clarifications describe any new product specifications, changes to prior product specifications, provide greater detail for a particular specification item, or further highlight a specification's impact to a complex design situation. This section outlines any specification clarifications incorporated in each document revision. II.1 Document Revision 01 None. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 49 .Specification . . . . . . .Clarifications ................................. THIS PAGE INTENTIONALLY LEFT BLANK. ...... 50 7955- Security Accelerator - Data Sheet, DS-0114-01 ......................................... III Document Changes/Revisions Documentation changes include additions, deletions, and modifications made to this document. This section identifies the changes made in each release of the document. III.1 Document Revision 01 Update 1. Added PCI Mode and PQI Mode Pinout drawings. Section 10. ...... 7955 - Security Accelerator - Data Sheet, DS-0114-01 51 .Document . . . . . Changes/Revisions ................................... THIS PAGE INTENTIONALLY LEFT BLANK. ...... 52 7955- Security Accelerator - Data Sheet, DS-0114-01 750 University Avenue Los Gatos, California 95032 tel: 408.399.3500 fax: 408.399.3501 web:www.hifn.com