7955
Security Accelerator
Data Sheet
750 University Ave. ● Los Gatos, CA 95032 ● E:info@hifn.com ● P:408.399.3500 ● F: 408.399.3501
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DS-0114-01, © 2003, Hi/fn®, Inc. All rights reserved. 12/03
No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any
language in any form by any means without the written permission of Hi/fn, Inc. (“Hifn”)
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Disclaimer
Hifn reserves the right to make changes to its products, including the contents of this document, or to discontinue any product
or service without notice. Hifn advises its customers to obtain the latest version of relevant information to verify, before
placing orders, that information being relied upon is current. Every effort has been made to keep the information in this
document current and accurate as of the date of this document’s publication or revision.
Hifn warrants performance of its products to the specifications applicable at the time of sale in accordance with Hifn’s
standard warranty or the warranty provisions specified in any applicable license. Testing and other quality control techniques
are utilized to the extent Hifn deems necessary to support such warranty. Specific testing of all parameters, with the
exception of those mandated by government requirements, of each product is not necessarily performed.
Certain applications using Hifn products may involve potential risks of death, personal injury, or severe property or
environmental damage (“Critical Applications”). Hifn products are not designed, intended, authorized, or warranted to be
suitable for use in life saving, or life support applications, devices or systems or other critical applications. Inclusion of Hifn
products in such critical applications is understood to be fully at the risk of the customer. Questions concerning potential risk
applications should be directed to Hifn through a local sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be
provided by the customer to minimize inherent or procedural hazards. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals,” should be validated for each customer application by the
customer’s technical experts.
Hifn does not warrant that its products are free from infringement of any patents, copyrights or other proprietary rights of
third parties. In no event shall Hifn be liable for any special, incidental or consequential damages arising from infringement
or alleged infringement of any patents, copyrights or other third party intellectual property rights.
The use of this product in stateful compression protocols (for example, PPP or multi-history applications) with certain
configurations may require a license from Motorola. In such cases, a license agreement for the right to use Motorola patents
may be obtained through Hifn or directly from Motorola.
Patents
May include one or more of the following United States patents: 4,701,745; 5,003,307; 5,016,009; 5,126,739; 5,146,221;
5,414,425; 5,463,390; 5,506,580; and 5,5532,694. Other patents pending.
Trademarks
Hi/fn®, MeterFlow®, MeterWorks®, and LZS®, are registered trademarks of Hi/fn, Inc. HifnTM, FlowThroughTM, and the Hifn
logo are trademarks of Hi/fn, Inc. All other trademarks and trade names are the property of their respective holders.
Exporting
This product may only be exported from the United States in accordance with applicable Export Administration Regulations.
Diversion contrary to United States laws is prohibited.
7955 - Security Accelerator - Data Sheet, DS-0114-01 iii
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Contents
List of Figures...........................................................................................................................v
List of Tables..........................................................................................................................vii
Preface...................................................................................................................................... ix
About This Document............................................................................................................................. ix
Audience .................................................................................................................................................. ix
Prerequisite............................................................................................................................................. ix
Document Conventions........................................................................................................................... ix
Customer Support.................................................................................................................................... x
Web Site ................................................................................................................................................... x
1 Product Description..........................................................................................................1
2 Features................................................................................................................................3
2.1 High Performance ......................................................................................................................... 3
2.2 Major Security and Compression Protocol Support.................................................................... 3
2.3 Multiple Host Bus Interface Modes ............................................................................................. 3
2.4 Low Host Overhead....................................................................................................................... 4
2.5 Advanced Cryptographic Engines................................................................................................ 4
2.6 Software Support .......................................................................................................................... 4
2.7 Other Features .............................................................................................................................. 4
3 Performance Summary.....................................................................................................5
3.1 Symmetric Key Processing Units................................................................................................. 5
3.2 Protocol Performance .................................................................................................................... 6
3.3 Public Key...................................................................................................................................... 6
4 Block Diagram....................................................................................................................9
4.1 Operation ....................................................................................................................................... 9
4.2 Security Processing ..................................................................................................................... 10
4.2.1 Muting Table ........................................................................................................................ 11
4.2.2 Public Key Processing.......................................................................................................... 11
5 Configuration Options....................................................................................................13
5.1 Core Clock Configuration ........................................................................................................... 13
5.2 EEPROM and Hardware Configuration.................................................................................... 13
5.2.1 EEPROM Memory Map....................................................................................................... 15
5.2.2 Configuration without EEPROM........................................................................................ 16
5.3 Endianness Configuration......................................................................................................... 16
5.3.1 Device Endianness Configuration....................................................................................... 17
5.3.2 Device Endianness Configuration Examples ..................................................................... 19
6 Signal Description ...........................................................................................................21
6.1 Signal Overview .......................................................................................................................... 21
Contents
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6.1.1 PCI Signal Overview............................................................................................................ 21
6.1.2 PowerQuicc I Signal Overview............................................................................................ 22
6.2 Detailed Signal Description........................................................................................................ 23
7 Timing Specifications .....................................................................................................27
7.1 AC Operating Conditions............................................................................................................ 27
7.2 Host Bus Interface Clock ............................................................................................................ 27
7.3 PCI Timing .................................................................................................................................. 28
7.4 PowerQuicc_I Timing.................................................................................................................. 29
7.5 EEPROM ..................................................................................................................................... 31
8 DC Specifications.............................................................................................................33
8.1 Absolute Maximum Ratings ....................................................................................................... 33
8.2 Power Sequencing ....................................................................................................................... 33
8.3 Recommended Operating Conditions ........................................................................................ 34
8.4 DC Characteristics...................................................................................................................... 34
9 Thermal Specifications...................................................................................................37
9.1 Heat Sink Requirements ............................................................................................................ 37
9.2 Junction Temperature Specifications ........................................................................................ 37
10 Pin List ...............................................................................................................................39
10.1 PCI-Mode Pin List ................................................................................................................... 39
10.2 PCI-Mode Pin List (by Category)............................................................................................ 40
10.3 PCI Mode Pinout ..................................................................................................................... 41
10.3.1 PQI-Mode Pin List ............................................................................................................ 42
10.3.2 PQI Mode Pin List (by Category) ..................................................................................... 43
10.4 PQI Mode Pinout ..................................................................................................................... 44
11 Physical Specifications...................................................................................................45
11.1 LQFP 144-pin Plastic Quad Flatpack .................................................................................... 45
I Errata..................................................................................................................................47
I.1 Document Revision 01 ................................................................................................................ 47
II Specification Clarifications...........................................................................................49
II.1 Document Revision 01 ................................................................................................................ 49
III Document Changes/Revisions.......................................................................................51
III.1 Document Revision 01............................................................................................................. 51
7955 -Security Accelerator - Data Sheet, DS-0114-01 v
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List of Figures
Figure 1 Example System Concept, MPC versus PCI Interface Mode............................................... 1
Figure 2 Block Diagram ........................................................................................................................ 9
Figure 3 Hardware Configuration Options ........................................................................................ 14
Figure 4 Endianness Transfer Modes................................................................................................. 18
Figure 5 PCI Host Bus Interface Signals ........................................................................................... 21
Figure 6 PowerQuicc_I Host Bus Interface Signals .......................................................................... 22
Figure 7 Input Bus Clock Timing ....................................................................................................... 27
Figure 8 Read/Write Timing (PQI bus) .............................................................................................. 30
Figure 9 EEPROM Timing .................................................................................................................. 31
Figure 10 PCI Mode Pinout Drawing ................................................................................................... 41
Figure 11 PQI Mode Pinout Drawing ................................................................................................... 44
Figure 12 144 LQFP Package ............................................................................................................... 45
List of Figures
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List of Tables
Table 1 Ordering Information ................................................................................................................ 4
Table 2 Processing Unit Performance ................................................................................................... 5
Table 3 Protocol Processing Performance ............................................................................................. 6
Table 4 IKE Performance ....................................................................................................................... 6
Table 5 Public Key Performance (133 MHz Operation) ....................................................................... 6
Table 6 Description of the functional units......................................................................................... 10
Table 7 EEPROM Memory Map .......................................................................................................... 15
Table 8 Host Bus Mode Configuration without EEPROM................................................................. 16
Table 9 Host Bus Endian Configuration without EEPROM.............................................................. 16
Table 10 PCI Register Configuration without EEPROM .................................................................. 16
Table 11 7955 Endianness Configuration .......................................................................................... 17
Table 12 Endianness Mapping of System Data ................................................................................. 17
Table 13 64-bit Host Data Endianness Control ................................................................................. 19
Table 14 PCI Signals............................................................................................................................ 23
Table 15 PowerQuicc_I Signals ........................................................................................................... 23
Table 16 Hardware Configuration and EEPROM Signals ................................................................ 24
Table 17 PLL Signals........................................................................................................................... 25
Table 18 JTAG signals......................................................................................................................... 25
Table 19 Power and Ground signals ................................................................................................... 26
Table 20 AC Operating Conditions ..................................................................................................... 27
Table 21 PCI_CLK Timing ..................................................................................................................27
Table 22 PQI_CLK Timing ..................................................................................................................28
Table 23 PLL_REF Clock..................................................................................................................... 28
Table 24 PCI 66MHz and 33MHz Timing Parameters...................................................................... 28
Table 25 Read/Write Timing (PQI bus) .............................................................................................. 29
Table 26 EEPROM Timing .................................................................................................................. 31
Table 27 Absolute Maximum Ratings................................................................................................. 33
Table 28 Recommended Operating Conditions .................................................................................. 34
Table 29 DC Electrical Characteristics .............................................................................................. 34
Table 30 Thermal Specifications ......................................................................................................... 37
Table 31 Thermal Resistance ..............................................................................................................37
Table 32 PCI-Mode Pin List (Numeric) .............................................................................................. 39
Table 33 PCI-Mode Pin List (Signal Category).................................................................................. 40
Table 34 PQI-Mode Pin List (Numeric) .............................................................................................. 42
Table 35 PQI-Mode Pin List (Signal Category).................................................................................. 43
List of Tables
viii 7955- Security Accelerator - Data Sheet, DS-0114-01
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Preface
Welcome to the Data Sheet for the Hifn 7955 network security processors family. This document
provides feature, performance, and interface information and specifications for the 7955.
The reader is assumed to have a general knowledge of Hifn 795x architecture. The 7955 is the
newest members of the 795x family of algorythm accelerators, which began with the Hifn 7951. For
register descriptions, definitions of data structures, and general usage information, refer to the
7954/7955/7956 Har d ware Users Guide (UG-0034).
About This Document
This document assumes you are already familiar with the chip technology and terminology.
Audience
This document is intended for integrators and application developers responsible for and familiar
with software and hardware architecture of a target system.
Prerequisite
None
Document Conventions
The following conventions will be used throughout this document:
! Italic typeface indicates file names, book titles, new words or terms, words to be
emphasized.
! SIGNAL names appear in Bold Small Caps.
Preface
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Customer Support
For technical support about this product, please contact your local Hifn sales office, representative,
or distributor.
Web Site
For general information about Hifn and Hifn products refer to: www.hifn.com.
7955 - Security Accelerator - Data Sheet, DS-0114-01 1
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1 Product Description
High Performance- The Hifn TM 7955 Security Accelerator supports multi-protocol algorithm
processing. Optimized for OC3/T3 Applications, 7955 Security Accelerator achieves over 250 Mbps
full-duplex sustained performance with simultaneous encryption, compression, and authentication of
large packets (1500 Bytes).
Highly Integrated- All major security/compression protocols are supported. The 7955 is an ideal
security solution for VPN enabled routers, remote access concentrators, VPN gateways, firewalls,
and WAN switches. The 7955’s integrated high-speed compression engines also makes it ideal for
wireless applications. IPSec algorithms include AES-128, AES-192, AES-256, DES, 3DES, and
ARC4 encryption. The 7955 supports SHA-1 and MD5 authentication, LZS and MPPC compression.
AES Support- The 7955 fully supports the new Advanced Encryption Standard, AES, with key
lengths of 128, 192 & 256-bits. It also supports AES counter-mode.
Integrated Public-Key Processing- The 7955 contains an on-chip public-key subsystem. SSL,
TLS, and IKE algorithms include RSA, DSA, and Diffie-Hellman operations.
Host Bus Interface- The 7955 is equipped with a configurable PCI-2.2 compliant interface,
enabling direct connection to any PCI host system. The 7955 also offers a glueless interface to the
MPC860 bus.
Compatibility- The 7955 is software-compatible with the Hifn 79xx family.
7955
MPC CPU
(860) PowerQuicc I Bus (32-bit @ 4 0 MHz )
WAN/LAN
Ports System
Memory
CPU
7955
System
Controller
System
Memory
PCI Host Bus (32/64-bit @ 66 MHz )
WAN Ports LA N Por t s
Figure 1 Example System Concept, MPC v ersus PCI Interface Mode
1 Product Description
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2 Features
2.1 High Performance
! Supports IPSec processing at OC3 and higher data rates (for 1500-byte packets)
! Processes entire packet (compression, encryption, and authentication) in a single pass
! Supports concurrent Public-Key and Symmetric Key processing
! Integrated Public Key processor
# IPSec performance; 75 Diffie-Hellmann quick-mode connections/s (1024-bit)
# SSL performance; 40 RSA signatures/s (1024-bit)
! Compression engine runs at over 250 Mbps and increases effective throughput
! Supports 128 Security Associations (SA) on-chip, and unlimited in host memory.
2.2 Major Security and Compression Protocol
Support
! 128/192/256-bit AES (Advanced Encryption Standard), DES, 3DES, and ARC4 encryption
(ARC4 is fully compatible with RSA’s RC4TM algorithm)
! SHA-1 and MD5 hashing and authentication
! LZS and MPPC compression
! Public-key support includes RSA, DSA, SSL, IKE, and Diffie-Hellman
! Supports up to 3072-bit modular arithmetic and exponentiation
! True Hardware Random Number Generator
2.3 Multiple Host Bus Interface Modes
! Bus mastering PCI-2.2 Interface at 33 or 66 MHz
! Efficient scatter/gather DMA engines handle fragmented host memory
! Programmable bus arbitration/utilization for PCI bandwidth control
2 Features
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! 64-byte FIFO input and output buffers support high-speed burst transfers
! Optional external serial EEPROM enables customized PCI configurations
! Direct MPC860/850 PowerQuicc bus (32-bit GPCM) interface, up to 4 word burst
2.4 Low Host Overhead
! Security context (encryption keys and other stateful parameters) may be stored in on-chip
memory to reduce host overhead
! Descriptor Based DMA engine (supports data scatter / gather) in PCI mode
! On-chip memory used to buffer control data packets
2.5 Advanced Cryptographic Engines
! Support for ECB, CBC, and CTR block-cipher modes of operation
! Multi-mode automatic padding
! Programmable mutable field MAC support for handling AH, IPv4, IPv6, and others
2.6 Software Support
! Supported by standard 79xx Hifn API
! API supports the full feature set of Hifn 79xx products
! API works with a wide variety of host architectures
2.7 Other Features
! Architecture compatibility with other Hifn 79xx Security Accelerators
! Supports low-cost implementation with 144-pin LQFP package
! JTAG support
! Reference hardware design
! 1.5V core with 3.3V I/O
! Typical dissipation <1W
Table 1 Ordering Information
Part Number Speed Description
7955PT6 66 MHz 144-pin LQFP 7955 Network Security Accelerator
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3 Performance Summary
The figures in this section summarize the performance of the 7955 Security Accelerator functional
units. Performance of the 7955 Security Accelerator when multiple engines are used (for example,
the compression, MAC and encryption engines are all engaged) can be approximated by using
throughput of the slowest engine.
The MAC and encryption engine speeds are accelerated (effectively multiplied) by the actual
compression ratio achieved by the compression engine. For example, if the achieved compression
ratio is 2:1, then the MAC and encryption engine speeds are effectively doubled and the compression
engine would be the slowest engine. This performance data reflects the following conditions:
! 66 MHz maximum internal core frequency
! 1500-byte packets.
! Single session or security association.
! Encoded text throughput
3.1 Symmetric Key Processing Units
Table 2 Processing Unit Performance
Protocol Performance @ 66 MHz (Mbps)
AES-128, 192, 256 365, 420, 460
3DES 340
ARC4 210
SHA-1 325
MD5 360
Stateless Stateful
LZS Compression 510 450
LZS Decompression 455 395
MPPC Compression 505 460
MPPC Decompression 420 425
Note
All performance numbers are based on simulation results.
Text from the United States Constitution was arbitrarily
selected for the compression and decompression simulations.
The compression ratio is approximately 2:1.
3 Performance Summary
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3.2 Protocol Performance
Table 3 Protocol Processing Performance
Performance @ 66 MHz
Protocol Throughput
(Mbps) Packets/Sec
IPSec (Tunnel; 3DES-CBC, SHA-1
HMAC)
325 27K
IPSec (Tunnel; AES-256, SHA-1
HMAC)
330 27K
IPSec (AH Tunnel; SHA-1 HMAC) 320 27K
3-DES, SHA-1, Stateless LZS 370 31K
PPTP (RC4, MPPC) 360 30K
Note
All performance numbers are based on simulation results. Text from
the United States Constitution was arbitrarily selected for the
compression and decompression simulations. The compression ratio is
approximately 2:1.
3.3 Public Key
Table 4 IKE Performance
IKE Handshake Connections/Sec
@ 133 MHz
Two 1024-bit Diffie-Hellman operations (Quick Mode) 70
Two 1024-bit Diffie-Hellman operations, 1 RSA sign, 2 RSA verifies (Main
Mode)
24
Four 1024-bit Diffie-Hellman operations, 1 RSA sign, 2 RSA verifies (Main
Mode + Quick Mode)
38
Note
180-bit exponent. The number of connections/sec is based on simulation results.
Table 5 Public Key Performance (133 MHz Operation)
Completion Time (ms) vs. Key Length (bits) Operation @ 66 MHz 2048 1024 768 512
RSA private key 82.75 11.88 4.69 1.75
RSA public key (3-bit exponent) .45 .12 .07 .03
Diffie-Hellman (180-bit exponent) 27.13 7.25 4.81 2.06
Diffie-Hellman (exponent = key
size)
308 41.25 20.50 5.88
DSA sign 12.94 7.78 3.75
DSA verify 19.41 11.66 5.63
Performance Summary
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Note
Performance numbers assume a uniform distribution of ones and zeros in the exponent. Actual
performance varies with the Hamming weight of the exponent. Performance numbers assume
that the public key module has unrestricted access to memory. Actual performance varies with
the memory usage of other system components. These numbers are only estimates and have not
been experimentally verified.
3 Performance Summary
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4 Block Diagram
4.1 Operation
The 7955 Security Accelerator contains several processing units - Public Key encryption, symmetric
key encryption, compression, padding, authentication, and Random Number Generator,. The
symmetric key encryption, compression, padding, and authentication units are combined into a
single functional block called the Packet Engine. The 7955 Security Accelerator also contains two
programmable DMA engines with time-multiplex capability to transfer control and traffic data,
source and destination FIFOs, PCI and PowerQuicc-I Host Interface.
PCI Rev 2.2 64/32-bits 66/33MHz Master
MPC PowerQuicc I Slave
Algorithm
Engines
AlgorithmAlgorithm
EnginesEngines
EncryptionEncryption
PK Engine
RNG
Fetch FIFOs
Post FIFOs
CompressionCompression
AuthenticationAuthentication
PK Operand
RAM (4KB)
JTAG
PLL
Interrupt
and C ontrol
Registers
Host Bus Interface (PCI or PQI)
Context
RAM (32KB)
EEPROM
Interface
Data Path
DMA (PCI)
Memory Ctrl Pipeline
uControl
EEPROM
Optional
PLL_REF
Figure 2 Block Diagram
4 Block Diagram
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Table 6 Description of the functional units
Block Description
Packet Engine The packet engine consist of the security, compression, padd ing,
and MAC (not shown ) processors. The packet engine contains
pipelined compression, encryption, padding and authentication
units, along with hardware for computing checksums, CRCs, and
LCBs. The packet engine is configured by a command message
prior to the start of each packet or task.
Public-Key Processor The public-key processor incorporates enhanced features, providing
hardware acceleration of public-key or symmetric key calculations
on keys of up to 3,072 bits. The public-key processor also contains a
hardware true-random number generator. It is accessible from both
the PCI or MPC interfaces.
Context RAM The 32KB local memory is used for the storage of information such
as descriptor, command, or per-session security context data. It
may also contain I/O packet buffers.
Inbound/Outbound
DMA Units
When the 7955 Security Accelerator is operating in PCI-bus mode,
the inbound and outbound DMA units are special-purpose block-
transfer engines controlled by the 7955 Security Accelerator. The
inbound DMA unit transfers commands and unprocessed packets
from PCI to the 7955 Security Accelerator’s security processing
core, while the outbound DMA unit transfers processed packets and
status information from security core to PCI. Fragmented buffers
are supported through scatter/gather features in the DMA
hardware. Internal FIFOs provide buffering to allow high-speed
burst transfers.
When the 7955 Security Accelerator is operating in slave-bus MPC
mode, the PCI portion of the inbound/outbound DMA unit is
disabled, and the PowerQuicc_I logic is enabled.
PCI Interface The PCI interface is both an efficient bus master and an efficient
bus target. It becomes a bus master for either the inbound DMA
unit, or the outbound DMA unit. As a PCI slave, it services
requests by the PCI host to access 7955 Security Accelerator
registers and private memory.
PowerQuicc_I The PowerQuicc_I interface is an alternate I/O interface supporting
direct host interface to MPC860/850.The MPC interface shares pins
with the PCI interface, so both cannot be active in the same design.
7955 Security Accelerator
Registers The 7955 Security Accelerator registers control the operation of the
subsystem. They are memory-mapped to both the MPC and PCI.
EEPROM /
Hardware Configuration
Interface
This interface supports an optional serial EEPROM used to
configure the device registers at reset. If no EEPROM is used, the
interface can be used to select default configuration, including host
bus interface mode.
4.2 Security Processing
The 7955 DMA channels and associated controller are designed to off-load the host from having to
move numerous copies of data and associated context for each iteration of security processing.
Locally accessible descriptor, command and context further relieve the host from having to move
Block Diagram
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multiple control data packets between the host and target to perform necessary security related
processing.
4.2.1 Muting Table
An on-board muting table memory provides the mask that controls the input to the MAC processor.
The mask nulls specific segments of the data packet prior to being submitted to the MAC processor.
The masks are programmable through the host bus & are selected by the MAC descriptor.
4.2.2 Public Key Processing
7955 uses an enhanced PK processor. To further optimize the PK acceleration, 7955 PK processor is
equipped with a 16 Opcode FIFO and access to intermediate results is provided. PK processor
operates on a batch of modular arithmetic instructions (up to 16) and issues an interrupt once the
operand FIFO is empty. Since each modular arithmetic instruction (nano instruction) execution is
host independent, the host is only expected to setup the PK engine and retrieve the result upon
reception of PK interrupt.
4 Block Diagram
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5 Configuration Options
The 7955 Security Accelerator supports a five-pin configuration interface that is used during
hardware reset to select the host bus mode and to set up critical register values. This configuration
information may be contained in a serial EEPROM attached to the interface. Otherwise, a default
configuration can be selected by the applying a value to the interface during hardware reset.
5.1 Core Clock Configuration
When the 7955 comes out of reset the core logic is directly driven by the host bus interface clock,
HBI_CLK (PCI_CLK or PQI_CLK depending on the bus mode selected). During register
intialization, the on-chip PLL is enabled and programmed appropriately if a multiple of one of the
input clocks (host bus interface or PLL_REF) is needed to maximize the 7955’s performance. The
clock configuration circuit provides maximum flexibility allowing the 7955 to be clocked
synchronously or asynchronously to its host bus interface. Refer to the PLL Configuration Register
section in the 7954/7955/7956 Har dware Users Guide (UG-0034) for details on configuring the clock
circuit.
Note
The PLL_REF input signal may not be required in some systems to achieve
maximum performance (see Table 17 for more information on use of this input
signal). Care must be exercised in configuring the clock circuit to prevent the core
logic from being over-clocked.
5.2 EEPROM and Hardware Configuration
This section describes how the 5-pin serial EEPROM interface is used to configure the 7955 as it
comes out of reset. The 7955 is designed so that the use of an external serial EEPROM is optional.
When the 7955 comes out of reset (rising edge of the RST# signal), the EEPROM_EN signal is
sampled to determine if an exteranl EEPROM is present or not. If EEPROM_EN is tied high, the
7955 will determine that an EEPROM is present and begin loading configuration register values
from it. Aside from internal register logic, the remainder of the 7955, including the host interface, is
held in a reset state for 20K clock cycles (the time it takes to load register values from EEPROM).
If EEPROM_EN is tied low, the 7955 will determine that there is no external EEPROM present as
the device comes out of reset. However, in non-EEPROM configurations, the remaining 4 EEPROM
signals are designed to be individually tied high and low (see section 5.2.2) on the PCB to enable
additional 7955 configuration options.
5 Configuration Options
14 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7955
Security
Accelerator Hardware
Configuration
Option Flag
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
7955
Security
Accelerator EEPROM
Local Configuration
Memory
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
Figure 3 Hardware Configuration Options
Configuration Options
7955 - Security Accelerator - Data Sheet, DS-0114-01 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
5.2.1 EEPROM Memory Map
Table 7 EEPROM Memory Map
EEPROM
Address
(H)
Bit
Field Name Description
Default
Value
(H)
0x00 1:0 HBI Select Host Bus Interface Select 0x0
0x00 3:2 reserved 0x0
0x00 4 HBI_SWAP8* Endian Byte Swap 0x0
0x00 5 HBI_SWAP32* Endian Double-Word Swap 0x0
0x00 15:6 reserved 0x0
0x01 15:0 PCI Vendor ID 0x13A3
0x02 15:0 PCI Device ID 0x0020
0x03 15:0 PCI Class Code [23:8] 0x0B40
0x04 15:8 PCI Class Code [7:0] 0x00
0x04 7:0 RESERVED 0x00
0x05 15:8 PCI Revision ID 0x00
0x05 7:0 RESERVED 0x00
0x06 15:8 PCI BIST 0x00
0x06 7:0 RESERVED 0x00
0x07 15:8 PCI Header Type 0x00
0x07 7:0 RESERVED 0x00
0x08 15:0 PCI Subsystem ID 0x0000
0x09 15:0 PCI Subsystem Vendor ID
0x0A 15:8 PCI Max_Lat 0x00
0x0A 7:0 PCI Min_Gnt 0x00
0x0B 15:8 PCI Interrupt Pin 0x00
0x0B 7:0 RESERVED 0x00
0x0C 15:0 RESERVED 0x00
0x0D 15:0 RESERVED 0x00
0x0E 15:0 RESERVED 0x00
0x0F 15:0 RESERVED 0x00
0x10 0 PQ_ADD_DEcODE_EN Address decode enable 0x0
0x10 1 RESERVED 0x0
0x10 15:2 RESERVED 0x0000
0x11 15:0 PQ_Base_ADD Base address 0x0000
0x12 -
0x1F 15:0 RESERVED 0x0000
0x20 -
0x2F 15:0 RESERVED 0x0000
0x30 -
0x3F 15:0 RESERVED 0x0000
Notes:
* Refer to Section 5.3 for endianness control.
5 Configuration Options
16 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Configuration without EEPROM
If the EEPROM_EN input is tied low, the EEPROM interface signals are used as simple
configuration inputs. EEPROM_CS and EEPROM_SK select the Host Bus mode, while
EEPROM_DI and EEPROM_DO select the endian settings.
Table 8 Host Bus Mode Configuration without EEPROM
EEPROM_CS EEPROM_SK Host Bus Mode
0 0 PCI Bus Mode
0 1 Reserved
1 0 PowerQuicc-I Bus Mode
1 1 Asynchronous SRAM Bus Mode
Table 9 Host Bus Endian Configuration without EEPROM
EEPROM_DI EEPROM_DO Host Bus Endian Mode
0 0 SWAP[32,8] = 00
0 1 SWAP[32,8] = 01
1 0 SWAP[32,8] = 10
1 1 SWAP[32,8] = 11
Table 10 PCI Register Configuration without EEPROM
Field Size in bits Default Value
Vendor ID 16 0x13A3
Device ID 16 0x0020
Class Code 16 0x0B40
Class Code 8 0x00
Revision ID 8 0x01
BIST 8 0x00
Subsystem ID 16 0x0000
Subsystem
Vendor ID
16 0x0000
5.3 Endianness Configuration
The internal data endianness format of the 7955 is 64-bit Little-Endian. However, the 7955 is
capable of functioning with four different host interface modes; 64-bit PCI-2.2 and 32-bit
PowerQuicc-I.
Endianness configuration is controlled for the following data paths:
! Target access to Registers (EEPROM Memory Map)
! Target access to Local-RAM (DMA Configuration Register #1)
! Target access to PKRAM (DMA Configuration Register #2)
Configuration Options
7955 - Security Accelerator - Data Sheet, DS-0114-01 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
! Initiator access to external descriptors (DMA Configuration Register #1)
! Initiator access to external data (Descriptor Structures)
Initiator access to Local-RAM for internal descriptors and data is always in Little-Endian format.
Target access to Local-RAM must be configured appropriately to preserve internal Little-Endian
format.
5.3.1 Device Endianness Configuration
Independent 2-bit fields will determine the endianness of each of these 5 data paths. The 2-bit field
comprise of SWAP8 bit, which controls byte transposition of a 32-bit entity, and SWAP32 bit that
controls swapping within a 64-bit entity. To the extent possible, these two bits are adjacent and the
SWAP32 bit is the significant bit position.
Table 11 7955 Endianness Configuration
Endianness Conf iguration System Data Format
HBI_SWAP32 HBI_SWAP8 32-bit 64-bit
0 0 Little-Endian Little-Endian
0 1 Big-Endian Big-Endian (Double-Word
Swapped)
1 0 Little-Endian (Double-
Word Swapped)
1 1
RESERVED
Big-Endian
Table 12 Endianness Mapping of System Data
System Data Format
System
Endianness
Mode Byte[7] Byte[6] Byte[5] Byte[4] Byte[3] Byte[2] Byte[1] Byte[0]
32-bit Little-
Endian Byte[3] Byte[2] Byte[1] Byte[0]
32-bit Big-
Endian
RESERVED
Byte[0] Byte[1] Byte[2] Byte[3]
64-bit Little-
Endian Byte[7] Byte[6] Byte[5] Byte[4] Byte[3] Byte[2] Byte[1] Byte[0]
64-bit Little-
Endian (DW
swapped) Byte[3] Byte[2] Byte[1] Byte[0] Byte[7] Byte[6] Byte[5] Byte[4]
64-bit Big-
Endian Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] Byte[7]
64-bit Big-
Endian (DW
swapped) Byte[4] Byte[5] Byte[6] Byte[7] Byte[0] Byte[1] Byte[2] Byte[3]
5 Configuration Options
18 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B3 B2 B0
B1
B0 B2 B3
B1
32-bit Big-Endian
B3 B2 B0
B1
B3 B2 B0
B1
32-bit Little-Endian
B7B6B4 B5 B3B2B0 B1
B7 B6 B4
B5 B3 B2 B0
B1
64-bit Big-Endian (Double-Word Swapped)
B7B6B4 B5
B3B2B0 B1
B7 B6 B4
B5 B3 B2 B0
B1
64-bit Big-Endian
B7 B6 B4
B5 B3 B2 B0
B1
B7 B6 B4
B5 B3 B2 B0
B1
64-bit Little-Endian
B7 B6 B4
B5 B3 B2 B0
B1
B7 B6 B4
B5
B3 B2 B0B1
64-bit Little-Endian (Double-Word Swapped)
Figure 4 Endianness Transfer Modes
Configuration Options
7955 - Security Accelerator - Data Sheet, DS-0114-01 19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
5.3.2 Device Endianness Configuration Examples
Table 13 64-bit Host Data Endianness Control
Endianness Conf iguration System Data Format
HBI_SWAP32 HBI_SWAP8 32-bit Mode Transferred Data 64-bit Mode Transferred Data
0 0 0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 1 6
7
4
5
2
3
0
1
8
9
A
B
C
D
E
F
6
7
4
5
2
3
0
1
1 0 E
F
C
D
A
B
8
9
6
7
4
5
2
3
0
1
1 1
RESERVED 6
7
4
5
2
3
0
1
E
F
C
D
A
B
8
9
5 Configuration Options
20 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THIS PAGE INTENTIONALLY LEFT BLANK.
7955 - Security Accelerator - Data Sheet, DS-0114-01 21
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Signal Description
The 7955 Security Accelerator supports two different Host Bus Interface modes; PCI 2.2 and
PowerQuicc I. All other signals are used for configuration and testing.
6.1 Signal Overview
6.1.1 PCI Signal Overview
7955
Security
Accelerator
(PCI mode) PLL_REF
AVS
AVD
PCI_RST#
PCI_CLK
PCI_AD[31:0]
32
PCI_CBE#[7:0]
8
PCI_REQ#
PCI_GNT#
PCI_REQ64#
PCI_ACK64#
PCI_IDSEL
PCI_FRAME#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_INTA#
PCI_PAR
PCI_PAR64
PCI_PERR#
PCI_SERR#
PCI_IRDY#
PCI_AD[63:32]
32
JTRST#
JTMS
JTDO
JTDI
JTCK
TEST_EN
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
Core
Clock
PLL
EEPROM
Config
Interface
PCI 2.2
Host Bus
Interface
JTAG
Test
Interface
Tied Low
Figure 5 PCI Host Bus Interface Signals
6 Signal Description
22 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 PowerQuicc I Signal Overview
7955
Security
Accelerator
(PowerQuicc_I m od e)
PLL_REF
AVS
AVD
JTRST#
JTMS
JTDO
JTDI
JTCK
TEST_EN
EEPROM_EN
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
PQI_RST#
PQI_CLK
PQI_A[0:31]
32
PQI_TA#
PQI_RD/W R#
PQI_BURST#
PQI_TEA#
PQI_TS#
PQI_D[0:31]
32
PQI_TSIZ[0:1]
2
PQI_INT#
PQI_CS#
Figure 6 PowerQuicc_I Host Bus Interface Signals
Signal Description
7955 - Security Accelerator - Data Sheet, DS-0114-01 23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
6.2 Detailed Signal Description
The 7955 provides a PCI 2.2 compliant interface mode. The following PCI signals are supported.
Table 14 PCI Signals
PCI Signals I/O (Buffer type) Description
PCI_CLK Input (I-PCI) PCI clock
PCI_RST# Input (I-PCI) PCI reset. Master reset for 7954.
PCI_IDSEL Input (I-PCI) PCI initialization device select.
PCI_REQ# Output (TS-PCI) PCI bus request.
PCI_GNT# Input (I-PCI) PCI bus grant.
PCI_AD[63:0] I/O (I/O-PCI) PCI address/data bus.
PCI_PAR I/O (I/O-PCI) PCI Parity signal; even parity across PCI_AD[31:0] and
PCI_CBE#[3:0]
PCI_PAR64 I/O (I/O-PCI) PCI Parity Upper DWORD signal for PCI_AD[63:32] and
PCI_CBE#[7:4]. The PCI_PAR64 port is used only when
the interface is configured with a 64-bit AD bus.
PCI_CBE#[7:0] I/O (I/O-PCI) PCI bus command/byte-enable bits.
PCI_FRAME# I/O (I/O-PCI) PCI cycle frame.
PCI_TRDY# I/O (I/O-PCI) PCI target ready.
PCI_IRDY# I/O (I/O-PCI) PCI initiator ready.
PCI_DEVSEL# I/O (I/O-PCI) PCI device select.
PCI_STOP# I/O (I/O-PCI) PCI stop.
PCI_PERR# I/O (I/O-PCI) PCI parity error.
PCI_SERR# Output (TS-PCI) PCI system error.
PCI_ACK64# I/O (I/O-PCI) PCI Acknowledge 64-Bit Transfer signal. The PCI_ACK64#
is used only when the interface is configured with a 64-bit
AD bus.
PCI_REQ64# I/O (I/O-PCI) PCI Request 64-Bit Transfer signal. The PCI_REQ64# is
used only when the interface is configured with a 64-bit AD
bus.
PCI_INTA# Output (TS-PCI) PCI interrupt request.
Notes:
Buffer Type: I-PCI=PCI input, I/O-PCI=PCI Bidirectional, TS-PCI=PCI Tri-State output
Table 15 PowerQuicc_I Signals
PowerQuicc_I Signal I/O (Buffer type) Description
PQI_CLK Input (I-PQ) Clock input, for the PowerQuicc_I interface bus clock
PQI_RST# Input (I-PQ) Chip reset. Master reset for 7954.
PQI_CS# Input (I-PQ) External space chip-select. Active-low chip-select for memory
space.
PQI_A[0:31] Input (I/O-PQ) PowerQuicc_I address bus. Only 32-bit word aligned
addresses are supported and PQI_TEA# will be asserted if
PQI_A[31:30] are not held low during the transfer.
PQI_BURST# Input (I/O-PQ) PowerQuicc_I transfer burst
PQI_D[0:31] I/O (I/O-PQ) PowerQuicc_I data bus
PQI_RD/WR# Input (I/O-PQ) PowerQuicc_I read/write enable
PQI_TA# Tri-state Output
(I/O-PQ) PowerQuicc_I transfer acknowledge
PQI_TEA# Tri-state Output
(TS-PQ) PowerQuicc_I transfer error acknowledge
6 Signal Description
24 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PQI_TS# Input (I-PQ) PowerQuicc_I transfer start
PQI_TSIZ[0:1] Input (I/O-PQ) PowerQuicc_I transfer size
PQI_TSIZ[0:1] PQI_BURST# Burst Size
00 1 4 bytes
00 0 16 bytes
PQI_INT# Open-Drain
Output (TS-PQ) PowerQuicc_I interrupt request
Notes:
Buffer Type: I-PQ=PQ input, I/O-PQ=PQ Bi-directional, TS-PQ=PQ Tri-State
output
Table 16 Hardware Configuration and EEPROM Signals
EEPROM Signal I/O (Buffer type) Description
TEST_EN Input (I) Test mode enable. It is normally tied low at all times
EEPROM_EN Input (I) Hardware configuration selectors to indicate PCI BARs,
memory size, etc. EEPROM configuration is selected when
this inputs is forced low.
EEPROM_CS I/O (I/O-O4) EEPROM chip select /
HW Configuration Address bit[0]
EEPROM_DI I/O (I) EEPROM serial data in /
HW Configuration Address bit[1]
EEPROM_DO I/O (I/O-O4) EEPROM serial data out /
HW Configuration Address bit[2]
EEPROM_SK I/O (I/O-O4) EEPROM clock /
HW Configuration Address bit[3]
Notes:
Buffer Type: I=Input, I/O-O4=I/O with 4mA output driver
Signal Description
7955 - Security Accelerator - Data Sheet, DS-0114-01 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
Table 17 PLL Signals
PLL Signal I/O Description
PLL_REF Input (CI)
PLL reference clock input or system clock (7955
Security Accelerator). This signal is completely
asynchronous to the host bus interface, HBI_CLK,
(PQI_CLK and PCI_CLK). On 7955 Security
Accelerator, this signal is the input to a clock-
multiplier PLL, which provides the clock for the
packet engine and PK processor subsystems.
Note
The 7955 requires a clock source to drive the PLL_REF input pin in all configurations. This
clock input pin must not be grounded when register to a 0b0 to select the HBI_CLK as the PLL
source will fail unless PLL the HBI_CLK (PQI_CLK or PCI_CLK) is used to drive the internal
PLL.
Programming bit 0 (PLL_REF_SEL) of the PLL Configuration _REF is driven by a clock source.
Once the PLL Configuration register has been programmed, the PLL_REF input requires four
rising edges to complete the PLL clock source reconfiguration. Once the four clocks have been
completed, the PLL lock time, as specified in the Timing Specifications shown in Table 22 for
PLL_REF, will begin.
When using PLL_REF as the clock source to the PLL, all timing requirements as stated in Table
22 must be met. When using PLL_REF to reconfigure the PLL source to the HBI_CLK, the clock
frequency still must not exceed the values specified in Table 22 but the minimum frequency
doesn’t apply. Any source that will provide the required four clocks can be used.
One solution for customers that use an EEPROM (EEPROM_EN=0b1) to configure the device is
to connect the EEPROM_SK signal to the PLL_REF input pin as well as to the EEPROM. In
this case, the PLL clock source is guaranteed to be configured to the HBI_CLK within 2050 PCI
clock periods after writing to the PLL Configuration register.
Note:
Buffer Type: CI=clock input
Table 18 JTAG signals
Test Signal I/O (Buffer type) Description
JTDI Input (PI) JTAG test data in
JTDO Output (TS-O4) JTAG test data out
JTMS Input (PI) JTAG test mode select
JTCK Input (PI) JTAG test clock
JTRST# Input (PI) JTAG test mode reset. This should not be tied to the
system reset signal. It is normally tied low at all times
except JTAG testing.
Note:
Buffer Type: PI-Input with pull-up resistor, TS-O4=Tri-State with 4mA output driver
6 Signal Description
26 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19 Power and Ground signals
Misc. Signal I/O Description
VSS Ground Digital ground for output buffers
VSS2 Ground
Digital ground for input buffers, internal arrays &
pre-buffers
VDDC Power Power for 1.5 V internal logic
VDDS Power Power for 3.3 V output buffers
VDDS2 Power
Power for 3.3 V input buffers & pre-
buffers
VDDS12 Power
Power for 3.3 V input & output buffers
& pre-buffers
Tie these
together
AVS Ground PLL Analog ground
AVD Power PLL 1.5 V Analog supply
RESERVED_VSS Input Must be tied to VSS (series resistor is optional)
RESERVED_NC Output Must not be connected
7955 - Security Accelerator - Data Sheet, DS-0114-01 27
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Timing Specifications
7.1 AC Operating Conditions
Table 20 AC Operating Conditions
Symbol Parameter Conditions*
VDDC
Supply voltage - Core 1.5V ± 5%
VDDS
Supply voltage – I/O 3.3V ± 10%
VSS
Ground potential 0V
TA Ambient operating temperature 0°C to +70°C
Note:
(*) See derating information below for other load conditions.
7.2 Host Bus Interface Clock
1
32
4 5
Figure 7 Input Bus Clock Timing
Table 21 PCI_CLK Timing
Number Description Min Max Units
Clock frequency DC 66.67 MHz
1
Clock period Infinite 15 ns
2 Clock width high 6 ns
3 Clock width low 6 ns
4 Clock rise time from VIL to VIH 2 ns
5 Clock fall time from VIH to VIL 2 ns
7 Timing Specifications
28 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22 PQI_CLK Timing
Number Description Min Max Units
Clock frequency DC 40 MHz
1
Clock period Infinite 25 ns
2 Clock width high 6 ns
3 Clock width low 6 ns
4 Clock rise time from VIL to VIH 2 ns
5 Clock fall time from VIH to VIL 2 ns
Table 23 PLL_REF Clock
Number Description Min Max Units
Clock frequency 20 100 MHz 1
Clock Period 50 10 ns
2 Clock width high 4.5 ns
3 Clock width low 4.5 ns
4 Clock rise time from VIL to VIH 2 ns
5 Clock fall time from VIH to VIL 2 ns
n/a Duty cycle 45 55 %
n/a Jitter (peak to peak) 100 ps
n/a PLL lock time 100*n usec
Note:
n = (PLL_ND+1)*2 (see the PLL Configuration Register description in the
7954/7955/7956 Hardware Users Guide (UG-0034) for more information on the
PLL_ND setting).
7.3 PCI Timing
Table 24 PCI 66MHz and 33MHz Timing Parameters
66MHz 33MHz
Symbol Parameter Min Max Min Max Units
Tval PCI_CLK to Signal Valid
Delay – bused signals
2 6 2 11 ns
Tval (ptp) PCI_CLK to Signal Valid
Delay – point to point signals
2 6 2 12 ns
Ton Float to Active Delay 2 2 ns
Toff Active to Float Delay 14 28 ns
Tsu Initial setup time to PCI_CLK
– bused signals
3 7 ns
Tsu
(ptp)
Initial setup time to PCI_CLK
– point to point signals
5 10,12 ns
Th Input Hold time from
PCI_CLK
0 0 ns
Trst Reset Active Time after power
stable
1 1 ms
Trst-clk Reset Active Time after
PCI_CLK stable
100 100 ms
Timing Specifications
7955 - Security Accelerator - Data Sheet, DS-0114-01 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . .
Trst-off Reset Active to output float
delay
40 40 ns
Trrsu PCI_REQ64# to PCI_RST#
setup time
10Tcyc 10Tcyc ns
trrh PCI_RST# to PCI_REQ# hold
time
0 50 0 50 ns
Trhfa PCI_RST# high to first
Configuration access
2 2 clocks
Trhff PCI_RST# high to first
PCI_FRAME# assertion
5 5 clock
Notes:
These specifications are taken from the PCI 2.2 Standard, section 7.6.4.2.
PCI_REQ# and PCI_GNT# are point to point signals and have different input
setup times than do bused signals.
7.4 PowerQuicc_I Timing
Table 25 Read/Write Timing (PQI bus)
Number Description Min Max Units
1 PQI_A[0:31], PQI_TS#, PQI_CS#, PQI_TSIZ[0:1],
PQI_RD/WR# setup 3 ns
2 PQI_A[0:31], PQI_TS#, PQI_CS#, PQI_TSIZ[0:1],
PQI_RD/WR# hold 0 ns
3 Write data setup 3 ns
4 Write data hold 0 ns
5 PQI_TA# high-z to low (assertion delay) 2 7 ns
6 PQI_TA# low to high (deassertion delay) 2 7 ns
7 PQI_TA# high to high-z 2 7 ns
8 Read data output valid delay (high-z to 0/1) 2 7 ns
9 Read data output invalid delay (0/1 to high-z) 2 7 ns
Notes
All signals are synchronous to PQI_CLK. Max values are for a 50 pF load and Min
values are for a 2 pF load.
7 Timing Specifications
30 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PQI_TS#
PQI_CS#
PQI_A[0:31]
PQI_TSIZ[0:1]
1
1
2
2
12
12
Write O perati on
Read Operation
PQI_RD/WR#
PQI_D[0:31]
43
PQI_D[0:31]
PQI_RD/WR#
9
8
1
1
2
2
PQI_TA#
567
PQI_CLK
Figure 8 Read/Write Timing (PQI bus)
Timing Specifications
7955 - Security Accelerator - Data Sheet, DS-0114-01 31
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7.5 EEPROM
The EEPROM interface signal timing is derived from the PCI_CLK divided by 256.
Table 26 EEPROM Timing
Number Symbol Min Max Units
1 Fsk 256 tPCI_CLK ns
2 Tskh 128 tPCI_CLK – 5 ns
3 Tskl 128 tPCI_CLK – 5 ns
4 Tsks 128 tPCI_CLK – 5 ns
5 Tcs 256 tPCI_CLK – 5 ns
6 Tcss 128 tPCI_CLK – 10 ns
7 Tdh 0 ns
8 Tdis 128 tPCI_CLK – 10 ns
9 Tcsh 0 ns
10 Tdih 127 tPCI_CLK – 10 ns
11 Tpd0 127 tPCI_CLK – 10 ns
12 Tpd1 127 tPCI_CLK – 10 ns
Synchronous Data Timing
VIH
EEPROM_CS
EEPROM_SK
EEPROM_DO
EEPROM_DI
VIL
VIH
VIL
VIH
VIL
VOH
VOL
4
810
7
7
12
9
1
62 3
11
5
Figure 9 EEPROM Timing
7 Timing Specifications
32 7955- Security Accelerator - Data Sheet, DS-0114-01
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7955 - Security Accelerator - Data Sheet, DS-0114-01 33
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8 DC Specifications
8.1 Absolute Maximum Ratings
Table 27 Absolute Maximum Ratings
DC Supply Voltage (VDDS, VDDS2, VDDS12) –0.3V to +5.0V
DC Supply Voltage (VDDC, AVD) -0.3V to +3.3V
DC Input Voltage (Signals) –0.3V to VDDS+0.3
Storage Temperature –40°C to +125°C
Delay between asserting +1.5V (VDDC & AVD) and +3.3V (VDDS,
VDDS2, VDDS12) power supplies
0-500ms
8.2 Power Sequencing
The +1.5V and +3.3V power supply voltages must be asserted at the same time. Otherwise, the
device may be damaged by reverse currents. To prevent damage to the device, these voltages must
be enabled within the time given in the absolute maximum ratings. The power supply should be
designed to assert power within the time limits given under the recommended operating conditions.
Warning
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
8 DC Specifications
34 7955- Security Accelerator - Data Sheet, DS-0114-01
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8.3 Recommended Operating Conditions
Table 28 Recommended Operating Conditions
DC Supply Voltage (VDDS, VDDS2, VDDS12) +3.0V to +3.6V
DC Supply Voltage (VDDC, AVD) +1.425V to +1.575V
Delay between asserting +1.5V (VDDC & AVD) and +3.3V
(VDDS, VDDS2, VDDS12) power supplies
0 – 100ms
Operating Temperature 0°C to +70°C
8.4 DC Characteristics
Table 29 DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
VIL Low level input voltage (I, PI, I/O-O4) 0.8 V
I-PCI, I/O-PCI, I-PQ, I/O-PQ -0.5 1.17
Clock Input (CI) 0.72
VIH High level input voltage (I, PI, I/O-O4) 2.0 V
I-PCI, I/O-PCI, I-PQ, I/O-PQ 1.425 4.1
Clock Input (CI) 2.4
IIL Low level input current (I, I/O-O4) VIN = VSS
VDDS = 3.6V
-10 10 µA
With pull-up (PI) 10 200
I-PCI, I/O-PCI, I-PQ, I/O-PQ -10 10
IIH High level input current (I, I/O-O4) VIN = VDDS
VDDS = 3.6V
-10 10 µA
I-PCI, I/O-PCI, I-PQ, I/O-PQ -10 10
VOL Low level output voltage VDDS = 3.0V V
(O4) IOL = 4mA 0.4
I/O-PCI, TS-PCI, I/O-PQ, TS-PQ 0.36
VOH High level output voltage VDDS = 3.0V V
(O4) IOH = -4mA 2.4
I/O-PCI, TS-PCI, I/O-PQ, TS-PQ 2.7
IOZ High impedance output leakage
current
VO = VSS or
VDDS
VDDS = 3.6V
-10 µA
IDD Quiescent supply current 300 µA
CIN Input capacitance (I, PI) VDDS = 3.3V 2.4 pF
I-PCI, I/O-PCI, I-PQ, I/O-PQ 10
PCI_IDSEL 8
PCI_CLK, PQI_CLK 5 12
COUT Output capacitance (TS-O4) VDDS = 3.3V 5.6 pF
CI/O I/O capacitance (I/O-O4) VDDS = 3.3V 6.6 pF
DC Specifications
7955 - Security Accelerator - Data Sheet, DS-0114-01 35
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. . . . . .
Symbol Parameter Conditions Min Typ Max Units
IDD core Active Supply Current (VDDC) VDDC=1.575V 166 178 mA
IDD I/O Active Supply Current (VDDS) VDDS = 3.6V 115 165 mA
IAVD PLL analog power supply current AVD =
1.575V
6 mA
Notes:
Host Bus pins are shared between 32-bit PowerQuicc I and the 64-bit PCI.
Buffer Type: I=input, I/O-O4=Bi-directional with 4mA output driver, CI=Clock input, PI-Input
with pull-up resistor, TS-O4=Tri-State with 4mA output driver, I-PCI=PCI input, I/O-PCI=PCI
Input/Output, TS-PCI=PCI Tri-State output, I-PQ=PQ input, I/O-PQ=PQ Input/Output, TS-
PQ=PQ Tri-State output
8 DC Specifications
36 7955- Security Accelerator - Data Sheet, DS-0114-01
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7955 - Security Accelerator - Data Sheet, DS-0114-01 37
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9 Thermal Specifications
Table 30 Thermal Specifications
Parameter Min Typ Max Units
Junction Temperature (Tj) 0 100* 125* ºC
Ambient Operating Temperature (Ta) 0 70 ºC
Storage Temperature -40 125 ºC
Power Dissipation (P) @ VDDS = 3.6V 0.638 0.885 W
* For proper operation, the maximum junction temperature must not exceed 125 ºC. However, the
life of the part may be shortened if the average operating junction temperature is allowed to exceed
100 ºC.
Table 31 Thermal Resistance
Parameter Max Units
Thermal Resistance, Junction to Ambient (θja) 44.4 ºC/W
Thermal Resistance, Junction to Ambient (θjma at 1 m/s) 38.5 ºC/W
Internal Thermal Resistance (θjc) 12 ºC/W
Temperature Correlation, Center Top of Pkg to Junction (Ψjt) TBD ºC/W
9.1 Heat Sink Requirements
Refer to the 7954/7955/7956 Thermal Characteristics Application Note for additional information to
help determine the heat sink requirements.
9.2 Junction Temperature Specifications
The maximum operating junction temperature is 125 ºC. Above this temperature, operating the part
is not guaranteed. For maximum operating life the junction temperature in the device should be no
more than 100 ºC. Worst case device dissipation should be used when performing thermal
calculations. Refer to Thermal Management Applicati on Note, AN-0038 for additional information to
help determine application specific junction temperatures and heat sink requirements.
9 Thermal Specifications
38 7955- Security Accelerator - Data Sheet, DS-0114-01
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7955 - Security Accelerator - Data Sheet, DS-0114-01 39
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10 Pin List
10.1 PCI-Mode Pin List
Table 32 PCI-Mode Pin List (Numeric)
Pin Name Pin Name Pin Name Pin Name
1 TEST_EN 37 PCI_AD21 73 VSS2 109 PCI_AD51
2 JTDO 38 PCI_AD20 74 PCI_AD5 110 PCI_AD50
3 JTCK 39 PCI_AD19 75 PCI_AD4 111 PCI_AD49
4 JTRST# 40 VDDS 76 VSS 112 PCI_AD48
5 EEPROM_EN 41 PCI_AD18 77 PCI_AD3 113 VSS2
6 VDDS2 42 PCI_AD17 78 VDDS 114 VDDS
7 EEPROM_DO 43 PCI_AD16 79 VDDS2 115 PCI_AD47
8 EEPROM_CS 44 VSS 80 PCI_AD2 116 VSS
9 EEPROM_SK 45 PCI_CBE#2 81 PCI_AD1 117 PCI_AD46
10 EEPROM_DI 46 PCI_FRAME# 82 PCI_AD0 118 PCI_AD45
11 VSS2 47 PCI_IRDY# 83 PCI_ACK64# 119 PCI_AD44
12 VDDC 48 PCI_TRDY# 84 PCI_REQ64# 120 PCI_AD43
13 PCI_INTA# 49 PCI_DEVSEL# 85 PCI_CBE#7 121 PCI_AD42
14 PCI_RST# 50 PCI_STOP# 86 PCI_CBE#6 122 PCI_AD41
15 VDDS 51 VDDS 87 PCI_CBE#5 123 VDDC
16 PCI_CLK 52 PCI_PERR# 88 VSS 124 PCI_AD40
17 PCI_GNT# 53 VSS 89 PCI_CBE#4 125 VDDS2
18 VDDC 54 VSS2 90 VDDS12 126 VDDS
19 PCI_REQ# 55 VDDS2 91 PCI_PAR64 127 PCI_AD39
20 PCI_AD31 56 PCI_SERR# 92 VDDC 128 VSS
21 PCI_AD30 57 PCI_PAR 93 PCI_AD63 129 PCI_AD38
22 PCI_AD29 58 VDDC 94 VSS2 130 PCI_AD37
23 VSS 59 PCI_CBE#1 95 PCI_AD62 131 PCI_AD36
24 PCI_AD28 60 PCI_AD15 96 PCI_AD61 132 PCI_AD35
25 PCI_AD27 61 PCI_AD14 97 PCI_AD60 133 PCI_AD34
26 PCI_AD26 62 PCI_AD13 98 PCI_AD59 134 PCI_AD33
27 VDDS 63 PCI_AD12 99 PCI_AD58 135 PCI_AD32
28 PCI_AD25 64 VSS 100 PCI_AD57 136 VSS2
29 PCI_AD24 65 PCI_AD11 101 VDDS2 137 RESERVED_nc
30 VDDS2 66 VDDS 102 VSS 138 VDDS
31 PCI_CBE#3 67 PCI_AD10 103 PCI_AD56 139 AVS
32 PCI_IDSEL 68 PCI_AD9 104 VDDS 140 AVD
33 PCI_AD23 69 PCI_AD8 105 PCI_AD55 141 VSS
34 VSS2 70 PCI_CBE#0 106 PCI_AD54 142 JTMS
35 VDDC 71 PCI_AD7 107 PCI_AD53 143 JTDI
36 PCI_AD22 72 PCI_AD6 108 PCI_AD52 144 PLL_REF
10 Pin List
40 7955- Security Accelerator - Data Sheet, DS-0114-01
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10.2 PCI-Mode Pin List (by Category)
Table 33 PCI-Mode Pin List (Signal Category)
Pin Name Pin Name Pin Name Pin Name
140 AVD 33 PCI_AD23 98 PCI_AD59 92 VDDC
139 AVS 29 PCI_AD24 97 PCI_AD60 123 VDDC
8 EEPROM_CS 28 PCI_AD25 96 PCI_AD61 15 VDDS
10 EEPROM_DI 26 PCI_AD26 95 PCI_AD62 27 VDDS
7 EEPROM_DO 25 PCI_AD27 93 PCI_AD63 40 VDDS
5 EEPROM_EN 24 PCI_AD28 70 PCI_CBE#0 51 VDDS
9 EEPROM_SK 22 PCI_AD29 59 PCI_CBE#1 66 VDDS
3 JTCK 21 PCI_AD30 45 PCI_CBE#2 78 VDDS
143 JTDI 20 PCI_AD31 31 PCI_CBE#3 104 VDDS
2 JTDO 135 PCI_AD32 89 PCI_CBE#4 114 VDDS
142 JTMS 134 PCI_AD33 87 PCI_CBE#5 126 VDDS
4 JTRST# 133 PCI_AD34 86 PCI_CBE#6 138 VDDS
83 PCI_ACK64# 132 PCI_AD35 85 PCI_CBE#7 90 VDDS12
82 PCI_AD0 131 PCI_AD36 16 PCI_CLK 6 VDDS2
81 PCI_AD1 130 PCI_AD37 49 PCI_DEVSEL# 30 VDDS2
80 PCI_AD2 129 PCI_AD38 46 PCI_FRAME# 55 VDDS2
77 PCI_AD3 127 PCI_AD39 17 PCI_GNT# 79 VDDS2
75 PCI_AD4 124 PCI_AD40 32 PCI_IDSEL 101 VDDS2
74 PCI_AD5 122 PCI_AD41 13 PCI_INTA# 125 VDDS2
72 PCI_AD6 121 PCI_AD42 47 PCI_IRDY# 23 VSS
71 PCI_AD7 120 PCI_AD43 57 PCI_PAR 44 VSS
69 PCI_AD8 119 PCI_AD44 91 PCI_PAR64 53 VSS
68 PCI_AD9 118 PCI_AD45 52 PCI_PERR# 64 VSS
67 PCI_AD10 117 PCI_AD46 19 PCI_REQ# 76 VSS
65 PCI_AD11 115 PCI_AD47 84 PCI_REQ64# 88 VSS
63 PCI_AD12 112 PCI_AD48 14 PCI_RST# 102 VSS
62 PCI_AD13 111 PCI_AD49 56 PCI_SERR# 116 VSS
61 PCI_AD14 110 PCI_AD50 50 PCI_STOP# 128 VSS
60 PCI_AD15 109 PCI_AD51 48 PCI_TRDY# 141 VSS
43 PCI_AD16 108 PCI_AD52 144 PLL_REF 11 VSS2
42 PCI_AD17 107 PCI_AD53 137 RESERVED_NC 34 VSS2
41 PCI_AD18 106 PCI_AD54 1 TEST_EN 54 VSS2
39 PCI_AD19 105 PCI_AD55 12 VDDC 73 VSS2
38 PCI_AD20 103 PCI_AD56 18 VDDC 94 VSS2
37 PCI_AD21 100 PCI_AD57 35 VDDC 113 VSS2
36 PCI_AD22 99 PCI_AD58 58 VDDC 136 VSS2
Pin List
7955 - Security Accelerator - Data Sheet, DS-0114-01 41
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10.3 PCI Mode Pinout
TEST_EN
JTDO
JTCK
EEPROM_EN
VDDS2
EEPROM_DO
EEPROM_CS
EEPROM_SK
EEPROM_DI
VSS2
VDDC
PCI_RST#
VDDS
PCI_CLK
PCI_GNT#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD26
VDDS2
PCI_CBE#3
PCI_IDSEL
PCI_AD25
PCI_AD17
PCI_AD16
VSS
VSS2
VDDS2
PCI_SERR#
PCI_PAR
VSS
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
VDDS
PCI_PERR#
PCI_CBE#1
PCI_AD43
PCI_AD42
PCI_AD41
VDDC
PCI_AD40
VDDS
VSS
PCI_AD38
PCI_AD37
PCI_AD36
PCI_AD35
PCI_AD34
PCI_AD33
RESERVED_NC
AVS
AVD
VSS
JTMS
JTDI
37
38
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
VDDS
PCI_AD10
PCI_AD9
PCI_AD8
PCI_CBE#0
PCI_AD7
PCI_AD51
PCI_AD50
PCI_AD49
PCI_AD48
VSS2
PCI_AD23
VSS2
VDDC
PCI_AD22
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VDDC
PCI_REQ#
VSS
PCI_AD27
VDDS
PCI_AD24
PCI_AD15
VDDS
PCI_AD47
VSS
PCI_AD46
PCI_AD45
PCI_AD44
VSS2
VDDS
VDDS2
PCI_AD39
PCI_AD32
PLL_REF
PCI_AD6
VSS
VDDC
PCI_AD21
PCI_AD20
PCI_AD19
VDDS
PCI_AD18
PCI_CBE#2
PCI_INTA#
JTRST#
PCI_REQ64#
PCI_CBE#7
PCI_CBE#6
PCI_CBE#5
VSS
PCI_CBE#4
PCI_PAR64
PCI_AD63
VSS2
PCI_AD62
PCI_AD61
PCI_AD59
PCI_AD58
PCI_AD57
VDDS2
VSS
PCI_AD56
VDDS
PCI_AD55
PCI_AD54
PCI_AD53
VDDS
VSS2
PCI_AD5
PCI_AD4
VSS
PCI_AD3
PCI_ACK64#
VDDS2
PCI_AD2
PCI_AD1
PCI_AD0
VDDS12
PCI_AD60
PCI_AD52
VDDC
Figure 10 PCI Mode Pinout Drawing
10 Pin List
42 7955- Security Accelerator - Data Sheet, DS-0114-01
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10.3.1 PQI-Mode Pin List
Table 34 PQI-Mode Pin List (Numeric)
Pin Name Pin Name Pin Name Pin Name
1 TEST_EN 37 PQI_A10 73 VSS2 109 PQI_D12
2 JTDO 38 PQI_A11 74 PQI_A26 110 PQI_D13
3 JTCK 39 PQI_A12 75 PQI_A27 111 PQI_D14
4 JTRST# 40 VDDS 76 VSS 112 PQI_D15
5 EEPROM_EN 41 PQI_A13 77 PQI_A28 113 VSS2
6 VDDS2 42 PQI_A14 78 VDDS 114 VDDS
7 EEPROM_DO 43 PQI_A15 79 VDDS2 115 PQI_D16
8 EEPROM_CS 44 VSS 80 PQI_A29 116 VSS
9 EEPROM_SK 45 PQI_TSIZ0 81 PQI_A30 117 PQI_D17
10 EEPROM_DI 46 RESERVED_VDD 82 PQI_A31 118 PQI_D18
11 VSS2 47 PQI_BURST# 83 RESERVED_VSS 119 PQI_D19
12 VDDC 48 RESERVED_VSS 84 RESERVED_VSS 120 PQI_D20
13 PQI_INT# 49 RESERVED_VSS 85 RESERVED_VSS 121 PQI_D21
14 PQI_RST# 50 RESERVED_VSS 86 RESERVED_VSS 122 PQI_D22
15 VDDS 51 VDDS 87 RESERVED_VSS 123 VDDC
16 PQI_CLK 52 PQI_TA# 88 VSS 124 PQI_D23
17 PQI_TS# 53 VSS 89 PQI_RW# 125 VDDS2
18 VDDC 54 VSS2 90 VDDS12 126 VDDS
19 RESERVED_NC 55 VDDS2 91 RESERVED_VSS 127 PQI_D24
20 PQI_A0 56 PQI_TEA# 92 VDDC 128 VSS
21 PQI_A1 57 RESERVED_VSS 93 PQI_D0 129 PQI_D25
22 PQI_A2 58 VDDC 94 VSS2 130 PQI_D26
23 VSS 59 RESERVED_VSS 95 PQI_D1 131 PQI_D27
24 PQI_A3 60 PQI_A16 96 PQI_D2 132 PQI_D28
25 PQI_A4 61 PQI_A17 97 PQI_D3 133 PQI_D29
26 PQI_A5 62 PQI_A18 98 PQI_D4 134 PQI_D30
27 VDDS 63 PQI_A19 99 PQI_D5 135 PQI_D31
28 PQI_A6 64 VSS 100 PQI_D6 136 VSS2
29 PQI_A7 65 PQI_A20 101 VDDS2 137 RESERVED_NC
30 VDDS2 66 VDDS 102 VSS 138 VDDS
31 PQI_TSIZ1 67 PQI_A21 103 PQI_D7 139 AVS
32 PQI_CS# 68 PQI_A22 104 VDDS 140 AVD
33 PQI_A8 69 PQI_A23 105 PQI_D8 141 VSS
34 VSS2 70 RESERVED_VSS 106 PQI_D9 142 JTMS
35 VDDC 71 PQI_A24 107 PQI_D10 143 JTDI
36 PQI_A9 72 PQI_A25 108 PQI_D11 144 PLL_REF
Pin List
7955 - Security Accelerator - Data Sheet, DS-0114-01 43
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10.3.2 PQI Mode Pin List (by Category)
Table 35 PQI-Mode Pin List (Signal Category)
Pin Name Pin Name Pin Name Pin Name
140 AVD 69 PQI_A23 127 PQI_D24 92 VDDC
139 AVS 71 PQI_A24 129 PQI_D25 123 VDDC
8 EEPROM_CS 72 PQI_A25 130 PQI_D26 15 VDDS
10 EEPROM_DI 74 PQI_A26 131 PQI_D27 27 VDDS
7 EEPROM_DO 75 PQI_A27 132 PQI_D28 40 VDDS
5 EEPROM_EN 77 PQI_A28 133 PQI_D29 51 VDDS
9 EEPROM_SK 80 PQI_A29 134 PQI_D30 66 VDDS
3 JTCK 81 PQI_A30 135 PQI_D31 78 VDDS
143 JTDI 82 PQI_A31 13 PQI_INT# 104 VDDS
2 JTDO 47 PQI_burst# 14 PQI_RST# 114 VDDS
142 JTMS 16 PQI_CLK 89 PQI_rw# 126 VDDS
4 JTRST# 32 PQI_CS# 52 PQI_TA# 138 VDDS
144 PLL_REF 93 PQI_D0 56 PQI_tea# 90 VDDS12
20 PQI_A0 95 PQI_D1 17 PQI_Ts# 6 VDDS2
21 PQI_A1 96 PQI_D2 45 PQI_tsiz0 30 VDDS2
22 PQI_A2 97 PQI_D3 31 PQI_tsiz1 55 VDDS2
24 PQI_A3 98 PQI_D4 19 RESERVED_NC 79 VDDS2
25 PQI_A4 99 PQI_D5 46 RESERVED_VDD 101 VDDS2
26 PQI_A5 100 PQI_D6 85 RESERVED_VSS 125 VDDS2
28 PQI_A6 103 PQI_D7 86 RESERVED_VSS 23 VSS
29 PQI_A7 105 PQI_D8 87 RESERVED_VSS 44 VSS
33 PQI_A8 106 PQI_D9 59 RESERVED_VSS 53 VSS
36 PQI_A9 107 PQI_D10 70 RESERVED_VSS 64 VSS
37 PQI_A10 108 PQI_D11 48 RESERVED_VSS 76 VSS
38 PQI_A11 109 PQI_D12 49 RESERVED_VSS 88 VSS
39 PQI_A12 110 PQI_D13 50 RESERVED_VSS 102 VSS
41 PQI_A13 111 PQI_D14 57 RESERVED_VSS 116 VSS
42 PQI_A14 112 PQI_D15 83 RESERVED_VSS 128 VSS
43 PQI_A15 115 PQI_D16 84 RESERVED_VSS 141 VSS
60 PQI_A16 117 PQI_D17 91 RESERVED_VSS 11 VSS2
61 PQI_A17 118 PQI_D18 137 RESERVED_NC 34 VSS2
62 PQI_A18 119 PQI_D19 1 TEST_EN 54 VSS2
63 PQI_A19 120 PQI_D20 12 VDDC 73 VSS2
65 PQI_A20 121 PQI_D21 18 VDDC 94 VSS2
67 PQI_A21 122 PQI_D22 35 VDDC 113 VSS2
68 PQI_A22 124 PQI_D23 58 VDDC 136 VSS2
10 Pin List
44 7955- Security Accelerator - Data Sheet, DS-0114-01
. . . . . .
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10.4 PQI Mode Pinout
TEST_EN
JTDO
JTCK
EEPROM_EN
VDDS2
EEPROM_DO
EEPROM_CS
EEPROM_SK
EEPROM_DI
VSS2
VDDC
PQI_RST#
VDDS
PQI_CLK
PQI_TS#
PQI_A0
PQI_A1
PQI_A2
PQI_A3
PQI_A5
VDDS2
PQI_TSIZ1
PQI_CS#
PQI_A6
PQI_A14
PQI_A15
VSS
VSS2
VDDS2
PQI_TEA#
RESERVED_VSS
VSS
RESERVED_VDD
PQI_BURST#
RESERVED_VSS
RESERVED_VSS
RESERVED_VSS
VDDS
PQI_TA#
RESERVED_VSS
PQI_D20
PQI_D21
PQI_D22
VDDC
PQI_D23
VDDS
VSS
PQI_D25
PQI_D26
PQI_D27
PQI_D28
PQI_D29
PQI_D30
RESERVED_NC
AVS
AVD
VSS
JTMS
JTDI
37
38
PQI_A17
PQI_A18
PQI_A19
PQI_A20
VDDS
PQI_A21
PQI_A22
PQI_A23
RESERVED_VSS
PQI_A24
PQI_D12
PQI_D13
PQI_D14
PQI_D15
VSS2
PQI_A8
VSS2
VDDC
PQI_A9
108
107
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144
VDDC
RESERVED_NC
VSS
PQI_A4
VDDS
PQI_A7
PQI_A16
VDDS
PQI_D16
VSS
PQI_D17
PQI_D18
PQI_D19
VSS2
VDDS
VDDS2
PQI_D24
PQI_D31
PLL_REF
PQI_A25
VSS
VDDC
PQI_A10
PQI_A11
PQI_A12
VDDS
PQI_A13
PQI_TSIZ0
PQI_INT#
JTRST#
RESERVED_VSS
RESERVED_VSS
RESERVED_VSS
RESERVED_VSS
VSS
PQI_RW#
RESERVED_VSS
PQI_D0
VSS2
PQI_D1
PQI_D2
PQI_D4
PQI_D5
PQI_D6
VDDS2
VSS
PQI_D7
VDDS
PQI_D8
PQI_D9
PQI_D10
VDDS
VSS2
PQI_A26
PQI_A27
VSS
PQI_A28
RESERVED_VSS
VDDS2
PQI_A29
PQI_A30
PQI_A31
VDDS12
PQI_D3
PQI_D11
VDDC
Figure 11 PQI Mode Pinout Drawing
7955 - Security Accelerator - Data Sheet, DS-0114-01 45
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11 Physical Specifications
11.1 LQFP 144-pin Plastic Quad Flatpack
20.0±0.1
22.0±0.2
20.0±0.1
22.0±0.2
1.25
TYP
0.5 M
0.08
1.4±0.05
1.7 MAX
0.1±0.05
0~10°
0.22
0.08
0.145
+0.055
–0.04
5
All u nits in m illim e ters
0.45min,
0.75max
-0.04
+0.05
Figure 12 144 LQFP Package
11 Physical Specifications
46 7955- Security Accelerator - Data Sheet, DS-0114-01
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7955 - Security Accelerator - Data Sheet, DS-0114-01 47
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I Errata
Errata are design defects or errors. Errata may cause the product behavior to deviate from
published specifications.
I.1 Document Revision 01
None.
Errata
48 7955- Security Accelerator - Data Sheet, DS-0114-01
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7955 - Security Accelerator - Data Sheet, DS-0114-01 49
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II Specification Clarifications
Specification clarifications describe any new product specifications, changes to prior product
specifications, provide greater detail for a particular specification item, or further highlight a
specification’s impact to a complex design situation. This section outlines any specification
clarifications incorporated in each document revision.
II.1 Document Revision 01
None.
Specifi cation Clarifications
50 7955- Security Accelerator - Data Sheet, DS-0114-01
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7955 - Security Accelerator - Data Sheet, DS-0114-01 51
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III Document Changes/Revisions
Documentation changes include additions, deletions, and modifications made to this document. This
section identifies the changes made in each release of the document.
III.1 Document Revision 01
Update 1. Added PCI Mode and PQI Mode Pinout drawings.
Section 10.
Document Changes/Revisions
52 7955- Security Accelerator - Data Sheet, DS-0114-01
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