ASIX ELECTRONICS CORPORATION Frist Released Date : Dec/13/1999
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88190AL
PCMCIA Fast Ethernet MAC Controller
10/100BASE PCMCIA Fast Ethernet MAC Controller
Document No.: AX190A-13 / V1.3 / June. 27 ’00
Features
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Single chip PCMCIA bus 10/100Mbps Fast
Ethernet MAC Controller
• Embedded 8K * 16 bit SRAM
• NE2000 register level compatible instruction
• Compliant with 16 bit PC Card Standard - February
1995
• Support both 10Mbps and 100Mbps data rate
• Support both full-duplex or half-duplex operation
• Provides a MII port for both 10/100Mbps operation
• Provides SNI I/F for Home LAN PHY or 10M
transceiver option
• Support 128/256 bytes EEPROM (used for saving
CIS)
• Support automatic loading of Ethernet ID, CIS and
Adapter Configuration from EEPROM on power-on
initialization
• External and internal loop-back capability
• Support 8 General Purpose I/O ports
• 128-pin LQFP low profile package
• 20MHz to 25MHz Operation, Dual 5V and 3.3V
CMOS process with 5V I/O tolerance. Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are the
property of their respective holders.
Product description
The AX88190A Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet Controller
with embedded 8K*16 bit SRAM. The AX88190A contains a 16 bit PCMCIA interfaces to host CPU and compliant with
PC Card Standard – February 1995. The AX88190A implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88190A supports 10Mbps/100Mbps media-independent interface (MII)
and legacy pure 10Mbps SNI interface to simplify the design. Using Serial Network Interface (SNI) transceiver, Home
LAN PHY or 10BASE-2 BNC type media can be supported. The AX88190A is built in interface to connect
FAX/MODEM chipset with parallel bus interface.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
AX88190A
10/100
PHY/TxRx
MODEM
DAA
MAGNETIC
RJ45
RJ11
PCMCIA I/F
EEPROM
Home LAN PHY or
10M PHY/TxRx
MAGNETIC
RJ11 or BNC
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
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CONTENTS
1.0 INTRODUCTION...............................................................................................................................................5
1.1 GENERAL DESCRIPTION:.....................................................................................................................................5
1.2 AX88190A BLOCK DIAGRAM:............................................................................................................................5
1.3 AX88190A PIN CONNECTION DIAGRAM .............................................................................................................6
2.0 SIGNAL DESCRIPTION....................................................................................................................................7
2.1 PCMCIA BUS INTERFACE SIGNALS GROUP .........................................................................................................7
2.2 EEPROM SIGNALS GROUP.................................................................................................................................8
2.3 MII INTERFACE SIGNALS GROUP ..........................................................................................................................8
2.4 SNI INTERFACE PINS GROUP................................................................................................................................9
2.5 MODEM INTERFACE PINS GROUP ..........................................................................................................................9
2.6 GENERAL PURPOSE I/O PINS GROUP.....................................................................................................................9
2.7 MISCELLANEOUS PINS GROUP ............................................................................................................................10
2.8 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE.................................................................11
3.0 MEMORY AND I/O MAPPING ......................................................................................................................12
3.1 EEPROM MEMORY MAPPING ..........................................................................................................................12
3.2 ATTRIBUTE MEMORY MAPPING.........................................................................................................................12
3.3 I/O MAPPING....................................................................................................................................................13
3.4 SRAM MEMORY MAPPING...............................................................................................................................13
4.0 REGISTERS OPERATION..............................................................................................................................14
4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN............................................................................14
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)...............................................15
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)..........................................16
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write).......................................16
4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM.....................................................................17
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write).......................................17
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write)..................................18
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)...............................18
4.3 MAC CORE REGISTERS ....................................................................................................................................19
4.3.1 Command Register (CR) Offset 00H (Read/Write)....................................................................................21
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write) ...........................................................................21
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) ....................................................................................22
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)...........................................................................22
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write).....................................................................22
4.3.6 Transmit Status Register (TSR) Offset 04H (Read) ...................................................................................23
4.3.7 Receive Configuration (RCR) Offset 0CH (Write) ....................................................................................23
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)....................................................................................23
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)........................................................................................23
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)..................................................................24
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)..................................................................24
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) .................................................24
4.3.13 Test Register (TR) Offset 15H (Write).....................................................................................................24
4.3.14 General Purpose Input Register (GPI) Offset 18H (Read) ......................................................................24
4.3.15 General Purpose I/O Register (GPIO) Offset 1AH (Read/Write).............................................................25
5.0 PCMCIA DEVICE ACCESS FUNCTIONS....................................................................................................26
5.1 ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS..........................................................................................26
5.2 I/O ACCESS FUNCTION FUNCTIONS.....................................................................................................................26
AX88190A PCMCIA Fast Ethernet MAC Controller
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6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................27
6.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................27
6.2 GENERAL OPERATION CONDITIONS ...................................................................................................................27
6.3 DC CHARACTERISTICS......................................................................................................................................27
6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................28
6.4.1 XTAL / CLOCK.........................................................................................................................................28
6.4.2 Reset Timing.............................................................................................................................................28
6.4.3 Attribute Memory Read Timing.................................................................................................................29
6.4.4 Attribute Memory Write Timing ................................................................................................................30
6.4.5 I/O Read Timing .......................................................................................................................................31
6.4.6 I/O Write Timing.......................................................................................................................................32
6.4.7 MII Timing................................................................................................................................................33
6.4.8 SNI Timing................................................................................................................................................34
7.0 PACKAGE INFORMATION...........................................................................................................................35
APPENDIX A: APPLICATION NOTE.................................................................................................................36
A.1 USING CRYSTAL 25MHZ OR 20MHZ.................................................................................................................36
A.2 USING OSCILLATOR 25MHZ OR 20MHZ............................................................................................................36
A.3 USING 60MHZ OSCILLATOR/CRYSTAL..............................................................................................................36
A.4 DUAL POWER (5V AND 3.3V) APPLICATION.......................................................................................................37
A.5 SINGLE POWER (3.3V) APPLICATION .................................................................................................................37
A.6 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY .............................................................................38
APPENDIX B: AX88190 DESIGN CHANGES TO AX88190A ...........................................................................39
ERRATA OF AX88190A VERSION ED2..............................................................................................................40
DEMONSTRATION CIRCUIT : AX88190A + ETHERNET PHY + HOMEPNA 1M8 PHY ...........................41
REFERENCE BILL OF MATERIALS..................................................................................................................47
SPONSORS OF COMPONENTS...........................................................................................................................48
SPONSORS OF COMPONENTS (CHINESE)......................................................................................................49
AX88190A PCMCIA Fast Ethernet MAC Controller
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FIGURES
FIG - 1 AX88190A BLOCK DIAGRAM ...........................................................................................................................5
FIG - 2 AX88190A PIN CONNECTION DIAGRAM............................................................................................................6
TABLES
TAB - 1 PCMCIA BUS INTERFACE SIGNALS GROUP ........................................................................................................7
TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP........................................................................................................8
TAB - 3 MII INTERFACE SIGNALS GROUP........................................................................................................................8
TAB - 4 SERIAL NETWORK INTERFACE PINS GROUP ........................................................................................................9
TAB - 5 MODEM INTERFACE SIGNALS GROUP..................................................................................................................9
TAB - 6 GENERAL PURSOSE I/O PINS GROUP ................................................................................................................10
TAB - 7 MISCELLANEOUS PINS GROUP..........................................................................................................................10
TAB - 8 POWER ON CONFIGURATION SETUP TABLE......................................................................................................11
TAB - 9 EEPROM MEMORY MAPPING........................................................................................................................12
TAB - 10 ATTRIBUTE MEMORY MAPPING....................................................................................................................12
TAB - 11 I/O ADDRESS MAPPING................................................................................................................................13
TAB - 12 LOCAL MEMORY MAPPING...........................................................................................................................13
TAB - 13 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF LAN...............................................................14
TAB - 14 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF MODEM........................................................17
TAB - 15 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................19
TAB - 16 PAGE 1 OF MAC CORE REGISTERS MAPPING.................................................................................................20
AX88190A PCMCIA Fast Ethernet MAC Controller
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1.0 Introduction
1.1 General Description:
The AX88190A provides industrial standard NE2000 registers level compatable instruction set. Various drivers
are easy acquired, maintenance and usage with no pain and tears
The AX88190A Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet
Controller with embedded 8K*16 bit SRAM. The AX88190A contains a 16 bit PCMCIA interfaces to host CPU
and compliant with PC Card Standard – February 1995. The AX88190A implements both 10Mbps and
100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88190A support
10Mbps/100Mbps media-independent interface (MII) and legacy pure 10Mbps SNI interface to simplify the
design. Using Serial Network Interface (SNI) transceiver, Home LAN PHY or 10BASE-2 BNC type media can be
supported. The AX88190A is built in interface to connect FAX/MODEM chipset with parallel bus interface.
The main difference between AX88190A and AX88190 are : 1) Replace memory I/F with SNI I/F. 2) Fix OE#
signal synchronous problem 3) Fix interrupt status can’t always clean up problem of AX88190. 4) Add 8 general
Purpose I/O ports. 5) Change MPD_SET (pin 74 -> pin 68) and PPD_SET (pin 76 -> pin 70) power on setup
pins location.
AX88190A use 128-pin LQFP low profile package, typical 25MHz operation, dual 5V and 3.3V CMOS process
with 5V I/O tolerance or pure 3.3V operation.
1.2 AX88190A Block Diagram:
Fig - 1 AX88190A Block Diagram
MAC
Core
8K* 16 SRAM
and Memory Arbiter
Remote
DMA
FIFOs
NE2000/GPIO
Registers
PCMCIA Interface
STA
SEEPROM
LOADER I/F
SD[15:0]
SA[9:0]
Ctl BUS
MII I/F
SMDC
EECS
EECK
EEDI
EEDO
MODEM
I/F
SNI I/F
GPI/O
AX88190A PCMCIA Fast Ethernet MAC Controller
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1.3 AX88190A Pin Connection Diagram
The AX88190A is housed in the 128-pin plastic light quad flat pack. See Fig - 2 AX88190A Pin
Connection Diagram.
Fig - 2 AX88190A Pin Connection Diagram
MPWDN
123
118
122
78
70
54
41
32
24
12
8
LVDD
117
75
57
42
26
31
21
SA[1]
MRESET#
VSS
MINT
107
105
66
65
63
60
25
16
13
3
7
VSS
MRDY
LCLK/XTALIN
128
115
112
61
33
111
43
19
15
4
109
106
77
62
11
6
71
49
17
LVDD
68
58
56
55
45
23
VSS
53
116
113
59
36
34
1
VSS
124
108
HVDD
PPWDN
MAUDIO
MDCS#
28
22
9
HVDD
LVDD
VSS
126
119
110
121
79
74
80
72
46
29
52
10
MRIN#
67
44
39
27
51
5
127
125
120
114
73
69
38
48
76
47
35
30
20
2
VSS
IOIS16#
VSS
40
37
50
18
14
AX88190A
PCMCIA
10/100BASE MAC
CONTROLLER
103
104
82
91
81
86
93
94
84
87
95
96
90
88
92
85
89
83
98
97
99
100
102
101
TX_EN
TX_CLK
VSS
MDC
MDIO
RXD[3]
RXD[2]
RXD[1]
RXD[0]
LVDD
RX_CLK
CRS
COL
RX_DV
RX_ER
SD[0]
SD[1]
SD[2]
SD[3]
SA[0]
SA[3]
SA[2]
SA[5]
SA[4]
SA[6]
SA[7]
SA[9]
SA[8]
IREQ#
WE#
IORD#
IOWR#
OE#
SD[15]
SD[14]
SD[13]
SD[12]
SD[11]
SD[10]
SD[9]
SD[8]
SD[6]
SD[4]
SD[5]
SD[7]
WAIT#
RESET
INPACK#
CE2#
CE1#
TXD[0]
TXD[1]
TXD[2]
TXD[3]
XTALOUT
EEDI
EEDO
EECK
EECS
STSCHG#
SPKR#
REG#
VSS
VSS
64
CLKO
SCRS
SRXD
SRXC
SLINK#
STXE
STXD
STXC
SCOL
VSS
HVDD
TEST
HVDD
LVDD
LVDD
VSS
VSS
GPIO3
GPIO2
GPIO1#
GPIO0#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CLK_DIV3#
EEPROM_SIZE
GPI3
GPI2
GPI1
GPI0
AX88190A PCMCIA Fast Ethernet MAC Controller
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2.0 Signal Description
The following terms describe the AX88190A pin-out:
All pin names with the “#” suffix are asserted low.
The following abbreviations are used in following Tables.
IInput PU Pull Up
OOutput PD Pull Down
I/O Input/Output PPower Pin
OD Open Drain
2.1 PCMCIA Bus Interface Signals Group
SIGNAL TYPE PIN NO. DESCRIPTION
SA[9:0] I10 – 1 System Address : Signals SA[9:0] are address bus input lines which
enable direct address of up to 64K memory and I/O spaces on card.
SD[15:0] I/O 20 – 23,
25 – 38,
30 – 33,
35 – 38
System Data Bus : Signals SD[15:0] constitute the bi-directional data
bus.
IREQ# O12 Interrupt Request : IREQ# is asserted to indicate the host system that
the PC Card device requires host software service.
WAIT# O125 Wait : This signal is set low to insert wait states during Remote DMA
transfer.
REG# I123 Attribute Memory and I/O Space Select : When the REG# signal is
asserted, access is limited to Attribute Memory and to the I/O space.
IORD# I15 I/O Read : The host asserts IORD# to read data from AX88190A I/O
space.
IOWR# I14 I/O Write : The host asserts IOWR# to write data into AX88190A I/O
space.
OE# I16 Output Enable : The OE# line is used to gate Memory Read data from
memory on PC Card
WE# I13 Write Enable : The WE# signal is used for strobing Memory Write
data into the memory on PC Card.
IOIS16# O120 I/O is 16 Bit Port : The IOIS16# is asserted when the address at the
socket corresponds to an I/O address to which the card responds, and
the I/O port addressed is capable of 16-bit access.
INPACK# O124 Input Port Acknowledge : The signal is asserted when the AX88190A
is selected and can respond to and I/O read cycle at the address on the
address bus.
CE1#-CE2#I18, 17 Card Enable : The CE1# enables even numbered address bytes and
CE2# enables odd numbered address bytes
BVD1_STSCHG# O121 Battery Voltage Detect 1 / Status Change
BVD2_SPKR# O122 Battery Voltage Detect 2 / Audio speaker out
Tab - 1 PCMCIA bus interface signals group
AX88190A PCMCIA Fast Ethernet MAC Controller
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2.2 EEPROM Signals Group
SIGNAL TYPE PIN NO. DESCRIPTION
EECS O106 EEPROM Chip Select : EEPROM chip select signal.
EECK O107 EEPROM Clock : Signal connected to EEPROM clock pin.
EEDI O108 EEPROM Data In : Signal connected to EEPROM data input pin.
EEDO I/PU 109 EEPROM Data Out : Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL TYPE PIN NO. DESCRIPTION
RXD[3:0] I90 – 87 Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
CRS I85 Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
RX_DV I83 Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
RX_ER I82 Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
RX_CLK I86 Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
COL I84 Collision : this signal is driven by PHY when collision is detected.
TX_EN O95 Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
TXD[3:0] O99 – 96 Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
TX_CLK I94 Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
MDC O92 Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
MDIO I/O/PU 91 Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
Tab - 3 MII interface signals group
AX88190A PCMCIA Fast Ethernet MAC Controller
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2.4 SNI Interface pins group
SIGNAL TYPE PIN NO. DESCRIPTION
STXC I66 Transmit Clock : this signal is driven by PHY with 20MHz clock.
STXD O68 Transmit Data : STXD is transition synchronously with respect to the
rising edge of STXC. For each STXC period in which STXE is
asserted, STXD is accepted for transmission by the PHY.
STXE O70 Transmit Enable : STXE is transition synchronously with respect to
the rising edge of STXC. STXE indicates that the port is presenting
data on STXD for transmission.
SCOL I76 Collision : this signal is driven by PHY when collision is detected.
SRXC I78 Receive Clock : SRXC is driven by PHY for received data
synchronization.
SRXD I79 Receive Data : SRXD is driven by the PHY synchronously with respect
to SRXC.
SCRS I80 Carrier Sense : Asynchronous signal SCRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
SLINK# I/PU 74 Link indicator : Active low indicate the SNI interface is link to
network. When SNI is not used must keep the pin no connection or
pull high the signal.
Tab - 4 Serial Network Interface pins group
2.5 Modem interface pins group
Signal Name Type Pin No. Description
MRDY I/PU 118 Modem Ready : MRDY low indicates that modem is initializing the
modem after reset signal asserted or the modem is at SLEEP/STOP
mode.
MRESET#O117 Modem Reset :This signal asserts low to reset the modem chipset.
MDCS#O111 Modem Chip Select : This signal connected to modem chip select pin.
MPWDN O116 Modem Power Down : Rockwell modem chipset, this signal asserts
low to let modem chipset into power down mode. AT&T modem
chipset, this signal asserts high to let modem chipset into power down
mode.
MINT I/PD 112 Modem Interrupt : This signal driven by modem chipset to active
interrupt.
MRIN# I/PU 115 Ring Input :This signal is driven by DAA’s ring detect circuit. When
a telephone ringing signal is being received.
MAUDIO I/PD 113 Modem Audio : This signal is passed to PCMCIA interface via SPKR.
Tab - 5 Modem interface signals group
2.6 General Purpose I/O pins group
Signal Name Type Pin No. Description
GPI[3] I57 Read register offset 18h bit 3 value reflects this input value.
GPI[2] I58 Read register offset 18h bit 2 value reflects this input value.
GPI[1] I60 Read register offset 18h bit 1 value reflects this input value.
GPI[0] I61 Read register offset 18h bit 0 value reflects this input value.
AX88190A PCMCIA Fast Ethernet MAC Controller
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GPIO3# I/O 41 Default “1”. The pin reflects register offset 1Ah bit 3 inverted value.
GPIO2 I/O 42 Default “0”. The pin reflects register offset 1Ah bit 2 value.
GPIO1# I/O 43 Default “1”. The pin reflects register offset 1Ah bit 1 inverted value.
GPIO0# I/O 45 Default “1”. The pin reflects register offset 1Ah bit 0 inverted value.
Tab - 6 General Pursose I/O pins group
2.7 Miscellaneous pins group
SIGNAL TYPE PIN NO. DESCRIPTION
LCLK/XTALIN I103 CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40%-60%
duty cycle. ( See application note also )
Crystal Oscillator Input : Typical a 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT.
XTALOUT O104 Crystal Oscillator Output : Typical a 25Mhz crystal, +/- 25 ppm can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
CLKO O101 Clock Output : This clock is source from LCLK/XTALIN.
CLK_DIV3# I/PU 67 Clock Devide 3 Enable : Active low to enable the devided 3 circuit.
That internally devides LCLK/XTALIN input frequeny by 3 and then
feed into internal circuit for system clock used.
Default value set to logic high, this function is disabled.
PPWDN O114 Phy Power Down : This pin connects to PHY chip power down mode
control input.
RESET I/PD 127 Reset
Reset is active high then place AX88190A into reset mode
immediately. During Falling edge the AX88190A loads the EEPROM
data.
TEST# I/PU 77 Test Pin : Active LOW
The pin is just for test mode setting purpose only. Must be pull high
when normal operation.
EEPROM SIZE I/PU 73 EEPROM SIZE = 0 : 93C46 128 byte type EEPROM is used.
EEPROM SIZE = 1 : 93C56 256 byte type EEPROM is used.
NC N/A 46–48, 50–
53, 55-56, No Connection : for manufacturing test only.
LVDD P44, 54,
100, 110,
126, 128
Power Supply : +3.3V DC.
HVDD P19, 29, 64,
75 Power Supply : +5V DC.
Note : for pure 3.3V single power solution, all the HVDD pin can
connect to +3.3V. Care should be taken that HVDD input power must
be greater or equal ( > = ) than LVDD.
VSS P11, 24, 34,
39, 40, 49,
59, 69, 81,
93, 102, 105,
119
Power Supply : +0V DC or Ground Power.
Tab - 7 Miscellaneous pins group
AX88190A PCMCIA Fast Ethernet MAC Controller
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2.8 Power on configuration setup signals cross reference table
Signal Name Share with Description
MPD_SET STXD MPD_SET = 0 : MPWDN pin active high.
MPD_SET = 1 : MPWDN pin active low.
PPD_SET STXE PPD_SET = 0 : PPWDN pin active high.
PPD_SET = 1 : PPWDN pin active low.
All of the above signals are pull-up for default values.
Tab - 8 Power on Configuration Setup Table
AX88190A PCMCIA Fast Ethernet MAC Controller
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3.0 Memory and I/O Mapping
There are four memory or I/O mapping used in AX88190A.
1. EEPROM Memory Mapping
2. Attribute Memory Mapping
3. I/O Mapping
4. Local Memory Mapping
3.1 EEPROM Memory Mapping
EEPROM OFFSET HIGH BYTE LOW BYTE
00H RESERVED WORD COUNT
01H CFH CFL
02H NODE-ID1 NODE ID 0
03H NODE ID 3 NODE ID 2
04H NODE ID 5 NODE ID 4
05H CHECKSUM RESERVED
06H – 10H RESERVED RESERVED
10H – FFH CIS CIS
Tab - 9 EEPROM Memory Mapping
Note : bit 3 register of LCOR in AX88190 is replaced by bit 0 of CFL in AX88190A
Bit 0 of CFL : Enable Power Down mode
this bit is set to 1, the LAN will go into power down mode. At power down mode AX88190A will disable MAC
transmitting and receiving operation. But the host interface will not be affected.
3.2 Attribute Memory Mapping
ATTRIBUTE MEMORY
OFFSET CONTENTS
0000H
03BFH CIS
03C0H LCOR
03C2H LCCSR
03C4H -
03C6H -
03CAH LIOBASE0
03CCH LIOBASE1
03CEH
03DFH RESERVED
03E0H MCOR
03E2H MCCSR
03E4H -
03E6H -
03EAH MIOBASE0
03ECH MIOBASE1
03EEH
03FFH RESERVED
Tab - 10 Attribute Memory Mapping
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13
3.3 I/O Mapping
SYSTEM I/O OFFSET FUNCTION
0000H
001FH MAC CORE REGISTER
Tab - 11 I/O Address Mapping
3.4 SRAM Memory Mapping
OFFSET FUNCTION
0000H
03BFH CIS *1
03C0H LCOR *1
03C2H LCCSR *1
03C4H -
03C6H -
03CAH LIOBASE0 *1
03CCH LIOBASE1 *1
03CEH
03DFH RESERVED
03E0H MCOR *1
03E2H MCCSR *1
03E4H -
03E6H -
03EAH MIOBASE0 *1
03ECH MIOBASE1 *1
03EEH
03FFH RESERVED
0400H NODE ID 0
0401H NODE ID 1
0402H NODE ID 2
0403H NODE ID 3
0404H NODE ID 4
0405H NODE ID 5
0406H
07FFH RESERVED
4000H
7FFFH 8K X 16
SRAM BUFFER
Tab - 12 Local Memory Mapping
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4.0 Registers Operation
There are three register sets in AX88190A :
The PCMCIA function configuration registers of LAN.
The PCMCIA function configuration registers of MODEM.
The MAC core register.
4.1 PCMCIA Function Configuration Register Set of LAN
REGISTER NAME OFFSET
LCOR CONFIGURATION OPTION REGISTER 3C0H
LCSR CONFIGURATION AND STATUS REGISTER 3C2H
LIOBASE0 I/O BASED REGISTER 0 3CAH
LIOBASE1 I/O BASED REGISTER 1 3CCH
Tab - 13 PCMCIA Function Configuration Register Mapping of LAN
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4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)
FIELD R/W/C DESCRIPTION
7R/W Software Reset
Assert this bit will reset the LAN function of AX88190A. Return a 0 to this bit will leave
the LAN function of AX88190A in a post-reset state as same as that following a hardware
reset. The value of this bit is 0 at power-on.
6R/W Level IRQ
This bit should be set to 1, the AX88190A always generates Level Mode Interrupt.
5:0 R/W Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit 4, Bit 3 : MODEM I/O base registers
Bit 5 Bit 4 Bit 3 LAN I/O base MODEM I/O base
0 0 0 300H Decided by MIOBASE registers
0 0 1 320H 2f8H
0 1 0 340H 3e8H
0 1 1 360H 2e8H
1 0 0 380H Decided by MIOBASE registers
1 0 1 200H 2f8H
1 1 0 220H 3e8H
1 1 1 240H 2e8H
Bit 2 : Enable IREQ# Routing
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will generate interrupt request
via IREQ# signal. If this bit is set to 0, the LAN will not generate interrupt request via
IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by
the Base and Limit registers are passed to LAN function. If this bit is set to 0,all I/O
addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the LAN function is disabled.
If this bit is set to 1, the LAN function is enabled.
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4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)
FIELD R/W/C DESCRIPTION
7:3 -Reserved
2R/W PPwrDwn : PHY power down setting
While this bit set to 1, PPWDN pin (pin 114) will be active to force PHY chip into power
down mode. As for PPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.
1RIntr : Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
0RIntrAck : Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to
access the LAN specific registers (MAC Core Registers).
I/O Base Register 0
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 7 – 0.
I/O Base Register 1
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 15 – 8.
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4.2 PCMCIA Function Configuration Register Set of MODEM
REGISTER NAME OFFSET
MCOR CONFIGURATION OPTION REGISTER 3E0H
MCSR CONFIGURATION AND STATUS REGISTER 3E2H
MIOBASE0 I/O BASED REGISTER 0 3EAH
MIOBASE1 I/O BASED REGISTER 1 3ECH
Tab - 14 PCMCIA Function Configuration Register Mapping of MODEM
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)
FIELD R/W/C DESCRIPTION
7R/W Software Reset
Assert this bit will reset the MODEM function of AX88190A. Return a 0 to this bit will
leave the MODEM function of AX88190A in a post-reset state as same as that following
a hardware reset. The value of this bit is 0 at power-on.
6R/W Level IRQ
This bit should be set to 1, the AX88190A always generates Level Mode Interrupt.
5:0 R/W Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit4 : Reserved
Bit 3 : MINT route to STSCHG#
If bit 0 of MCOR is set to 0, this bit is ignored.
If both bit 0 and bit 2 of MCOR are set to 1 and this bit is set to 1, the MODEM will route
interrupt request to STSCHG# signal. If this bit is set to 0, the MODEM will generate
interrupt request via IREQ# line.
Bit 2 : MINT route to IREQ# (Enable IREQ# Routing)
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1, the MODEM will generate interrupt
request via IREQ# signal. If this bit is set to 0, the MODEM will not generate interrupt
request via IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified
by the Base and Limit registers are passed to MODEM function. If this bit is set to 0,all
I/O addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the MODEM function is disabled.
If this bit is set to 1, the MODEM function is enabled.
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4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write)
FIELD R/W/C DESCRIPTION
7:3 -Reserved
2R/W MPwrDwn : Modem power down setting
While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power
down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross reference table.
1RIntr : Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
0RIntrAck : Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)
The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to
access the MODEM specific registers.
I/O Base Register 0
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 7 – 0.
I/O Base Register 1
FIELD R/W/C DESCRIPTION
7:0 R/W Base I/O address bit 15 – 8.
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4.3 MAC Core Registers
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the Command
Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET READ WRITE
00H Command Register
( CR ) Command Register
( CR )
01H Page Start Register
( PSTART ) Page Start Register
( PSTART )
02H Page Stop Register
( PSTOP ) Page Stop Register
( PSTOP )
03H Boundary Pointer
( BNRY ) Boundary Pointer
( BNRY )
04H Transmit Status Register
( TSR ) Transmit Page Start Address
( TPSR )
05H Number of Collisions Register
( NCR ) Transmit Byte Count Register 0
( TBCR0 )
06H Current Page Register
( CPR ) Transmit Byte Count Register 1
( TBCR1 )
07H Interrupt Status Register
( ISR ) Interrupt Status Register
( ISR )
08H Current Remote DMA Address 0
( CRDA0 ) Remote Start Address Register 0
( RSAR0 )
09H Current Remote DMA Address 1
( CRDA1 ) Remote Start Address Register 1
( RSAR1 )
0AH Reserved Remote Byte Count 0
( RBCR0 )
0BH Reserved Remote Byte Count 1
( RBCR1 0
0CH Receive Status Register
( RSR ) Receive Configuration Register
( RCR )
0DH Frame Alignment Errors
( CNTR0 ) Transmit Configuration Register ( TCR )
0EH CRC Errors
( CNTR1 ) Data Configuration Register
( DCR )
0FH Missed Packet Errors
( CNTR2 ) Interrupt Mask Register
( IMR )
10H
11H Data Port Data Port
12H IFGS1 IFGS1
13H IFGS2 IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H -Test Register
16H Inter-frame Gap (IFG)Inter-frame Gap (IFG)
17H – 18H Reserved Reserved
19H GPI Reserved
1AH GPIO GPIO
1BH - 1EH Reserved Reserved
1FH Reset Reserved
Tab - 15 Page 0 of MAC Core Registers Mapping
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PAGE 1 (PS1=0,PS0=1)
OFFSET READ WRITE
00H Command Register
( CR ) Command Register
( CR )
01H Physical Address Register 0
( PARA0 ) Physical Address Register 0
( PAR0 )
02H Physical Address Register 1
( PARA1 ) Physical Address Register 1
( PAR1 )
03H Physical Address Register 2
( PARA2 ) Physical Address Register 2
( PAR2 )
04H Physical Address Register 3
( PARA3 ) Physical Address Register 3
( PAR3 )
05H Physical Address Register 4
( PARA4 ) Physical Address Register 4
( PAR4 )
06H Physical Address Register 5
( PARA5 ) Physical Address Register 5
( PAR5 )
07H Current Page Register
( CPR ) Current Page Register
( CPR )
08H Multicast Address Register 0
( MAR0 ) Multicast Address Register 0
( MAR0 )
09H Multicast Address Register 1
( MAR1 ) Multicast Address Register 1
( MAR1 )
0AH Multicast Address Register 2
( MAR2 ) Multicast Address Register 2
( MAR2 )
0BH Multicast Address Register 3
( MAR3 ) Multicast Address Register 3
( MAR3 )
0CH Multicast Address Register 4
( MAR4 ) Multicast Address Register 4
( MAR4 )
0DH Multicast Address Register 5
( MAR5 ) Multicast Address Register 5
( MAR5 )
0EH Multicast Address Register 6
( MAR6 ) Multicast Address Register 6
( MAR6 )
0FH Multicast Address Register 7
( MAR7 ) Multicast Address Register 7
( MAR7 )
10H
11H Data Port Data Port
12H Inter-frame Gap Segment 1
IFGS1 Inter-frame Gap Segment 1
IFGS1
13H Inter-frame Gap Segment 2
IFGS2 Inter-frame Gap Segment 2
IFGS2
14H MII/EEPROM Access MII/EEPROM Access
15H -Test Register
16H Inter-frame Gap (IFG)Inter-frame Gap (IFG)
17H – 18H Reserved Reserved
19H GPI Reserved
1AH GPIO GPIO
1BH - 1EH Reserved Reserved
1FH Reset Reserved
Tab - 16 Page 1 of MAC Core Registers Mapping
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4.3.1 Command Register (CR) Offset 00H (Read/Write)
FIELD NAME DESCRIPTION
7:6 PS1,PS0 PS1,PS0 : Page Select
The two bit selects which register page is to be accessed.
PS1 PS0
0 0 page 0
0 1 page 1
5:3 RD2,RD1
,RD0 RD2,RD1,RD0 : Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88190A when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address are not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0 0 0 Not allowed
0 0 1 Remote Read
0 1 0 Remote Write
0 1 1 Not allowed
1 X X Abort / Complete Remote DMA
2TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
1START START :
This bit is used to active AX88190A operation.
0STOP STOP : Stop AX88190A
This bit is used to stop the AX88190A operation.
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD NAME DESCRIPTION
7RST Reset Status :
Set when AX88190A enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
6RDC Remote DMA Complete
Set when remote DMA operation has been completed
5 CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
4OVW Over Write : Set when receive buffer ring storage resources have been exhausted.
3TXE Transmit Error
Set when packet transmitted with one or more of the following errors
Excessive collisions
FIFO Under-run
2RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
1PTX Packet Transmitted
Indicates packet transmitted with no error
0PRX Packet Received
Indicates packet received with no error.
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4.3.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD NAME DESCRIPTION
7-Reserved
6RDCE DMA Complete Interrupt Enable. Default “low” disabled.
5CNTE Counter Overflow Interrupt Enable. Default “low” disabled.
4OVWE Overwrite Interrupt Enable. Default “low” disabled.
3TXEE Transmit Error Interrupt Enable. Default “low” disabled.
2RXEE Receive Error Interrupt Enable. Default “low” disabled.
1 PTXE Packet Transmitted Interrupt Enable. Default “low” disabled.
0PRXE Packet Received Interrupt Enable. Default “low” disabled.
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD NAME DESCRIPTION
7RDCR Remote DMA always completed
6:2 -Reserved
1BOS Byte Order Select
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80X86).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(68K)
0WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD NAME DESCRIPTION
7FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
6PD Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
5RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
4:3 -Reserved
2:1 LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0 0 0 Normal operation
Mode 1 0 1 Internal NIC loop-back
Mode 2 1 0 PHYcevisor loop-back
0CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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4.3.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD NAME DESCRIPTION
7OWC Out of window collision
6:4 -Reserved
3ABT Transmit Aborted
Indicates the AX88190A aborted transmission because of excessive collision.
2COL Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
1-Reserved
0PTX Packet Transmitted
Indicates transmission without error.
4.3.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD NAME DESCRIPTION
7INT_RG Interrupt Regeneration
0 : Enable interrupt regeneration function in multifunction application. (default) But must
set CIS relative Enable function first, than the function will be open.
1: Disable
6-Reserved
5MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
4PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
3AM AM : Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
2AB AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
1AR AR : Accept Runt
Enable the receiver to accept runt packet.
0SEP SEP : Save Error Packet
Enable the receiver to accept and save packets with error.
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD NAME DESCRIPTION
7-Reserved
6DIS Receiver Disabled
5PHY Multicast Address Received.
4MPA Missed Packet
3FO FIFO Overrun
2FAE Frame alignment error.
1CR CRC error.
0PRX Packet Received Intact
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD NAME DESCRIPTION
7-Reserved
6:0 IFG Inter-frame Gap. Default value 15H.
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4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD NAME DESCRIPTION
7-Reserved
6:0 IFG Inter-frame Gap Segment 1. Default value 1cH.
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD NAME DESCRIPTION
7-Reserved
6:0 IFG Inter-frame Gap Segment 2. Default value 11H.
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD NAME DESCRIPTION
7EECLK EECLK
EEPROM Clock
6EEO EEO
EEPROM Data Out
5EEI EEI
EEPROM Data In
4EECS EECS
EEPROM Chip Select
3MDO MDO
MII Data Out
2MDI MDI
MII Data In
1MDIR MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
0MDC MDC
MII Clock
4.3.13 Test Register (TR) Offset 15H (Write)
FIELD NAME DESCRIPTION
7-Reserved
6MPSEL Media Priority Select : default value is logic 0
MPSEL /SLINK Media Selected
0 0 SNI
0 1 MII
1 x Depand on MPSET bit
5MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.
When MPSET is logic 0 , SNI is selected.
When MPSET is logic 1 , MII is selected.
4TF16T Test for Collision, default value is logic 0
3TPE Test pin Enable, default value is logic 0
2:0 IFG Select Test Pins Output, default value is logic 0
4.3.14 General Purpose Input Register (GPI) Offset 18H (Read)
FIELD NAME DESCRIPTION
7:4 -Reserved
3GPI3 This register reflects GPI[3] input value
2GPI2 This register reflects GPI[2] input value
1GPI1 This register reflects GPI[1] input value
0GPI0 This register reflects GPI[0] input value
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4.3.15 General Purpose I/O Register (GPIO) Offset 1AH (Read/Write)
FIELD NAME DESCRIPTION
7:6 -Reserved
5CTL Default “1”. And must keep it to logic 1 always.
4-Reserved
3GPIO3 Default “0”. The register reflects to GPIO3# pin with inverted value.
2GPIO2 Default “0”. The register reflects to GPIO2 pin directly.
1GPIO1 Default “0”. The register reflects to GPIO1# pin with inverted value.
0GPIO0 Default “0”. The register reflects to GPIO0# pin with inverted value.
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5.0 PCMCIA Device Access Functions
5.1 Attribute Memory access function functions.
Attribute Memory Read function
Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode XHHX X X High-Z High-Z
Byte Access (8 bits) L
LH
HL
LL
HL
LH
HHigh-Z
High-Z Even-Byte
Not Valid
Word Access (16 bits) L L L XLHNot Valid Even-Byte
Odd Byte Only Access L L HXLHNot Valid High-Z
Attribute Memory Write function
Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode XHHX X X X X
Byte Access (8 bits) L
LH
HL
LL
HH
HL
LX
XEven-Byte
X
Word Access (16 bits) L L L XHLXEven-Byte
Odd Byte Only Access L L HXHLX X
5.2 I/O access function functions.
I/O Read function
Function Mode REG# CE2# CE1# SA0 OE# WE# SD[15:8] SD[7:0]
Standby Mode XHHX X X High-Z High-Z
Byte Access (8 bits) L
LH
HL
LL
HL
LH
HHigh-Z
High-Z Even-Byte
Odd-Byte
Word Access (16 bits) L L L L L HOdd-Byte Even-Byte
I/O Inhibit HX X X LHHigh-Z High-Z
Odd Byte Only Access L L HXLHOdd-Byte High-Z
I/O Write function
Function Mode REG# CE2# CE1# SA0 IORD# IOWR# SD[15:8] SD[7:0]
Standby Mode XHHX X X X X
Byte Access (8 bits) L
LH
HL
LL
HH
HL
LX
XEven-Byte
Odd-Byte
Word Access (16 bits) L L L L HLOdd-Byte Even-Byte
I/O Inhibit HXXXHLX X
Odd Byte Only Access L L HXHLOdd-Byte X
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6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description SYM Min Max Units
Operating Temperature Ta 0+85 °C
Storage Temperature Ts -55 +150 °C
Supply Voltage HVdd -0.3 +6 V
Supply Voltage LVdd -0.3 +4.6 V
Input Voltage HVin
LVin -0.3
-0.3 HVdd+0.5
LVdd+0.5 V
V
Output Voltage HVout
LVin -0.3
-0.3 HVdd+0.5
LVdd+0.5 V
V
Lead Temperature (soldering 10 seconds maximum) Tl -55 +220 °C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.2 General Operation Conditions
Description SYM Min Tpy Max Units
Operating Temperature Ta 0 25 +75 °C
Supply Voltage HVdd
LVdd +4.75V
+2.70
+3.00
+5.00V
+3.00
+3.30
+5.25V
+3.30
+3.60
V
V
V
Note : The power supply voltages must always fulfill HVdd >= LVdd inequality.
6.3 DC Characteristics
(Vdd=5.0V, Vss=0V, Ta=0°C to 75°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil -0.8 V
High Input Voltage Vih 2-V
Low Output Voltage Vol -0.4 V
High Output Voltage Voh Vdd-0.4 -V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil -0.8 V
High Input Voltage Vih 1.9 -V
Low Output Voltage Vol -0.4 V
High Output Voltage Voh Vdd-0.4 -V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -1 +1 uA
Description SYM Min Tpy Max Units
Power Consumption (Dual power) DPt5v
DPt3v 17
31 mA
mA
Power Consumption (Single power 3.3V) SPt3v 48 mA
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6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
LCLK/XTALIN
Tr Tf Tlow
CLKO Tod
Symbol Description Min Typ. Max Units
Tcyc CYCLE TIME 40* ns
Thigh CLK HIGH TIME 16 20 24 ns
Tlow CLK LOW TIME 16 20 24 ns
Tr/TfCLK SLEW RATE 1-4ns
Tod LCLK/XTALIN TO CLKO OUT DELAY 10
* Note : The Tcyc can be from 16.6ns to 50ns, that is frequency from 60MHz to 20MHz.
6.4.2 Reset Timing
LCLK
RESET
Symbol Description Min Typ. Max Units
Trst Reset pulse width 100 - - LClk
Tcyc
Thigh
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6.4.3 Attribute Memory Read Timing
TcR
Ta(A) Th(A)
A[9:0], REG#
Ta(CE) Tv(A)
Tsu(CE)
CE#
Tsu(A) Ta(OE) Th(CE)
OE#
Tv(WT-OE) Tw(WT) Tdis(CE)
WAIT#
Ten(OE) Tv(WT) Tdis(OE)
D[15:0] DATA Valid
Symbol Description Min Typ. Max Units
TcR READ CYCLE TIME 300 - - ns
Ta(A) ADDRESS ACCESS TIME - - 120 ns
Ta(CE) CARD ENABLE ACCESS TIME - - 100 ns
Ta(OE) OUTPUT ENABLE ACCESS TIME - - 100 ns
Tdis(OE) OUTPUT DISABLE TIME FROM OE# 0.5 - - ns
Ten(OE) OUTPUT ENABLE TIME FROM OE# - - 100 ns
Tv(A) DATA VALID FROM ADDRESS CHANGE 0- - ns
Tsu(A) ADDRESS SETUP TIME 30 - - ns
Th(A) ADDRESS HOLD TIME 20 - - ns
Tsu(CE) CARD ENABLE SETUP TIME 0- - ns
Th(CE) CARD ENABLE HOLD TIME 20 - - ns
Tv(WT-OE) WAIT# VALID FROM OE# - - 10 ns
Tw(WT) WAIT# PULSE WIDTH - - 200 ns
Tv(WT) DATA SETUP FOR WAIT# RELEASED 100 - - ns
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6.4.4 Attribute Memory Write Timing
TcW
A[9:0], REG#
Tsu(CE-WEH)
CE# Tsu(CE)
Tsu(A-WEH) Th(CE)
OE#
Tsu(A) Tw(WE) Trec(WE)
WE#
Tv(WT-WE) Tv(WT)
Tw(WT) Th(OE-WE)
WAIT#
Tsu(OE-WE) Tsu(D-WEH) Th(D)
D[15:0](Din) DATA Input Establish
Tdis(WE) Ten(OE)
Tdis(OE) Ten(WE)
D[15:0](Dout)
Symbol Description Min Typ. Max Units
TcW WRITE CYCLE TIME 250 - - ns
Tw(WE) WRITE PULSE WIDTH 150 - - ns
Tsu(A) ADDRESS SETUP TIME 30 - - ns
Tsu(A-WEH) ADDRESS SETUP TIME FOR WE# 180 - - ns
Tsu(CE-WEH) CARD ENABLE SETUP TIME FOR WE# 180 - - ns
Tsu(D-WEH) DATA SETUP TIME FOR WE# 80 - - ns
Th(D) DATA HOLD TIME 30 - - ns
Trec(WE) WRITE RECOVER TIME 30 - - ns
Tdis(WE) OUTPUT DISABLE TIME FROM WE# - - 5ns
Tdis(OE) OUTPUT DISABLE TIME FROM OE# - - 5ns
Ten(WE) OUTPUT ENABLE TIME FROM WE# 5- - ns
Ten(OE) OUTPUT ENABLE TIME FROM OE# 5- - ns
Tsu(OE-WE) OUTPUT ENABLE SETUP TIME FROM OE# 10 - - ns
Th(OE-WE) OUTPUT ENABLE HOLD TIME FROM OE# 10 - - ns
Tsu(CE) CARD ENABLE SETUP TIME 0- - ns
Th(CE) CARD ENABLE HOLD TIME 20 - - ns
Tv(WT-WE) WAIT# VALID FROM WE# - - 15 ns
Tw(WT) WAIT# PULSE WIDTH - - 200 ns
Tv(WT) WE# HIGH FROM WAIT# RELEASED 0- - ns
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
31
6.4.5 I/O Read Timing
A[9:0]
ThA
TsuREG ThREG
REG#
TsuCE ThCE
CE#
Tw
IORD#
TsuA TdrINPACK
INPACK#
TdfINPACK TdrIOIS16
IOIS16#
TdfIOIS16 Td Tdr(WT)
WAIT#
TdfWT Tw(WT) Th
D[15:0] DATA Valid
Symbol Description Min Typ. Max Units
TdDATA DELAY AFTER IORD# - - 50 ns
ThDATA HOLD FOLLOWING IORD# 0.5 - - ns
TwIORD# WIDTH TIME 165 - - ns
TsuA ADDRESS SETUP BEFORE IORD# 70 - - ns
ThA ADDRESS HOLD BEFORE IORD# 20 - - ns
TsuCE CE# SETUP BEFORE IORD# 5- - ns
ThCE CE# HOLD BEFORE IORD# 20 - - ns
TsuREG REG# SETUP BEFORE IORD# 5- - ns
ThREG REG# HOLD BEFORE IORD# 0- - ns
TdfINPACK INPACK# DELAY FALLING FROM IORD# 0-10 ns
TdrINPACK INPACK# DELAY RISING FROM IORD# - - 10 ns
TdfIOIS16 IOIS16# DELAY FALLING FROM ADDRESS* - - 10 ns
TdrIOIS16 IOIS16# DELAY RISING FROM ADDRESS* - - 0ns
TdfWT WAIT# DELAY FALLING FROM IORD# - - 5ns
Tdr(WT) DATA DELAY FROM WAIT# RISING - - 0us
Tw(WT) WAIT# WIDTH TIME - - 100 ns
* Note : The address includes REG# and CE1# signal
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
32
6.4.6 I/O Write Timing
A[9:0]
ThA
TsuREG ThREG
REG#
TsuCE ThCE
CE#
Tw
IOWR#
TsuA TdrIOIS16
IOIS16#
TdfIOIS16 TdrIOWR
WAIT#
TdfWT Tw(WT) Th
Tsu
D[15:0] DATA
Symbol Description Min Typ. Max Units
Tsu DATA SETUP BEFORE IOWR# 60 - - ns
ThDATA HOLD FOLLOWING IOWR# 30 - - ns
TwIOWR# WIDTH TIME 165 - - ns
TsuA ADDRESS SETUP BEFORE IOWR# 70 - - ns
ThA ADDRESS HOLD BEFORE IOWR# 20 - - ns
TsuCE CE# SETUP BEFORE IOWR# 5- - ns
ThCE CE# HOLD BEFORE IOWR# 20 - - ns
TsuREG REG# SETUP BEFORE IOWR# 5- - ns
ThREG REG# HOLD BEFORE IOWR# 0- - ns
TdfIOIS16 IOIS16# DELAY FALLING FROM ADDRESS* - - 10 ns
TdrIOIS16 IOIS16# DELAY RISING FROM ADDRESS* - - 0ns
TdfWT WAIT# DELAY FALLING FROM IOWR# - - ** ns
Tw(WT) WAIT# WIDTH TIME - - ** ns
TdrIOWR IOWR# HIGH FROM WAIT# HIGH 0- - us
*Note : The address includes REG# and CE1# signal
** Note : There is no wait state while I/O Write operation
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
33
6.4.7 MII Timing
Ttclk Ttch Ttcl
TXCLK
Ttv Tth
TXD<3:0>
TXEN
Trclk Trch Trcl
RXCLK
Trs Trh
RXD<3:0>
RXDV
Trs1
RXER
Symbol Description Min Typ. Max Units
Ttclk Cycle time(100Mbps) -40 -ns
Ttclk Cycle time(10Mbps) -400 -ns
Ttch high time(100Mbps) 14 -26 ns
Ttch high time(10Mbps) 140 -260 ns
Trch low time(100Mbps) 14 -26 ns
Trch low time(10Mbps) 140 -260 ns
Ttv Clock to data valid - - 20 ns
Tth Data output hold time 5- - ns
Trclk Cycle time(100Mbps) -40 -ns
Trclk Cycle time(10Mbps) -400 -ns
Trch high time(100Mbps) 14 -26 ns
Trch high time(10Mbps) 140 -260 ns
Trcl low time(100Mbps) 14 -26 ns
Trcl low time(10Mbps) 140 -260 ns
Trs data setup time 6- - ns
Trh data hold time 10 - - ns
Trs1 RXER data setup time 10 - - ns
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
34
6.4.8 SNI Timing
Ttclk Ttch Ttcl
STXC
Ttv Tth
STXD
STXE
Trclk Trch Trcl
SRXC
Trs Trh
SRXD
SCRS
Symbol Description Min Typ. Max Units
Ttclk Cycle time(10Mbps) -100 -ns
Ttch high time(10Mbps) 45 -55 ns
Trch low time(10Mbps) 45 -55 ns
Ttv Clock to data valid - - 26 ns
Tth Data output hold time 5- - ns
Trclk Cycle time(10Mbps) -100 -ns
Trch high time(10Mbps) 45 -55 ns
Trcl low time(10Mbps) 45 -55 ns
Trs data setup time 10 - - ns
Trh data hold time 5- - ns
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
35
7.0 Package Information
be
D
Hd
E
He
pin 1
A2 A1
L
L1
θ
A
MILIMETERSYMBOL
MIN. NOM MAX
A1 0.1
A2 1.3 1.4 1.5
A1.7
b0.155 0.16 0.26
D13.90 14.00 14.10
E13.90 14.00 14.10
e0.40
Hd 15.60 16.00 16.40
He 15.60 16.00 16.40
L0.30 0.50 0.70
L1 1.00
θ0 10
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
36
Appendix A: Application Note
A.1 Using Crystal 25MHz or 20MHz
AX88190A To PHY
CLKO 25MHz
XTALIN XTALOUT
25MHz
Crystal
8pf 2Mohm 8pf
Note : The capacitors (8pf) may be various depend on the specification of crystal. While designing, please
refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator 25MHz or 20MHz
AX88190A To PHY
CLKO 20MHz
XTALIN XTALOUT
NC
3.3V Power OSC 20MHz
A.3 Using 60MHz Oscillator/Crystal
AX88190A To PHY
CLKO 60MHz
CLK_DIV3#
Pull Low 20MHz
XTALIN XTALOUT
NC
3.3V Power OSC 60MHz
Devided
By 3
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
37
A.4 Dual power (5V and 3.3V) application
+5V +5V
+3.3V
(option for core logic)
+5V HVdd +5V
+3.3V LVdd
A.5 Single power (3.3V) application
+3.3V +3.3V
+3.3V HVdd +3.3V
+3.3V LVdd
AX88190A
PHY/TxRxMODEM
DAA
MAGNETIC
RJ45RJ11
+5V PCMCIA I/F
EEPROM
AX88190A
PHY/TxRxMODEM
DAA
MAGNETIC
RJ45RJ11
+3.3V PCMCIA I/F
EEPROM
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
38
A.6 Dual power (5V and 3.3V) application with 3.3V PHY
The 510 and 1K Ohm resisters are just for voltage adjustment
AX88190A
PHY
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
RXD[3:0]
CRS
RX_DV
RX_ER
RX_CLK
COL
TX_EN
TXD[3:0]
TX_CLK
MDC
MDIO
510 ohm 1k ohm
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
39
Appendix B: AX88190 design changes to AX88190A
Please refer to following circuit diagram that implement in AX88190 PWB and follow the following
four steps.
1. Remove AX88190 and replace with AX88190A
2. Remove 2 pieces of buffer memory(32k*8 SRAM). Because they are not necessary anymore.
3. Remove 74F86 and 74F74 TTL IC
4. Shorten the jumper shown as below circuit diagram lable “Jumper for future use”
From PCMCIA
Connector
Pin 9
From AX88190
Pin 101
To AX88190
Pin 16
Jumper for future use
CLK25M
OE_# OE_M#
U1B
74F74
D
12
CLK
11 Q9
Q8
PR 10
CL
13
U1A
74F74
D
2
CLK
3Q5
Q6
PR 4
CL
1
U2A
74F86
1
23
AX88190A PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
40
Errata of AX88190A Version ED2
1. SNI (Serial Network Interface) has bug for HomePNA application.
Solution: Using MII interface for HomePNA solution. Refer to “Demonstration Circuit”
on page 39 to 44.
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
41
Demonstration Circuit : AX88190A + Ethernet PHY + HomePNA 1M8 PHY
VCC
GND
SPKR#
SA8
SD7
AX88190AL 10BASE-T/100BASE-TX & 1M HomePNA
Application with DP83846A & DP83851 PHYceiver.
(reference only)
CE2#
3.3V
SD8
OE#
IOWR#
VCC
R40
1k
INPACK#
SA5
RESET
IOIS16#
SD1
IOWR#
IREQ#
SD5
GND
SD14
IORD#
3.3V
CE2#
GND
SA3
WE#
+
C10
4.7uF/16V
IREQ#
SA0
SD15
CE1#
GND
GND
VCC
VCC
IORD#
INPACK#
WE#
INPACK# STSCHG#
SA1
GND
REG#
OE#
SA7
SD12
GND
IOIS16#
SD2
IORD#
IOWR#
STSCHG#
SPKR#
+
C1
4.7uF/16V
U4
PCMCIA-68
ICM-68FYC-OM03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
IORD#
IOWR#
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
R40 : option for 3.3V card tpye.
CE2#
WAIT#
SD13
C9
0.01u
IREQ#
WE#
CE1#
REG#
C12
0.01u
WAIT#
RESET
RESET
SA9
GND
SD9
SA6
CE1#
SPKR#
STSCHG#
GND
SD11
SD0
WAIT#
VCC
SA4
GND
SA2
3.3V
SD[0..15]
U7
AMS117
1
4
23
ADJ/GND
TAB/OUT
OUTIN
SD6
SA[0..9]
C32
0.01u
+
C8
4.7uF/16V
OE#
REG#
SD4
SD3
SD10
IOIS16#
VCC
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
42
RXCLK
R22 10K
3.3V
INPACK#
OE# SA1
TXD3
SPKR#
R21 10k
PCLK
GND
R7
2M
INPACK#
RXD1
XIN
CE2#
IREQ#
COL
EEDO
TXD0
RXD2
C19
0.1u
RXDV
R25 10K
RXD1
RXER
IORD#
IOIS16#
RXDV
GND
SD13
RESET#
C25
0.1u
TXEN
COL
PCLK
MDC
GND
SD8
CRS
EEDI
SD10
COL
OE#
3.3V
TXCLK
IREQ#
GND
SD2
SA9
IOWR#
SPKR#
RXD0
TXEN
(R23 : option for use 93C46)
5V
GND
EEDO
IOIS16#
5V
SD15
(R22 : option for test)
SPKR#
OE#
SD11
3.3V
SD1
IOIS16#
CE1#
RESET#
SD[0..15]
RXD2
IORD#
SD5
IOWR#
5V
SA8
IOWR#
RXD3
RESET
VCC
STSCHG#
SA5
RXD3
SA0
SD7
C23
0.1u
3.3V
REG#
WE#
TXD1
EECS
TXEN
3.3V
R2
4.7K
EESK
EECS
R6
10K
IREQ#
CE1#
EEDI
WAIT#
RXER
SA3
WAIT#
SA[0..9]
PCLK
SD9
RXD[0..3]
3.3V
SA4
(R42 : option for RESERVED)
SD14
C17
8p
RESET
Y1 25MHZ-CRYSTAL
WAIT#
WE#
CRS
C16
0.1u
XOUT
SA2
MDC
MDIO
U1
93C56
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
NC
NC
VCC
RXCLK
IORD#
C18
8p
RESET
CRS
XIN
MDIO
RXDV
SD0
R41 10K
INPACK#
MDIO
REG#
RESET#
MDC
WE#
TXCLK
CE2#
5V
SD3
RXD0
U5
AX88190AL
1
2
3
4
5
6
7
8
9
10
38
37
36
35
33
32
31
30
28
27
26
25
23
22
21
20
18
16
13
12
120
17
15
14
127
125
124
123
122
121
19
29
64
75
44
54
100
110
126
128
11
24
34
39
40
49
59
69
81
93
102
105
119
111
112
113
115
116
117
118
68
70
74
82
83
84
85
86
87
88
89
90
94
95
96
97
98
99
91
92
106
107
108
109
114
104
103
101
77
73
61
60
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CE1#
OE#
WE#
IREQ#
IOIS16#
CE2#
IORD#
IOWR#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
HVDD
HVDD
HVDD
HVDD
LVDD
LVDD
LVDD
LVDD
LVDD
LVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MDCS#
MMINT
MAUDIO
MRIN#
MPWDN
MRESET#
MRDY
MPD_SET
PPD_SET
SLINK#
RX_ER
RX_DV
COL
CRS
RX_CLK
RXD0
RXD1
RXD2
RXD3
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
MDIO
MDC
EECS
EECK
EEDI
EEDO
PPWDN
XTALOUT
LCLK/XTALIN
CLKO25M
TEST#
EEPROM SIZE
GPI0
GPI1
SA7
R23 10K
STSCHG#
SA6
CE1#
RXCLK
RXD[0..3]
TXD2
RXER
SD6
SD4
SD12
XOUT
R42 10K C20
0.1u
STSCHG#
3.3V
R8
20
CE2#
EESK
REG#
TXCLK
C24
0.1u
TXD[0..3]
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
43
RESET#
R1
4.7K
HSPDLED
TXD1
ACTLED
Set PHY address to 00000.
3.3V
GND
C13
0.1u
R17
510
TIP
3.3VA1
TXCLK
PWRLED
HCOLLED
ACTLED
3.3V
SPDLED
RXCLK
3.3V
RXD2
PWRLED
RXD3
RXD3
COLLED
CRS
HACTLED
TXEN
TXEN
PCLK HACTLED
CRS
R14
510
C14
0.1u
3.3V HCOLLED
R20
9.31K
1%
L1
F.B.
GND
TXCLK
RXD1
HSPDLED
TXCLK
TXD0
+
C7
4.7uF/16V
HSPDLED
3.3VA1
U3
DP83851
36
35
34
33
32
31
23
24
25
26
27
28
37
38
21
22
45
46
19
29
39
5
11
20
7
8
4
17
18
16
15
44
14
42
43
48
30
40
41
47
3
6
10
1
2
9
12
13
TXD3
TXD2
TXD1
TXD0/TXD
TX_EN
TX_CLK
RXD3/PHYAD0
RXD2/CMDDIS#
RXD1/HI_POWER_EN#
RXD0/RXD/LOW_SPEED_EN#
RX_DV/GPSI_SEL#
RX_CLK
COL/MDIO_INT_EN#
CRS/PIN_INTRP_EN#
MDIO
MDC
X1
X2
IO_VDD1
IO_VDD2
CORE_VDD
ANA_VDD2
ANA_VDD3
IO_GND1
TIP
RING
RBIAS
LED_COL/PHYAD2
LED_ACT/PHYAD1
LED_SPEED/PHYAD3
LED_POWER/PHYAD4
RESET#
RESERVED
RESERVED
RESERVED
ANA_VDD1
IO_GND2
CORE_GND
CORE_SUB(0V)
ANA_GND1
ANA_GND2
ANA_GND3
ANA_GND4
SUB_GND1
SUB_GND2
SUB_GND3
RESERVED
RESERVED
MDC MDIO
COL
3.3V
R16
510
TIP
3.3V C15
0.1u
TXD3
RING
COLLED
3.3VA2
3.3VA2
HCOLLED
TXD[0..3]
PCLK
TXD[0..3] RXCLK
SPDLED
C26
0.1u
C4
0.1u
PCLK
RXDV
RING
GND
R13
4.7K
RXD[0..3]
C21
0.1u
MDC
MDIO RXD3
R18 20
R4
4.7K
RESET#
3.3V
TXD2
GND
SPDLED
TXEN
COL
TIP
RXDV
R3 4.7K
RXD0
RXD2
HACTLED
GND
RXDV
L2
F.B.
COL
CRS
MDC
GND
RXD1
MDIO
R5
4.7K
C5
0.1u
R19 20
RXD0
ACTLED
RING
RESET#
RXD[0..3]
RXCLK
COLLED
R15
4.7K
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
44
TXD1
TDP
R30 510
R12 4.7K
RDN
C31
0.1u
L4
F.B.
TXCLK
FLED
GND
PHYAD1
PCLK
3.3V
RXDV
TXEN
L3
F.B.
RESET#
TXD3
LNKLED
RXD1
C41
0.01u
RLED
TLED
R47
9.31K
MDIO
GND
C22
0.01u
MDIO
TDN
PCLK
LNKLED
RXDV
TXCLK
RXER
RXD1
C35
0.1u
RESET#
C27
0.1u
R43 4.7K
RLED
COL
R32 510
3.3VA1
SPDLED
TXD[0..3]
SLED
C34
0.1u
GND
3.3V
ACTLED
R24 4.7K
RDP
3.3V
TLED
SPDLED
TDP3.3V
RDN
TLED
3.3V
RDP
LLED
CLED
CRS
ACTLED
PHYAD2
RXER
PCLK
3.3VA2
TDN
TXD2
CRS
RXD[0..3]
R11 4.7K
U8
DP83846A
59
58
55
54
52
51
38
39
40
41
44
45
60
61
36
37
67
66
57
65
12
14
64
3
7
23
73
2
9
13
15
18
19
76
79
50
46
16
17
11
10
1
5
8
20
21
22
47
63
68
69
70
71
74
75
77
78
80
6
48
34
42
53
56
4
24
49
72
43
35
62
33
32
31
30
29
28
27
26
25
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
COL
CRS/LED_CFG#
MDIO
MDC
X1
X2
IO_VDD
IO_VDD
ANA_VDD2
ANA_VDD3
IO_GND
RBIAS
ANA_VDD1
CORE_GND
CORE_GND
ANA_GND
ANA_GND
ANA_GND
ANA_GND
ANA_GND
SUB_GND
SUB_GND
SUB_GND
TX_ER
RX_ER/PAUSE_EN#
TD+
TD-
RD+
RD-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ANA_GND
CORE_GND
IO_GND
IO_GND
IO_GND
IO_GND
ANA_VDD
CORE_VDD
CORE_VDD
CORE_VDD
IO_VDD
IO_VDD
RESET#
LED_DPLX/PHY0
LED_COL/PHY1
LED_GDLNK/PHY2
LED_TX/PHY3
LED_RX/PHY4
LED_SPEED
AN_EN
AN_1
AN_0
R44 20
RESET#
LLED
PHYAD3
PHYAD4
TXD0
RXCLK
R27 20
RXD2
MDC
C39
0.1u
CRS
CLED
TDN
RXD2
R28 4.7K
PHYAD0
RDP
TXD[0..3]
RXD0
RLED
To PCMJ15 Connect
RXD3
R45
4.7K
TDP
3.3VA2
R29 510
R26 4.7K
Transmit Activity : used R29.
Receive Activity : used R30.
Transmit/Receive Activity :
D1 & D2 & R31.
RXCLK
GND
MDIO
ACTLED
RXD[0..3]
MDC
LLED
3.3V
LNKLED
C33
0.1u
TXEN
RXCLK
TXCLK
TXEN
3.3V
3.3V
RXD0
R31 510
GND
BY PASS CAP WITH DIGITAL POWER SUPPLY
FLED
RXDV
R33 510
RXER
BY PASS CAP WITH ANALOG POWER SUPPLY
SLED
SPDLED
GND
Set PHY ADDRESS TO 00011
RDN
R45 : Setting FDPX LED
(OPTION)
3.3VA1
D2 1N4148
GND
COL
C29
0.1u
RXD3
D1 1N4148
MDC
COL
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
45
TDP
C38
10p
RDN
SPDLED
C43 0.01u
TIP
R38
75
RDP
RING
J1
PCMCIA-15
RMC-E15MY-OM-MA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3.3V
C28
0.01u
GND
RDP
R34
49.9
1%
C11
0.01u/2KV
LNKLED
R35
49.9
1%
RING
C36
10p
HSPDLED
C3
0.01u/2KV
HACTLED
R48
75
C42
10p
TDN
U6
16ST0009P
6
7
8
1
2
3
11
10
9
16
15
14
CT
TD+
TD-
RD+
RD-
CT
CT
TX+
TX-
RX+
RX-
CT
TIP
ACTLED
HACTLED
HCOLLED
SPDLED
RX+
RX+
C37
0.01u
GND
R39
75
ACTLED
TDN
LRING
TX+
RDN
R10
49.9
1%
R37
75
C6
0.1u
TX-
TIP
TDN
LNKLED
R46
49.9
1%
CHASSIS
HACTLED
TDP
ACTLED
3.3V
RING R9
49.9
1%
RDP
C40
0.1u
RDN
LTIP
LNKLED
RX-
3.3V
3.3V
TX-
R49 1M
RX-
LRING
U2
LHR002
4
6
1
2
11
9
14
13
TUT+
TUT-
Z+
Z-
TIP+
RING-
C+
C-
C2
P0800SA
LTIP
SPDLED
R36
49.9
1%
HSPDLED
HCOLLED
HSPDLED
HCOLLED
GND
TDP
C30
10p
TX+
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
46
D5
LED
HACTLED
SPDLED
D8
LED
D4
LED
J3
CON8
1
2
3
4
5
6
7
8
D6
LED
TX+
HomePNA collision LED
TX+
HACTLED
RX-
10/100M collision LED
R45
LNKLED
HCOLLED
RX+
D3
LED
HomePNA speed LED
RX+
TX-
LTIP
HCOLLED
10/100Mspeed LED
ACTLED
GND
TX-
J4
RJ45N
1
2
3
6
4
5
7
8
LNKLED
J5
CON8
1
2
3
4
5
6
7
8
ACTLED
LRING
GND
R78
HSPDLED
R45
HomePNA activity LED
HSPDLED
R78
D7
LED
LTIP
SPDLED
RX-
J2
RJ11-S
1
2
3
4
5
6
NC
A1
TIP
RING
A2
NC
10/100M link LED
LRING
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
47
Reference Bill Of Materials
Item Quantity Reference Part Reamrk
1 2 C18,C17 8p 0603
2 4 C30,C36,C38,C42 10p 0603
3 8 C9,C12,C22,C28,C32,C37,C41,C43 0.01uF0603
4 22 C4,C5,C6,C13,C14,C15,C16,C19,C20,C21,C23,C24,C25,C26,C27,C29,C31,C33,C34,C35,C39,C40 0.1uF0603
5 4 C1,C7,C8,C10 4.7uF/16V 1206
6 2 C11,C3 0.01u/2KV 1206
7 1 C2 P0800SA *1
8 2 D2,D1 1N4148 SMD
9 6 D3,D4,D5,D6,D7,D8 LED DIP
10 4 L1,L2,L3,L4 F.B 1206
11 5 R8,R18,R19,R27,R44 20 0603
12 4 R37,R38,R39,R48 75 0603
13 5 R9,R10,R35,R46,R34,R36 49.9 1% 0603
14 5 R14,R16,R17,R32,R33 510 0603
14-1 1R31 330 0603
15 13 R1,R2,R3,R4,R5,R11,R12,R13,R15,R24,R26,R28,R43 4.7K 0603
16 2 R47,R20 9.31K 1% 0603
17 4 R6,R21,R25,R42 10K 0603
18 1 R49 1M 0603
19 1 R7 2M 0603
20 1 U5 AX88190AL TQFP
21 1 U1 93C56 SMD
22 1 U2 LHR002 *2
23 1 U6 16ST0009P *2
24 1 U3 DP83851 *3
25 1 U8 DP83846A *3
26 1 U7 AMS117 SMD
27 1 Y1 25MHZ CRYSTAL DIP
28 1 J2 RJ11 DIP
39 2 J3,J5 CON8 DIP
30 1 J4 RJ45 DIP
31 1 J1 PCMCIA-15 *4
32 1 U4 PCMCIA-68 *4
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
48
Sponsors of Components
Components Company Contect person Telephone
SIDACtor (P0800SA)GID GLORIA INTERNATIONAL Jason Hsu 02-25068371
TRANSFORMERS BOTHHAND ENTERPRISE INC. Dennis Fan 03-3698237
PHYceiver National Semiconductor Henry Chou 02-25370217
HONDA PCMCIA connectors & Frames Yun Hui Ltd. Zong-Ming Chen 02-27669242
AX88190A 10/100Mbps PCMCIA Fast Ethernet MAC Controller
ASIX ELECTRONICS CORPORATION
49
Sponsors of Components (Chinese)
Components Company Contect person Telephone
SIDACtor (P0800SA)GID GLORIA INTERNATIONAL
ºa´_°ê»Ú¦³--¤½¥qJason Hsu
®}ªø·Ë02-25068371
TRANSFORMERS BOTHHAND ENTERPRISE INC.
©-º~ªÑ¥÷¦³--¤½¥qDennis Fan
-S¥ò¦¨03-3698237
PHYceiver National Semiconductor Henry Chou
©P·çÅï02-25370217
HONDA PCMCIA connectors & Frames ¤¹×¦³--¤½¥q³¯Á`©ú02-27669242