Intel£Advanced+BootBlockFlash
Memory(C3)
28F800C3,28F160C3,28F320C3,28F640C3(x16)
Datasheet
ProductFeatures
TheIntel®Advanced+BookBlockFlashMemory(C3)device,manufacturedonIntel’slatest
0.13µmand0.18µmtechnologies,representsafeature-richsolutionforlow-powerapplications.
TheC3deviceincorporateslow-voltagecapability(3Vread,program,anderase)withhigh-
speed,low-poweroperation.Flexibleblocklockingallowsanyblocktobeindependentlylocked
orunlocked.AddtothistheIntel®
FlashDataIntegrator(FDI)softwareandyouhaveacost-
effective,flexible,monolithiccodeplusdatastoragesolution.Intel®Advanced+BootBlockFlash
Memory(C3)productswillbeavailablein48-leadTSOP,48-ballCSP,and64-ballEasyBGA
packages.AdditionalinformationonthisproductfamilycanbeobtainedbyaccessingtheIntel®
Flashwebsite:http://www.intel.com/design/flash.
■FlexibleSmartVoltageTechnology
—2.7V–3.6VRead/Program/Erase
—12VforFastProductionProgramming
■1.65 V–2.5 Vor2.7 V–3.6 VI/OOption
—ReducesOverallSystemPower
■HighPerformance
—2.7 V–3.6 V:70nsMaxAccessTime
■OptimizedArchitectureforCodePlus
DataStorage
—Eight4KwordBlocks,ToporBottom
ParameterBoot
—UptoOneHundred-Twenty-Seven32
KwordBlocks
—FastProgramSuspendCapability
—FastEraseSuspendCapability
■FlexibleBlockLocking
—Lock/UnlockAnyBlock
—FullProtectiononPower-Up
—WP#PinforHardwareBlockProtection
■LowPowerConsumption
—9mATypicalRead
—7ATypicalStandbywithAutomatic
PowerSavingsFeature(APS)
■ExtendedTemperatureOperation
—–40°Cto+85°C
■128-bitProtectionRegister
—64bitUniqueDeviceIdentifier
—64bitUserProgrammableOTPCells
■ExtendedCyclingCapability
—Minimum100,000BlockEraseCycles
■Software
—Intel®FlashDataIntegrator(FDI)
—SupportsToporBottomBootStorage,
StreamingData(e.g.,voice)
—IntelBasicCommandSet
—CommonFlashInterface(CFI)
■StandardSurfaceMountPackaging
—48-BallµBGA*/VFBGA
—64-BallEasyBGAPackages
—48-LeadTSOPPackage
■ETOX™VIII(0.13µm)Flash
Technology
—16,32Mbit
■ETOX™VII(0.18µm)FlashTechnology
—16,32,64Mbit
■ETOX™VI(0.25µm) FlashTechnology
—8,16and32Mbit
OrderNumber:290645-016
May2003
Notice:Thisspecificationissubjecttochangewithoutnotice.VerifywithyourlocalIntelsales
officethatyouhavethelatestdatasheetbeforefinalizingadesign.
2Datasheet
INFORMATIONINTHISDOCUMENTISPROVIDEDINCONNECTIONWITHINTELPRODUCTS.NOLICENSE,EXPRESSORIMPLIED,BY
ESTOPPELOROTHERWISE,TOANYINTELLECTUALPROPERTYRIGHTSISGRANTEDBYTHISDOCUMENT.EXCEPTASPROVIDEDIN
INTEL'STERMSANDCONDITIONSOFSALEFORSUCHPRODUCTS,INTELASSUMESNOLIABILITYWHATSOEVER,ANDINTELDISCLAIMS
ANYEXPRESSORIMPLIEDWARRANTY,RELATINGTOSALEAND/ORUSEOFINTELPRODUCTSINCLUDINGLIABILITYORWARRANTIES
RELATINGTOFITNESSFORAPARTICULARPURPOSE,MERCHANTABILITY,ORINFRINGEMENTOFANYPATENT,COPYRIGHTOROTHER
INTELLECTUALPROPERTYRIGHT.Intelproductsarenotintendedforuseinmedical,lifesaving,orlifesustainingapplications.
Intelmaymakechangestospecificationsandproductdescriptionsatanytime,withoutnotice.
Designersmustnotrelyontheabsenceorcharacteristicsofanyfeaturesorinstructionsmarked"reserved"or"undefined."Intelreservesthesefor
futuredefinitionandshallhavenoresponsibilitywhatsoeverforconflictsorincompatibilitiesarisingfromfuturechangestothem.
The28F800C3,28F160C3,28F320C3,28F640C3maycontaindesigndefectsorerrorsknownaserratawhichmaycausetheproducttodeviatefrom
publishedspecifications.Currentcharacterizederrataareavailableonrequest.
ContactyourlocalIntelsalesofficeoryourdistributortoobtainthelatestspecificationsandbeforeplacingyourproductorder.
Copiesofdocumentswhichhaveanorderingnumberandarereferencedinthisdocument,orotherIntelliteraturemaybeobtainedbycalling1-800-
548-4725orbyvisitingIntel'swebsiteathttp://www.intel.com.
Copyright©IntelCorporation,2003
*Third-partybrandsandnamesarethepropertyoftheirrespectiveowners.
Datasheet 3
Contents
Contents
1.0 Introduction....................................................................................................................................7
1.1 DocumentPurpose...............................................................................................................7
1.2 Nomenclature .......................................................................................................................7
1.3 Conventions..........................................................................................................................7
2.0 DeviceDescription ........................................................................................................................8
2.1 ProductOverview .................................................................................................................8
2.2 BalloutDiagram ....................................................................................................................8
2.3 SignalDescriptions.............................................................................................................13
2.4 BlockDiagram ....................................................................................................................14
2.5 MemoryMap.......................................................................................................................15
3.0 DeviceOperations.......................................................................................................................17
3.1 BusOperations...................................................................................................................17
3.1.1 Read ......................................................................................................................17
3.1.2 Write ......................................................................................................................17
3.1.3 OutputDisable.......................................................................................................17
3.1.4 Standby..................................................................................................................18
3.1.5 Reset .....................................................................................................................18
4.0 ModesofOperation.....................................................................................................................19
4.1 ReadMode.........................................................................................................................19
4.1.1 ReadArray.............................................................................................................19
4.1.2 ReadIdentifier .......................................................................................................19
4.1.3 CFIQuery ..............................................................................................................20
4.1.4 ReadStatusRegister.............................................................................................20
4.1.4.1 ClearStatusRegister.............................................................................21
4.2 ProgramMode....................................................................................................................21
4.2.1 12-VoltProductionProgramming...........................................................................21
4.2.2 SuspendingandResumingProgram.....................................................................22
4.3 EraseMode ........................................................................................................................22
4.3.1 SuspendingandResumingErase .........................................................................23
5.0 SecurityModes............................................................................................................................28
5.1 FlexibleBlockLocking ........................................................................................................28
5.1.1 LockingOperation..................................................................................................29
5.1.1.1 LockedState..........................................................................................29
5.1.1.2 UnlockedState.......................................................................................29
5.1.1.3 Lock-DownState....................................................................................29
5.2 ReadingBlock-LockStatus.................................................................................................29
5.3 LockingOperationsduringEraseSuspend ........................................................................30
5.4 StatusRegisterErrorChecking ..........................................................................................30
5.5 128-BitProtectionRegister.................................................................................................30
5.5.1 ReadingtheProtectionRegister............................................................................31
5.5.2 ProgrammingtheProtectionRegister....................................................................31
5.5.3 LockingtheProtectionRegister.............................................................................31
5.6 VPPProgramandEraseVoltages ......................................................................................31
Contents
4Datasheet
5.6.1 ProgramProtection................................................................................................32
6.0 PowerConsumption....................................................................................................................33
6.1 ActivePower(Program/Erase/Read)..................................................................................33
6.2 AutomaticPowerSavings(APS)........................................................................................33
6.3 StandbyPower ...................................................................................................................33
6.4 DeepPower-DownMode....................................................................................................33
6.5 PowerandResetConsiderations.......................................................................................34
6.5.1 Power-Up/DownCharacteristics............................................................................34
6.5.2 RP#ConnectedtoSystemReset..........................................................................34
6.5.3 VCC,VPPandRP#Transitions ............................................................................34
6.6 PowerSupplyDecoupling...................................................................................................35
7.0 ThermalandDCCharacteristics................................................................................................35
7.1 AbsoluteMaximumRatings................................................................................................35
7.2 OperatingConditions..........................................................................................................36
7.3 DCCurrentCharacteristics.................................................................................................36
7.4 DCVoltageCharacteristics.................................................................................................39
8.0 ACCharacteristics ......................................................................................................................40
8.1 ACReadCharacteristics ....................................................................................................40
8.2 ACWriteCharacteristics.....................................................................................................44
8.3 EraseandProgramTimings...............................................................................................48
8.4 ResetSpecifications...........................................................................................................49
8.5 ACI/OTestConditions.......................................................................................................50
8.6 DeviceCapacitance............................................................................................................50
AppendixAWriteStateMachineStates.............................................................................................51
AppendixBFlowCharts......................................................................................................................53
AppendixCCommonFlashInterface.................................................................................................59
AppendixDMechanicalSpecifications..............................................................................................65
AppendixEAdditionalInformation ....................................................................................................68
AppendixFOrderingInformation.......................................................................................................69
Datasheet 5
Contents
RevisionHistory
Dateof
Revision Version Description
05/12/98 -001 Originalversion
07/21/98 -002
48-LeadTSOPpackagediagramchange
µBGApackagediagramschange
32-Mbitorderinginformationchange(Section6)
CFIQueryStructureOutputTableChange(TableC2)
CFIPrimary-VendorSpecificExtendedQueryTableChangeforOptional
FeaturesandCommandSupportchange(TableC8)
ProtectionRegisterAddressChange
IPPDtestconditionsclarification(Section4.3)
µBGApackagetopsidemarkinformationclarification(Section6)
10/03/98 -003
Byte-WideProtectionRegisterAddresschange
VIHSpecificationchange(Section4.3)
VILMaximumSpecificationchange(Section4.3)
ICCStestconditionsclarification(Section4.3)
AddedCommandSequenceErrorNote(Table7)
Datasheetrenamedfrom3VoltAdvancedBootBlock,8-,16-,32-MbitFlash
MemoryFamily.
12/04/98 -004 AddedtBHWH/tBHEHandtQVBL(Section4.6)
ProgrammingtheProtectionRegisterclarification(Section3.4.2)
12/31/98 -005 Removedallreferencestox8configurations
02/24/99 -006 Removedreferenceto40-LeadTSOPfromfrontpage
06/10/99 -007
AddedEasyBGApackage(Section1.2)
Removed1.8VI/Oreferences
LockingOperationsFlowchartchanged(AppendixB)
AddedtWHGL(Section4.6)
CFIPrimaryVendor-SpecificExtendedQuerychanged(AppendixC)
03/20/00 -008 MaxICCDchangedto25µA
Table10,addednoteindicatingVCCMax=3.3Vfor32-Mbitdevice
04/24/00 -009 Addedspecificationsfor0.18micronproductofferingsthroughoutdocument
Added64-Mbitdensity
10/12/00 -010
Changedreferencesof32Mbit80nsdevicesto70nsdevicestoreflectthe
fasterproductoffering.
ChangedVccMax=3.3Vreferencetoindicatethattheaffectedproductisthe
0.25µm32Mbitdevice.
Minortexteditsthroughoutdocument.
7/20/01 -011
Added1.8vI/Ooperationdocumentationwhereapplicable
AddedTSOPPCN‘Pin-1’indicatorinformation
Changedreferencesin8x8BGApinoutdiagramsfrom‘GND’to‘Vssq’
Added‘Vssq’toPinDescriptionsInformation
Removed0.4µmreferencesinDCcharacteristicstable
Corrected64MbpackageOrderingInformationfrom48-uBGAto48-VFBGA
Corrected‘bottom’parameterblocksizestoon8Mbdeviceto8x4KWords
Minortexteditsthroughoutdocument
10/02/01 -012 Addedspecificationsfor0.13micronproductofferingsthroughoutdocument
Contents
6Datasheet
2/05/02 -013 CorrectedIccw/Ippw/Icces/Ippesvalues.
Addedmechanicalsfor16Mband64Mb
Minortexteditsthroughoutdocument.
4/05/02 -014
Updated64Mbproductofferings.
Updated16Mbproductofferings.
RevisedandcorrectedDCCharacteristicsTable.
AddedmechanicalsforEasyBGA.
Minortexteditsthroughoutdocument.
3/06/03 -016 Completetechnicalupdate.
Dateof
Revision Version Description
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 7
1.0 Introduction
1.1 DocumentPurpose
ThisdatasheetcontainsthespecificationsfortheIntel®Advanced+BootBlockFlashMemory
(C3)devicefamily.Theseflashmemoriesaddfeaturessuchasinstantblocklockingandprotection
registersthatcanbeusedtoenhancethesecurityofsystems.
1.2 Nomenclature
0x Hexadecimalprefix
0b Binaryprefix
Byte 8bits
Word 16bits
Kword 1024words
Mword 1,048,576words
Kb 1024bits
KB 1024bytes
Mb 1,048,576bits
MB 1,048,576bytes
APS AutomaticPowerSavings
CUI CommandUserInterface
OTP OneTimeProgrammable
PR ProtectionRegister
PRD ProtectionRegisterData
PLR ProtectionLockRegister
RFU ReservedforFutureUse
SR StatusRegister
SRD StatusRegisterData
WSM WriteStateMachine
1.3 Conventions
Thetermspinandsignalareoftenusedinterchangeablytorefertotheexternalsignalconnections
onthepackage.(ballisthetermusedforCSP).
GroupMembershipBrackets:Squarebracketswillbeusedtodesignategroupmembershiporto
defineagroupofsignalswithsimilarfunction(i.e.A[21:1],SR[4:1])
Set:Whenreferringtoregisters,thetermsetmeansthebitisalogical1.
Clear:Whenreferringtoregisters,thetermclearmeansthebitisalogical0.
Block:Agroupofbits(orwords)thaterasesimultaneouslywithoneblockeraseinstruction.
MainBlock:Ablockthatcontains32Kwords.
ParameterBlock:Ablockthatcontains4Kwords.
Intel£Advanced+BootBlockFlashMemory(C3)
8Datasheet
2.0 DeviceDescription
ThissectionprovidesanoverviewoftheIntel®Advanced+BootBlockFlashMemory(C3)device
features,packaging,signalnaming,anddevicearchitecture.
2.1 ProductOverview
TheC3deviceprovideshigh-performanceasynchronousreadsinpackage-compatibledensities
witha16bitdatabus.Individually-erasablememoryblocksareoptimallysizedforcodeanddata
storage.Eight4Kwordparameterblocksarelocatedinthebootblockateitherthetoporbottomof
thedevice’smemorymap.Therestofthememoryarrayisgroupedinto32Kwordmainblocks.
Thedevicesupportsread-arraymodeoperationsatvariousI/Ovoltages(1.8Vand3V)anderase
andprogramoperationsat3Vor12VVPP.Withthe3VI/Ooption,VCCandVPPcanbetied
togetherforasimple,ultra-low-powerdesign.InadditiontoI/Ovoltageflexibility,thededicated
VPPinputprovidescompletedataprotectionwhenVPP≤VPPLK.
Thedevicefeaturesa128-bitprotectionregisterenablingsecuritytechniquesanddataprotection
schemesthroughacombinationoffactory-programmedanduser-programmableOTPdata
registers.Zero-latencylocking/unlockingonanymemoryblockprovidesinstantandcomplete
protectionforcriticalsystemcodeanddata.Additionalblocklock-downcapabilityprovides
hardwareprotectionwheresoftwarecommandsalonecannotchangetheblock’sprotectionstatus.
AcommandUserInterface(CUI)servesastheinterfacebetweenthesystemprocessorandinternal
operationofthedevice.AvalidcommandsequenceissuedtotheCUIinitiatesdeviceautomation.
AninternalWriteStateMachine(WSM)automaticallyexecutesthealgorithmsandtimings
necessaryforblockerase,program,andlock-bitconfigurationoperations.
Thedeviceoffersthreelow-powersavingfeatures:AutomaticPowerSavings(APS),standby
mode,anddeeppower-downmode.ThedeviceautomaticallyentersAPSmodefollowingread
cyclecompletion.Standbymodebeginswhenthesystemdeselectstheflashmemoryby
deassertingCE#.Thedeeppower-downmodebeginswhenRP#isasserted,whichdeselectsthe
memoryandplacestheoutputsinahigh-impedancestate,producingultra-lowpowersavings.
Combined,thesethreepower-savingsfeaturessignificantlyenhancedpowerconsumption
flexibility.
2.2 BalloutDiagram
TheC3deviceisavailablein48-leadTSOP,48-ballVFBGA,48-ballµBGA,andEasyBGA
packages.(RefertoFigure1onpage 9,Figure3onpage 11,andFigure4onpage 12,
respectively.)
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 9
NOTES:
1. Forlowerdensities,upperaddressshouldbetreatedasNC.Forexample,a16-MbitdevicewillhaveNCon
Pins9and10.
Figure1.48-LeadTSOPPackage
Advanced+BootBlock
48-LeadTSOP
12mmx20mm
TOPVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
21
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32M
16M
64M
Intel£Advanced+BootBlockFlashMemory(C3)
10 Datasheet
Figure2.MarkforPin-1indicatoron48-Lead8Mb,16Mband32MbTSOP
Note: Thetopsidemarkingon8Mb,16Mb,and32MbIntel£AdvancedandAdvanced+BootBlock
48LTSOPproductswillconverttoawhiteinktriangleasaPin1indicator.Productswithoutthe
whitetrianglewillcontinuetouseadimpleasaPin1indicator.Therearenootherchangesin
packagesize,materials,functionality,customerhandling,ormanufacturability.Productwill
continuetomeetIntelstringentqualityrequirements.ProductsaffectedareIntelOrderingCodes
showninTable1.
Table1. 48-LeadTSOP
Extended64Mbit Extended32Mbit Extended16Mbit Extended8Mbit
TE28F640C3TC80
TE28F640C3BC80 TE28F320C3TD70
TE28F320C3BD70 TE28F160C3TD70
TE28F160C3BD70 TE28F800C3TA90
TE28F800C3BA90
TE28F320C3TC70
TE28F320C3BC70 TE28F160C3TC80
TE28F160C3BC80 TE28F800C3TA110
TE28F800C3BA110
TE28F320C3TC90
TE28F320C3BC90 TE28F160C3TA90
TE28F160C3BA90
TE28F320C3TA100
TE28F320C3BA100 TE28F160C3TA110
TE28F160C3BA110
TE28F320C3TA110
TE28F320C3BA110
CurrentMark:
NewMark:
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 11
NOTES:
1. Shadedconnectionsindicatetheupgradeaddressconnections.Routingisnotrecommendedinthisarea.
2. A19denotes16Mbit;A20denotes32Mbit;A21denotes64Mbit.
3. Unusedaddressballsarenotpopulated.
Figure3.48-BallµBGA*and48-BallVeryFinePitchBGA(VFBGA)ChipSizePackage
(TopView,BallDown)1,2,3
13254768
A
B
C
D
E
F
A13
A14
A15
A16
VCCQ
A11
A10
A12
D14
D15
A8
WE#
A9
D5
D6
VPP
RP#
A21
D11
D12
WP#
A18
A20
D2
D3
A19
A17
A6
D8
D9
A7
A5
A3
CE#
D0
A4
A2
A1
A0
GND
GND D7 D13 D4 VCC D10 D1 OE#
16M
32M64M
Intel£Advanced+BootBlockFlashMemory(C3)
12 Datasheet
Figure4.64-BallEasyBGAPackage1,2
NOTES:
1. A19denotes16Mbit;A20denotes32Mbit;A21denotes64Mbit.
2. Unusedaddressballsarenotpopulated.
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
TopView
-BallSide BottomView-BallSide
A
1
A
6
A
18
V
PP V
CC
GND A
10
A
15
A
2
A
17
A
19
(1)
RP# DU
A
20
(1)
A
11
A
14
A
3
A
7
WP# WE# DU
A
21
(1)
A
12
A
13
A
4
A
5
DU
DQ8
DQ1
DQ9
DQ3
DQ12
DQ6
DU DU
CE# DQ0
DQ10
DQ
11
DQ5
DQ14
DU DU
A
0
V
SSQ DQ2
DQ4
DQ13
DQ15
VSSQ
A
16
A
22
(2)
OE# V
CCQ V
CC
V
SSQ DQ7
V
CCQ DU
DU
DU
DU
A
8
A
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
A
15
A
10
GND V
CC
V
PP A
18
A
6
A
1
A
14
A
11
A
20
(1)
DU RP# A
19
(1)
A
17
A
2
A
13
A
12
A
21
(1)
DU WE# WP# A
7
A
3
A
9
A
8
DU
DU DU DQ6
DQ12
DQ3
DQ9
DQ1
DQ8
DU DU DQ
14
DQ5
DQ11
DQ10
DQ0
CE#
A
16
VSSQ
D
15
D
13
DQ4
DQ2
V
SSQ A
0
DU
V
CCQ D
7
V
SSQ V
CC
V
CCQ OE# A
22
(2)
DU DU DU
A
5
A
4
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 13
2.3 SignalDescriptions
Table2liststheactivesignalsusedandprovidesabriefdescriptionofeach.
Table2. SignalDescriptions
Symbol Type NameandFunction
A[MAX:0]INPUT
ADDRESSINPUTSformemoryaddresses.Addressareinternallylatchedduringaprogramorerase
cycle.
8Mbit:AMAX=A18
16Mbit:AMAX=A19
32Mbit:AMAX=A20
64Mbit:AMAX=A21
DQ[15:0] INPUT/
OUTPUT
DATAINPUTS/OUTPUTS:Inputsdataandcommandsduringawritecycle;outputsdataduringread
cycles.InputscommandstotheCommandUserInterfacewhenCE#andWE#areactive.Datais
internallylatched.Thedatapinsfloattotri-statewhenthechipisde-selectedortheoutputsare
disabled.
CE# INPUT CHIPENABLE:Active-lowinput.Activatestheinternalcontrollogic,inputbuffers,decodersandsense
amplifiers.CE#isactivelow.CE#highde-selectsthememorydeviceandreducespowerconsumption
tostandbylevels.
OE# INPUT OUTPUTENABLE:Active-lowinput.Enablesthedevice’soutputsthroughthedatabuffersduringa
Readoperation.
RP# INPUT
RESET/DEEPPOWER-DOWN:Active-lowinput.
WhenRP#isatlogiclow,thedeviceisinreset/deeppower-downmode,whichdrivestheoutputsto
High-Z,resetstheWriteStateMachine,andminimizescurrentlevels(ICCD).
WhenRP#isatlogichigh,thedeviceisinstandardoperation.WhenRP#transitionsfromlogic-lowto
logic-high,thedeviceresetsallblockstolockedanddefaultstothereadarraymode.
WE# INPUT WRITEENABLE:Active-lowinput.WE#controlswritestothedevice.Addressanddataarelatchedon
therisingedgeoftheWE#pulse.
WP# INPUT
WRITEPROTECT:Active-lowinput.
WhenWP#isalogiclow,thelock-downmechanismisenabledandblocksmarkedlock-downcannot
beunlockedthroughsoftware.
WhenWP#islogichigh,thelock-downmechanismisdisabledandblockspreviouslylocked-downare
nowlockedandcanbeunlockedandlockedthroughsoftware.AfterWP#goeslow,anyblocks
previouslymarkedlock-downreverttothelock-downstate.
SeeSection5.0,“SecurityModes”onpage 28fordetailsonblocklocking.
VPP INPUT/
POWER
PROGRAM/ERASEPOWERSUPPLY:Operatesasaninputatlogiclevelstocontrolcompletedevice
protection.SuppliespowerforacceleratedProgramandEraseoperationsin12 V
±5%range.Thispin
cannotbeleftfloating.
LowerVPP
≤VPPLKtoprotectallcontentsagainstProgramandErasecommands.
SetVPP = VCCforin-systemRead,ProgramandEraseoperations.Inthisconfiguration,VPPcan
dropaslowas1.65 Vtoallowforresistorordiodedropfromthesystemsupply.
ApplyVPPto12V
±5%forfasterprogramanderaseinaproductionenvironment.Applying12 V±5%
toVPPcanonlybedoneforamaximumof1000cyclesonthemainblocksand2500cyclesonthe
bootblocks.VPPmaybeconnectedto12 Vforatotalof80hoursmaximum.SeeSection5.6for
detailsonVPPvoltageconfigurations.
VCC POWER DEVICECOREPOWERSUPPLY:Suppliespowerfordeviceoperations.
VCCQ POWER OUTPUTPOWERSUPPLY:Output-drivensourcevoltage.ThisballcanbetieddirectlytoVCCif
operatingwithinVCC
range.
GND POWER GROUND:Forallinternalcircuitry.Allgroundinputsmustbeconnected.
DU - DON’TUSE:Donotusethisball.Thisballshouldnotbeconnectedtoanypowersupplies,signalsor
otherballs,andmustbeleftfloating.
NC - NOCONNECT:Pinmustbeleftfloating.
Intel£Advanced+BootBlockFlashMemory(C3)
14 Datasheet
2.4 BlockDiagram
Output
Multiplexer
4-KWord
ParameterBlock
32-KWord
MainBlock
32-KWord
MainBlock
4-KWord
ParameterBlock
Y-Gating/Sensing WriteState
Machine Program/Erase
VoltageSwitch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/OLogic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
InputBuffer
OutputBuffer
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
Command
User
Interface
InputBuffer
DQ
0
-DQ
15
V
CCQ
WP#
A[MAX:MIN]
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 15
2.5 MemoryMap
TheC3deviceisasymmetricallyblocked,whichenablessystemcodeanddataintegrationwithina
singleflashdevice.Thebulkofthearrayisdividedinto32Kwordmainblocksthatcanstorecode
ordata,and4Kwordbootblockstofacilitatestorageofbootcodeorforfrequentlychangingsmall
parameters.SeeTable 3,“TopBootMemoryMap”onpage 15andTable 4,“BottomBootMemory
Map”onpage 16fordetails.
Table3. TopBootMemoryMap
Size
(KW) Blk 8-Mbit
Memory
Addressing
(HEX)
Size
(KW) Blk 16-Mbit
Memory
Addressing
(HEX)
Size
(KW) Blk 32-Mbit
Memory
Addressing
(HEX)
Size
(KW) Blk 64-MbitMemory
Addressing
(HEX)
422 7F000-
7FFFF 4 38 FF000-FFFFF 4701FF000-
1FFFFF 4 134 3FF000-3FFFFF
421 7E000-
7EFFF 4 37 FE000-FEFFF 4691FE000-
1FEFFF 4 133 3FE000-3FEFFF
420 7D000-
7DFFF 4 36 FD000-FDFFF 4681FD000-
1FDFFF 4 132 3FD000-3FDFFF
419 7C000-
7CFFF 4 35 FC000-FCFFF 4671FC000-
1FCFFF 4 131 3FC000-3FCFFF
418 7B000-
7BFFF 4 34 FB000-FBFFF 4661FB000-
1FBFFF 4 130 3FB000-3FBFFF
417 7A000-
7AFFF 4 33 FA000-FAFFF 465 1FA000-
1FAFFF 4 129 3FA000-3FAFFF
4 16 79000-79FFF 4 32 F9000-F9FFF 464 1F9000-
1F9FFF 4 128 3F9000-3F9FFF
4 15 78000-78FFF 4 31 F8000-F8FFF 463 1F8000-
1F8FFF 4 127 3F8000-3F8FFF
32 14 70000-77FFF 32 30 F0000-F7FFF 32 62 1F0000-
1F7FFF 32 126 3F0000-3F7FFF
32 13 68000-6FFFF 32 29 E8000-EFFFF 32 61 1E8000-
1EFFFF 32 125 3E8000-3EFFFF
32 12 60000-67FFF 32 28 E0000-E7FFF 32 60 1E0000-
1E7FFF 32 124 3E0000-3E7FFF
32 11 58000-5FFFF 32 27 D8000-DFFFF 32 59 1D8000-
1DFFFF 32 123 3D8000-3DFFFF
... ... ... ... ... ... ... ... ... ... ... ...
32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF
32 1 8000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF
32 0 0000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF
Intel£Advanced+BootBlockFlashMemory(C3)
16 Datasheet
Table4. BottomBootMemoryMap
Size
(KW) Blk 8-Mbit
Memory
Addressing
(HEX)
Size
(KW) Blk 16-Mbit
Memory
Addressing
(HEX)
Size
(KW) Blk 32-Mbit
Memory
Addressing
(HEX)
Size
(KW) Blk 64-MbitMemory
Addressing
(HEX)
32 22 78000-7FFFF 32 38 F8000-FFFFF 32 70 1F8000-1FFFFF 32 134 3F8000-3FFFFF
32 21 70000-77FFF 32 37 F0000-F7FFF 32 69 1F0000-1F7FFF 32 133 3F0000-3F7FFF
32 20 68000-6FFFF 32 36 E8000-EFFFF 32 68 1E8000-1EFFFF 32 132 3E8000-3EFFFF
32 19 60000-67FFF 32 35 E0000-E7FFF 32 67 1E0000-1E7FFF 32 131 3E0000-3E7FFF
... ... ... ... ... ... ... ... ... . ... ...
32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF
32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF
32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF
4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF
4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF
4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF
4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF
4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF
4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF
4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF
4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 17
3.0 DeviceOperations
TheC3deviceusesaCUIandautomatedalgorithmstosimplifyProgramandEraseoperations.
TheCUIallowsfor100%CMOS-levelcontrolinputsandfixedpowersuppliesduringerasureand
programming.
TheinternalWSMcompletelyautomatesProgramandEraseoperationswhiletheCUIsignalsthe
startofanoperationandthestatusregisterreportsdevicestatus.TheCUIhandlestheWE#
interfacetothedataandaddresslatches,aswellassystemstatusrequestsduringWSMoperation.
3.1 BusOperations
TheC3deviceperformsread,program,anderaseoperationsin-systemviathelocalCPUor
microcontroller.Fourcontrolpins(CE#,OE#,WE#,andRP#)managethedataflowinandoutof
theflashdevice.Table5onpage 17summarizesthesebusoperations.
3.1.1 Read
Whenperformingareadcycle,CE#andOE#mustbeasserted;WE#andRP#mustbedeasserted.
CE#isthedeviceselectioncontrol;whenactivelow,itenablestheflashmemorydevice.OE#is
thedataoutputcontrol;whenlow,dataisoutputonDQ[15:0].SeeFigure8,“ReadOperation
Waveform”onpage 43.
3.1.2 Write
AwritecycleoccurswhenbothCE#andWE#arelow;RP#andOE#arehigh.Commandsare
issuedtotheCommandUserInterface(CUI).TheCUIdoesnotoccupyanaddressablememory
location.AddressanddataarelatchedontherisingedgeoftheWE#orCE#pulse,whichever
occursfirst.SeeFigure9,“WriteOperationsWaveform”onpage 48.
3.1.3 OutputDisable
WithOE#atalogic-highlevel(VIH),thedeviceoutputsaredisabled.DQ[15:0]areplacedina
high-impedancestate.
Table5. BusOperations
Mode RP# CE# OE# WE# DQ[15:0]
Read VIH VIL VIL VIH DOUT
Write VIH VIL VIH VIL DIN
OutputDisable VIH VIL VIH VIH High-Z
Standby VIH VIH X X High-Z
Reset VIL XXXHigh-Z
NOTE: X=Don’tCare(VILorVIH)
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3.1.4 Standby
DeselectingthedevicebybringingCE#toalogic-highlevel(VIH)placesthedeviceinstandby
mode,whichsubstantiallyreducesdevicepowerconsumptionwithoutanylatencyforsubsequent
readaccesses.Instandby,outputsareplacedinahigh-impedancestateindependentofOE#.If
deselectedduringaProgramorEraseoperation,thedevicecontinuestoconsumeactivepower
untiltheProgramorEraseoperationiscomplete.
3.1.5 Reset
Fromreadmode,RP#atVILfortimetPLPHdeselectsthememory,placesoutputdriversinahigh-
impedancestate,andturnsoffallinternalcircuits.Afterreturnfromreset,atimetPHQVisrequired
untiltheinitialread-accessoutputsarevalid.Adelay(tPHWLortPHEL)isrequiredafterreturnfrom
resetbeforeawritecyclecanbeinitiated.Afterthiswake-upinterval,normaloperationisrestored.
TheCUIresetstoread-arraymode,thestatusregisterissetto0x80,andallblocksarelocked.See
Figure10,“ResetOperationsWaveforms”onpage 49.
IfRP#istakenlowfortimetPLPHduringaProgramorEraseoperation,theoperationwillbe
abortedandthememorycontentsattheabortedlocation(foraprogram)orblock(foranerase)are
nolongervalid,sincethedatamaybepartiallyerasedorwritten.Theabortprocessgoesthrough
thefollowingsequence:
1.WhenRP#goeslow,thedeviceshutsdowntheoperationinprogress,aprocesswhichtakestime
tPLRHtocomplete.
2.AftertimetPLRH,thepartwilleitherresettoread-arraymode(ifRP#isassertedduringtPLRH)or
enterresetmode(ifRP#isdeassertedaftertPLRH).SeeFigure10,“ResetOperationsWaveforms”
onpage 49.
Inbothcases,afterreturningfromanabortedoperation,therelevanttimetPHQVortPHWL/tPHEL
mustbeobservedbeforeaReadorWriteoperationisinitiated,asdiscussedintheprevious
paragraph.However,inthiscase,thesedelaysarereferencedtotheendoftPLRHratherthanwhen
RP#goeshigh.
Aswithanyautomateddevice,itisimportanttoassertRP#duringasystemreset.Whenthesystem
comesoutofreset,theprocessorexpectstoreadfromtheflashmemory.Automatedflash
memoriesprovidestatusinformationwhenreadduringprogramorBlock-Eraseoperations.Ifa
CPUresetoccurswithnoflashmemoryreset,properCPUinitializationmaynotoccurbecausethe
flashmemorymaybeprovidingstatusinformationinsteadofarraydata.Intel®Flashmemories
allowproperCPUinitializationfollowingasystemresetthroughtheuseoftheRP#input.Inthis
application,RP#iscontrolledbythesameRESET#signalthatresetsthesystemCPU.
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4.0 ModesofOperation
4.1 ReadMode
Theflashmemoryhasfourreadmodes(readarray,readidentifier,readstatus,andCFIquery),and
twowritemodes(programanderase).Threeadditionalmodes(erasesuspendtoprogram,erase
suspendtoread,andprogramsuspendtoread)areavailableonlyduringsuspendedoperations.
Table 7,“CommandBusOperations”onpage 24andTable 8,“CommandCodesand
Descriptions”onpage 25summarizethecommandsusedtoreachthesemodes.AppendixA,
“WriteStateMachineStates”onpage 51isacomprehensivechartshowingthestatetransitions.
4.1.1 ReadArray
WhenRP#transitionsfromVIL(reset)toVIH,thedevicedefaultstoread-arraymodeandwill
respondtotheread-controlinputs(CE#,addressinputs,andOE#)withoutanyadditionalCUI
commands.
Whenthedeviceisinreadarraymode,fourcontrolsignalscontroldataoutput.
•WE#mustbelogichigh(VIH)
•CE#mustbelogiclow(VIL)
•OE#mustbelogiclow(VIL)
•RP#mustbelogichigh(VIH)
Inaddition,theaddressofthedesiredlocationmustbeappliedtotheaddresspins.Ifthedeviceis
notinread-arraymode,aswouldbethecaseafteraProgramorEraseoperation,theReadArray
command(0xFF)mustbeissuedtotheCUIbeforearrayreadscanoccur.
4.1.2 ReadIdentifier
Theread-identifiermodeoutputsthreetypesofinformation:themanufacturer/deviceidentifier,the
blocklockingstatus,andtheprotectionregister.Thedeviceisswitchedtothismodebyissuingthe
ReadIdentifiercommand(0x90).Onceinthismode,readcyclesfromaddressesshowninTable6
retrievethespecifiedinformation.Toreturntoread-arraymode,issuetheReadArraycommand
(0xFF).
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4.1.3 CFIQuery
TheCFIquerymodeoutputsCommonFlashInterface(CFI)dataafterissuingtheReadQuery
Command(0x98).TheCFIdatastructurecontainsinformationsuchasblocksize,density,
commandset,andelectricalspecifications.Onceinthismode,readcyclesfromaddressesshownin
AppendixC,“CommonFlashInterface,”retrievethespecifiedinformation.Toreturntoread-array
mode,issuetheReadArraycommand(0xFF).
4.1.4 ReadStatusRegister
Thestatusregisterindicatesthestatusofdeviceoperations,andthesuccess/failureofthat
operation.TheReadStatusRegister(0x70)commandcausessubsequentreadstooutputdatafrom
thestatusregisteruntilanothercommandisissued.Toreturntoreadingfromthearray,issuea
ReadArray(0xFF)command.
Thestatus-registerbitsareoutputonDQ[7:0].Theupperbyte,DQ[15:8],outputs0x00whena
ReadStatusRegistercommandisissued.
Table6. DeviceIdentificationCodes
Item Address1
Data Description
Base Offset
ManufacturerID Block 0x00 0x0089
DeviceID Block 0x01
0x88C0 8-MbitTopBootDevice
0x88C1 8-MbitBottomBootDevice
0x88C2 16-MbitTopBootDevice
0x88C3 16-MbitBottomBootDevice
0x88C4 32-MbitTopBootDevice
0x88C5 32-MbitBottomBootDevice
0x88CC 64-MbitTopBootDevice
0x88CD 64-MbitBottomBootDevice
BlockLockStatus2Block 0x02 DQ0=0b0 Blockisunlocked
DQ0=0b1 Blockislocked
BlockLock-DownStatus2Block 0x02 DQ1=0b0 Blockisnotlocked-down
DQ1=0b1 Blockislockeddown
ProtectionRegisterLockStatus Block 0x80 LockData
ProtectionRegister Block 0x81-
0x88 RegisterData Multiplereadsrequiredtoread
theentire128-bitProtection
Register.
NOTES:
1. Theaddressisconstructedfromabaseaddressplusanoffset.Forexample,toreadtheBlockLockStatus
forblocknumber38inabottombootdevice,settheaddressto0x0F8000plusthe
offset(0x02),i.e.
0x0F8002.ThenexamineDQ0ofthedatatodetermineiftheblockislocked.
2. SeeSection5.2,“ReadingBlock-LockStatus”onpage 29forvalidlockstatus.
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ThecontentsofthestatusregisterarelatchedonthefallingedgeofOE#orCE#(whicheveroccurs
last)whichpreventspossiblebuserrorsthatmightoccurifStatusRegistercontentschangewhile
beingread.CE#orOE#mustbetoggledwitheachsubsequentstatusread,ortheStatusRegister
willnotindicatecompletionofaProgramorEraseoperation.
WhentheWSMisactive,SR[7]willindicatethestatusoftheWSM;theremainingbitsinthe
statusregisterindicatewhethertheWSMwassuccessfulinperformingthepreferredoperation(see
Table 9,“StatusRegisterBitDefinition”onpage 27).
4.1.4.1 ClearStatusRegister
TheWSMcansetStatusRegisterbits1through7andcanclearbits2,6,and7;but,theWSM
cannotclearStatusRegisterbits1,3,4or5.Becausebits1,3,4,and5indicatevariouserror
conditions,thesebitscanbeclearedonlythroughtheClearStatusRegister(0x50)command.By
allowingthesystemsoftwaretocontroltheresettingofthesebits,severaloperationsmaybe
performed(suchascumulativelyprogrammingseveraladdressesorerasingmultipleblocksin
sequence)beforereadingthestatusregistertodetermineifanerroroccurredduringthatseries.
Clearthestatusregisterbeforebeginninganothercommandorsequence.TheReadArray
commandmustbeissuedbeforedatacanbereadfromthememoryarray.Resettingthedevicealso
clearstheStatusRegister.
4.2 ProgramMode
Programmingisexecutedusingatwo-writecyclesequence.TheProgramSetupcommand(0x40)
isissuedtotheCUIfollowedbyasecondwritewhichspecifiestheaddressanddatatobe
programmed.TheWSMwillexecuteasequenceofinternallytimedeventstoprogrampreferred
bitsoftheaddressedlocation,thenverifythebitsaresufficientlyprogrammed.Programmingthe
memoryresultsinspecificbitswithinanaddresslocationbeingchangedtoa“0.”Ifusersattempt
toprogram“1”s,thememorycellcontentsdonotchangeandnoerroroccurs.
TheStatusRegisterindicatesprogrammingstatus.Whiletheprogramsequenceexecutes,statusbit
7is“0.”ThestatusregistercanbepolledbytogglingeitherCE#orOE#.Whileprogramming,the
onlyvalidcommandsareReadStatusRegister,ProgramSuspend,andProgramResume.
Whenprogrammingiscomplete,theprogram-statusbitsshouldbechecked.Iftheprogramming
operationwasunsuccessful,bitSR[4]oftheStatusRegisterissettoindicateaprogramfailure.If
SR[3]isset,thenVPPwasnotwithinacceptablelimits,andtheWSMdidnotexecutetheprogram
command.IfSR[1]isset,aprogramoperationwasattemptedonalockedblockandtheoperation
wasaborted.
Thestatusregistershouldbeclearedbeforeattemptingthenextoperation.AnyCUIinstructioncan
followafterprogrammingiscompleted;however,topreventinadvertentstatus-registerreads,be
suretoresettheCUItoread-arraymode.
4.2.1 12-VoltProductionProgramming
WhenVPPisbetween1.65 Vand3.6 V,allprogramanderasecurrentisdrawnthroughtheVCC
pin.NotethatifVPPisdrivenbyalogicsignal,VIH min=1.65 V.Thatis,VPP
mustremainabove
1.65 Vtoperformin-systemflashmodifications.WhenVPPisconnectedtoa12 Vpowersupply,
thedevicedrawsprogramanderasecurrentdirectlyfromtheVPPpin.Thiseliminatestheneedfor
anexternalswitchingtransistortocontrolVPP.Figure7onpage 32showsexamplesofhowthe
flashpowersuppliescanbeconfiguredforvarioususagemodels.
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The12VVPPmodeenhancesprogrammingperformanceduringtheshortperiodoftimetypically
foundinmanufacturingprocesses;however,itisnotintendedforextendeduse.12 Vmaybe
appliedtoVPPduringProgramandEraseoperationsforamaximumof1000cyclesonthemain
blocksand2500cyclesontheparameterblocks.VPPmaybeconnectedto12 Vforatotalof80
hoursmaximum.Stressingthedevicebeyondtheselimitsmaycausepermanentdamage.
4.2.2 SuspendingandResumingProgram
TheProgramSuspendcommandhaltsanin-progressprogramoperationsothatdatacanberead
fromotherlocationsofmemory.Oncetheprogrammingprocessstarts,issuingtheProgram
SuspendcommandtotheCUIrequeststhattheWSMsuspendtheprogramsequenceat
predeterminedpointsintheprogramalgorithm.Thedevicecontinuestooutputstatus-registerdata
aftertheProgramSuspendcommandisissued.Pollingstatus-registerbitsSR[7]andSR[2]will
determinewhentheprogramoperationhasbeensuspended(bothwillbesetto“1”).tWHRH1/
tEHRH1specifytheprogram-suspendlatency.
ARead-ArraycommandcannowbeissuedtotheCUItoreaddatafromblocksotherthanthat
whichissuspended.TheonlyothervalidcommandswhileprogramissuspendedareReadStatus
Register,ReadIdentifier,CFIQuery,andProgramResume.
AftertheProgramResumecommandisissuedtotheflashmemory,theWSMwillcontinuewith
theprogrammingprocessandstatusregisterbitsSR[2]andSR[7]willautomaticallybecleared.
Thedeviceautomaticallyoutputsstatusregisterdatawhenread(seeFigure14,“ProgramSuspend
/ResumeFlowchart”onpage 54)aftertheProgramResumecommandisissued.VPPmustremain
atthesameVPPlevelusedforprogramwhileinprogram-suspendmode.RP#mustalsoremainat
VIH.
4.3 EraseMode
Toeraseablock,issuetheEraseSet-upandEraseConfirmcommandstotheCUI,alongwithan
addressidentifyingtheblocktobeerased.ThisaddressislatchedinternallywhentheErase
Confirmcommandisissued.Blockerasureresultsinallbitswithintheblockbeingsetto“1.”Only
oneblockcanbeerasedatatime.TheWSMwillexecuteasequenceofinternallytimedeventsto
programallbitswithintheblockto“0,”eraseallbitswithintheblockto“1,”thenverifythatall
bitswithintheblockaresufficientlyerased.Whiletheeraseexecutes,statusbit7isa“0.”
Whenthestatusregisterindicatesthaterasureiscomplete,checktheerase-statusbittoverifythat
theEraseoperationwassuccessful.IftheEraseoperationwasunsuccessful,SR[5]ofthestatus
registerwillbesettoa“1,”indicatinganerasefailure.IfVPPwasnotwithinacceptablelimitsafter
theEraseConfirmcommandwasissued,theWSMwillnotexecutetheerasesequence;instead,
SR[5]ofthestatusregisterissettoindicateaneraseerror,andSR[3]issettoa“1”toidentifythat
VPPsupplyvoltagewasnotwithinacceptablelimits.
AfteranEraseoperation,clearthestatusregister(0x50)beforeattemptingthenextoperation.Any
CUIinstructioncanfollowaftererasureiscompleted;however,topreventinadvertentstatus-
registerreads,itisadvisabletoplacetheflashinread-arraymodeaftertheeraseiscomplete.
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Datasheet 23
4.3.1 SuspendingandResumingErase
SinceanEraseoperationrequiresontheorderofsecondstocomplete,anEraseSuspendcommand
isprovidedtoallowerase-sequenceinterruptioninordertoreaddatafrom—orprogramdatato—
anotherblockinmemory.Oncetheerasesequenceisstarted,issuingtheEraseSuspendcommand
totheCUIsuspendstheerasesequenceatapredeterminedpointintheerasealgorithm.Thestatus
registerwillindicateif/whentheEraseoperationhasbeensuspended.Erase-suspendlatencyis
specifiedbytWHRH2/tEHRH2.
AReadArrayorProgramcommandcannowbeissuedtotheCUItoread/programdatafrom/to
blocksotherthanthatwhichissuspended.ThisnestedProgramcommandcansubsequentlybe
suspendedtoreadyetanotherlocation.TheonlyvalidcommandswhileEraseissuspendedare
ReadStatusRegister,ReadIdentifier,CFIQuery,ProgramSetup,ProgramResume,Erase
Resume,LockBlock,UnlockBlock,andLock-DownBlock.Duringerase-suspendmode,thechip
canbeplacedinapseudo-standbymodebytakingCE#toVIH,whichreducesactivecurrent
consumption.
EraseResumecontinuestheerasesequencewhenCE# = VIL.Similartotheendofastandard
Eraseoperation,thestatusregistershouldbereadandclearedbeforethenextinstructionisissued.
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24 Datasheet
BusoperationsaredefinedinTable 5,“BusOperations”onpage 17.
Table7. CommandBusOperations
Command Notes FirstBusCycle SecondBusCycle
Oper Addr Data Oper Addr Data
ReadArray 1,3 Write X 0xFF
ReadIdentifier 1,3 Write X 0x90 Read IA ID
CFIQuery 1,3 Write X 0x98 Read QA QD
ReadStatusRegister 1,3 Write X 0x70 Read X SRD
ClearStatusRegister 1,3 Write X 0x50
Program 2,3 Write X 0x40/
0x10 Write PA PD
BlockErase/Confirm 1,3 Write X 0x20 Write BA D0H
Program/EraseSuspend 1,3 Write X 0xB0
Program/EraseResume 1,3 Write X 0xD0
LockBlock 1,3 Write X 0x60 Write BA 0x01
UnlockBlock 1,3 Write X 0x60 Write BA 0xD0
Lock-DownBlock 1,3 Write X 0x60 Write BA 0x2F
ProtectionProgram 1,3 Write X 0xC0 Write PA PD
X="Don’tCare" PA = ProgAddr BA = BlockAddr IA =IdentifierAddr. QA = QueryAddr.
SRD = StatusReg.
Data PD = ProgData ID = IdentifierData QD = QueryData
NOTES:
1. FollowingtheReadIdentifierorCFIQuerycommands,readoperationsoutputdeviceidentificationdataor
CFIqueryinformation,respectively.SeeSection4.1.2andSection4.1.3.
2. Either0x40or0x10commandisvalid,buttheIntelstandardis0x40.
3. Whenwritingcommands,theupperdatabus[DQ8-DQ15]shouldbeeitherVILorVIH,tominimizecurrent
draw.
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Datasheet 25
Table8. CommandCodesandDescriptions
Code
(HEX) DeviceMode CommandDescription
FF ReadArray Thiscommandplacesthedeviceinread-arraymode,whichoutputsarraydataonthedata
pins.
40 ProgramSet-Up
Thisisatwo-cyclecommand.ThefirstcyclepreparestheCUIforaprogramoperation.The
secondcyclelatchesaddressesanddatainformationandinitiatestheWSMtoexecutethe
Programalgorithm.Theflashoutputsstatus-registerdatawhenCE#orOE#istoggled.ARead
Arraycommandisrequiredafterprogrammingtoreadarraydata.SeeSection4.2,“Program
Mode”onpage 21.
20 EraseSet-Up Thisisatwo-cyclecommand.PreparestheCUIfortheEraseConfirmcommand.Ifthenext
commandisnotanEraseConfirmcommand,thentheCUIwill(a)setbothSR.4andSR.5of
thestatusregistertoa“1,”(b)placethedeviceintotheread-status-registermode,and(c)wait
foranothercommand.SeeSection4.3,“EraseMode”onpage 22.
D0
EraseConfirm
Program/Erase
Resume
UnlockBlock
IfthepreviouscommandwasanEraseSet-Upcommand,thentheCUIwillclosetheaddress
anddatalatchesandbeginerasingtheblockindicatedontheaddresspins.Duringprogram/
erase,thedevicewillrespondonlytotheReadStatusRegister,ProgramSuspendandErase
Suspendcommands,andwilloutputstatus-registerdatawhenCE#orOE#istoggled.
IfaProgramorEraseoperationwaspreviouslysuspended,thiscommandwillresumethat
operation.
IfthepreviouscommandwasBlockUnlockSet-Up,theCUIwilllatchtheaddressandunlock
theblockindicatedontheaddresspins.IftheblockhadbeenpreviouslysettoLock-Down,this
operationwillhavenoeffect.(SeeSection5.1)
B0 ProgramSuspend
EraseSuspend
IssuingthiscommandwillbegintosuspendthecurrentlyexecutingProgram/Eraseoperation.
Thestatusregisterwillindicatewhentheoperationhasbeensuccessfullysuspendedby
settingeithertheprogram-suspendSR[2]orerase-suspendSR[6]andtheWSMstatusbit
SR[7]toa“1”(ready).TheWSMwillcontinuetoidleintheSUSPENDstate,regardlessofthe
stateofallinput-controlpinsexceptRP#,whichwillimmediatelyshutdowntheWSMandthe
remainderofthechipifRP#isdriventoVIL.SeeSections3.2.5.1and3.2.6.1.
70 ReadStatus
Register
Thiscommandplacesthedeviceintoread-status-registermode.Readingthedevicewill
outputthecontentsofthestatusregister,regardlessoftheaddresspresentedtothedevice.
ThedeviceautomaticallyentersthismodeafteraProgramorEraseoperationhasbeen
initiated.SeeSection4.1.4,“ReadStatusRegister”onpage 20.
50 ClearStatus
Register TheWSMcansettheblock-lockstatusSR[1],VPPStatusSR[3],programstatusSR[4],and
erase-statusSR[5]bitsinthestatusregisterto“1,”butitcannotclearthemto“0.”Issuingthis
commandclearsthosebitsto“0.”
90 Read
Identifier Putsthedeviceintotheread-identifiermodesothatreadingthedevicewilloutputthe
manufacturer/devicecodesorblock-lockstatus.SeeSection4.1.2,“ReadIdentifier”on
page 19.
60 BlockLock,Block
Unlock,Block
Lock-DownSet-
Up
PreparestheCUIforblock-lockingchanges.IfthenextcommandisnotBlockUnlock,Block
Lock,orBlockLock-Down,thentheCUIwillsetboththeprogramanderase-status-register
bitstoindicateacommand-sequenceerror.SeeSection5.0,“SecurityModes”onpage 28.
01 Lock-Block IfthepreviouscommandwasLockSet-Up,theCUIwilllatchtheaddressandlocktheblock
indicatedontheaddresspins.(SeeSection5.1)
2F Lock-Down IfthepreviouscommandwasaLock-DownSet-Upcommand,theCUIwilllatchtheaddress
andlock-downtheblockindicatedontheaddresspins.(SeeSection5.1)
98 CFI
Query PutsthedeviceintotheCFI-QuerymodesothatreadingthedevicewilloutputCommonFlash
Interfaceinformation.SeeSection4.1.3andAppendixC,“CommonFlashInterface”.
C0 Protection
Program
Set-Up
Thisisatwo-cyclecommand.ThefirstcyclepreparestheCUIforaprogramoperationtothe
protectionregister.Thesecondcyclelatchesaddressesanddatainformationandinitiatesthe
WSMtoexecutetheProtectionProgramalgorithmtotheprotectionregister.Theflashoutputs
status-registerdatawhenCE#orOE#istoggled.AReadArraycommandisrequiredafter
programmingtoreadarraydata.SeeSection5.5.
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10 Alt.ProgSet-Up OperatesthesameasProgramSet-upcommand.(See0x40/ProgramSet-Up)
00 Invalid/
Reserved Unassignedcommandsshouldnotbeused.Intelreservestherighttoredefinethesecodesfor
futurefunctions.
NOTE: SeeAppendixA,“WriteStateMachineStates”formodetransitioninformation.
Table8. CommandCodesandDescriptions
Code
(HEX) DeviceMode CommandDescription
Table9. StatusRegisterBitDefinition
WSMS ESS ES PS VPPS PSS BLS R
76543210
NOTES:
SR[7]WRITESTATEMACHINESTATUS(WSMS)
1 = Ready
0=Busy
CheckWriteStateMachinebitfirsttodetermineWordProgram
orBlockErasecompletion,beforecheckingprogramorerase-
statusbits.
SR[6] = ERASE-SUSPENDSTATUS(ESS)
1=EraseSuspended
0=EraseInProgress/Completed
WhenEraseSuspendisissued,WSMhaltsexecutionandsets
bothWSMSandESSbitsto“1.”ESSbitremainssetto“1”until
anEraseResumecommandisissued.
SR[5] = ERASESTATUS(ES)
1 = ErrorInBlockErase
0 = SuccessfulBlockErase
Whenthisbitissetto“1,”WSMhasappliedthemax.number
oferasepulsestotheblockandisstillunabletoverify
successfulblockerasure.
SR[4] = PROGRAMSTATUS(PS)
1 = ErrorinProgramming
0 = SuccessfulProgramming Whenthisbitissetto“1,”WSMhasattemptedbutfailedto
programaword/byte.
SR[3] = VPPSTATUS(VPPS)
1=V
PPLowDetect,OperationAbort
0=V
PPOK
TheVPP
statusbitdoesnotprovidecontinuousindicationof
VPP
level.TheWSMinterrogatesVPPlevelonlyafterthe
ProgramorErasecommandsequenceshavebeenentered,
andinformsthesystemifVPPhasnotbeenswitchedon.The
VPPisalsocheckedbeforetheoperationisverifiedbythe
WSM.TheVPP
statusbitisnotguaranteedtoreportaccurate
feedbackbetweenVPPLKandVPP1Min.
SR[2] = PROGRAMSUSPENDSTATUS(PSS)
1=ProgramSuspended
0=PrograminProgress/Completed
WhenProgramSuspendisissued,WSMhaltsexecutionand
setsbothWSMSandPSSbitsto“1.”PSSbitremainssetto“1”
untilaProgramResumecommandisissued.
SR[1] = BLOCKLOCKSTATUS
1=Prog/Eraseattemptedonalockedblock;Operation
aborted.
0=Nooperationtolockedblocks
IfaProgramorEraseoperationisattemptedtooneofthe
lockedblocks,thisbitissetbytheWSM.Theoperation
specifiedisabortedandthedeviceisreturnedtoreadstatus
mode.
SR[0] = RESERVEDFORFUTUREENHANCEMENTS(R) Thisbitisreservedforfutureuseandshouldbemaskedout
whenpollingthestatusregister.
NOTE: ACommand-SequenceErrorisindicatedwhenSR[4],SR[5],andSR[7]areset.
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Datasheet 27
5.0 SecurityModes
5.1 FlexibleBlockLocking
TheC3deviceoffersaninstant,individualblock-lockingschemethatallowsanyblocktobe
lockedorunlockedwithnolatency,enablinginstantcodeanddataprotection.
Thislockingschemeofferstwolevelsofprotection.Thefirstlevelallowssoftware-onlycontrolof
blocklocking(usefulfordatablocksthatchangefrequently),whilethesecondlevelrequires
hardwareinteractionbeforelockingcanbechanged(usefulforcodeblocksthatchange
infrequently).
Thefollowingsectionswilldiscusstheoperationofthelockingsystem.Theterm“state[abc]”will
beusedtospecifylockingstates;e.g.,“state[001],”wherea=valueofWP#,b = bitD1ofthe
BlockLockstatusregister,andc = bitD0oftheBlockLockstatusregister.Figure5,“Block
LockingStateDiagram”onpage 28displaysallofthepossiblelockingstates.
Figure5.BlockLockingStateDiagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down
4,5
Software
Locked
[011]
Hardware
Locked
5
Unlocked
WP#HardwareControl
Notes: 1.[a,b,c]represents[WP#,D1,D0].X=Don’tCare.
2.D1indicatesblockLock-downstatus.D1=‘0’,Lock-downhasnotbeenissuedto
thisblock.D1=‘1’,Lock-downhasbeenissuedtothisblock.
3.D0indicatesblocklockstatus.D0=‘0’,blockisunlocked.D0=‘1’,blockislocked.
4.Locked-down=Hardware+Softwarelocked.
5.[011]statesshouldbetrackedbysystemsoftwaretodeterminedifference
betweenHardwareLockedandLocked-Downstates.
SoftwareBlockLock(0x60/0x01)orSoftwareBlockUnlock(0x60/0xD0)
SoftwareBlockLock-Down(0x60/0x2F)
WP#hardwarecontrol
Intel£Advanced+BootBlockFlashMemory(C3)
28 Datasheet
5.1.1 LockingOperation
ThelockingstatusofeachblockcanbesettoLocked,Unlocked,orLock-Down,eachofwhich
willbedescribedinthefollowingsections.SeeFigure5,“BlockLockingStateDiagram”on
page 28andFigure17,“LockingOperationsFlowchart”onpage 57.
Thefollowingconciselysummarizesthelockingfunctionality.
5.1.1.1 LockedState
Thedefaultstateofallblocksuponpower-uporresetislocked(states[001]or[101]).Locked
blocksarefullyprotectedfromalteration.AnyProgramorEraseoperationsattemptedonalocked
blockwillreturnanerroronbitSR[1]oftheStatusRegister.Thestateofalockedblockcanbe
changedtoUnlockedorLockDownusingtheappropriatesoftwarecommands.AnUnlocked
blockcanbelockedbywritingtheLockcommandsequence,0x60followedby0x01.
5.1.1.2 UnlockedState
Unlockedblocks(states[000],[100],[110])canbeprogrammedorerased.Allunlockedblocks
returntotheLockedstatewhenthedeviceisresetorpowereddown.Thestatusofanunlocked
blockcanbechangedtoLockedorLockedDownusingtheappropriatesoftwarecommands.A
LockedblockcanbeunlockedbywritingtheUnlockcommandsequence,0x60followedby0xD0.
5.1.1.3 Lock-DownState
BlocksthatareLocked-Down(state[011])areprotectedfromProgramandEraseoperations(just
likeLockedblocks),buttheirprotectionstatuscannotbechangedusingsoftwarecommandsalone.
ALockedorUnlockedblockcanbeLockedDownbywritingtheLock-Downcommandsequence,
0x60followedby0x2F.Locked-DownblocksreverttotheLockedstatewhenthedeviceisresetor
powereddown.
TheLock-DownfunctiondependsontheWP#inputpin.WhenWP# = 0,blocksinLockDown
[011]areprotectedfromprogram,erase,andlockstatuschanges.WhenWP# = 1,theLock-Down
functionisdisabled([111])andLocked-Downblockscanbeindividuallyunlockedbysoftware
commandtothe[110]state,wheretheycanbeerasedandprogrammed.Theseblockscanthenbe
relocked[111]andunlocked[110]asrequiredwhileWP#remainshigh.WhenWP#goeslow,
blocksthatwerepreviouslyLockedDownreturntotheLock-Downstate[011],regardlessofany
changesmadewhileWP#washigh.Deviceresetorpower-downresetsallblocks,includingthose
inLock-Down,toLockedstate.
5.2 ReadingBlock-LockStatus
TheLockstatusofeachblockcanbereadinread-identifiermodeofthedevicebyissuingtheread-
identifiercommand(0x90).SubsequentreadsatBlockAddress+0x00002willoutputtheLock
statusofthatblock.TheLockstatusisrepresentedbyDQ0andDQ1.DQ0indicatestheBlock
Lock/UnlockstatusandissetbytheLockcommandandclearedbytheUnlockcommand.Itisalso
automaticallysetwhenenteringLockDown.DQ1indicatesLock-Downstatus,andissetbythe
Lock-Downcommand.Itcannotbeclearedbysoftware—onlybydeviceresetorpower-down.See
Table 6,“DeviceIdentificationCodes”onpage 20forblock-statusinformation.
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 29
5.3 LockingOperationsduringEraseSuspend
Changestoblock-lockstatuscanbeperformedduringanerase-suspendbyusingthestandard
lockingcommandsequencestoUnlock,Lock,orLockDownablock.Thisisusefulinthecase
whenanotherblockneedstobeupdatedwhileanEraseoperationisinprogress.
TochangeblocklockingduringanEraseoperation,firstissuetheEraseSuspendcommand(0xB0),
thencheckthestatusregisteruntilitindicatesthattheEraseoperationhasbeensuspended.Next,
writethepreferredLockcommandsequencetoablockandtheLockstatuswillbechanged.After
completinganypreferredLock,Read,orProgramoperations,resumetheEraseoperationwiththe
EraseResumecommand(0xD0).
IfablockisLockedorLockedDownduringaSuspendedEraseofthesameblock,thelocking
statusbitswillbechangedimmediately.ButwhentheEraseisresumed,theEraseoperationwill
complete.
LockingoperationscannotbeperformedduringaProgramSuspend.RefertoAppendixA,“Write
StateMachineStates”onpage 51fordetailedinformationonwhichcommandsarevalidduring
EraseSuspend.
5.4 StatusRegisterErrorChecking
Usingnested-lockingorprogram-commandsequencesduringEraseSuspendcanintroduce
ambiguityintostatusregisterresults.
Sincelockingchangesareperformedusingatwo-cyclecommandsequence,e.g.,0x60followedby
0x01tolockablock,followingtheBlockLock,BlockUnlock,orBlockLock-DownSetup
command(0x60)withaninvalidcommandwillproduceaLock-Commanderror(SR[4]andSR[5]
willbesetto1)intheStatusRegister.IfaLock-CommanderroroccursduringanEraseSuspend,
SR[4]andSR[5]willbesetto1andwillremainat1aftertheEraseisresumed.WhenEraseis
complete,anypossibleerrorduringtheErasecannotbedetectedviathestatusregisterbecauseof
thepreviousLock-Commanderror.
AsimilarsituationhappensifanerroroccursduringaProgram-Operationerrornestedwithinan
EraseSuspend.
5.5 128-BitProtectionRegister
TheC3devicearchitectureincludesa128-bitprotectionregisterthancanbeusedtoincreasethe
securityofasystemdesign.Forexample,thenumbercontainedintheprotectionregistercanbe
usedto“match”theflashcomponentwithothersystemcomponents,suchastheCPUorASIC,
preventingdevicesubstitution.TheIntelapplicationnote,
AP-657DesigningwiththeAdvanced+
BootBlockFlashMemoryArchitecture,containsadditionalapplicationinformation.
The128bitsoftheprotectionregisteraredividedintotwo64-bitsegments.Oneofthesegmentsis
programmedattheIntelfactorywithaunique64-bitnumber,whichisunchangeable.Theother
segmentisleftblankforcustomerdesignstoprogram,aspreferred.Oncethecustomersegmentis
programmed,itcanbelockedtopreventfurtherprogramming.
Intel£Advanced+BootBlockFlashMemory(C3)
30 Datasheet
5.5.1 ReadingtheProtectionRegister
Theprotectionregisterisreadintheread-identifiermode.Thedeviceisswitchedtothismodeby
issuingtheReadIdentifiercommand(0x90).Onceinthismode,readcyclesfromaddressesshown
inFigure6,“ProtectionRegisterMapping”retrievethespecifiedinformation.Toreturntoread-
arraymode,issuetheReadArraycommand(0xFF).
5.5.2 ProgrammingtheProtectionRegister
Theprotectionregisterbitsareprogrammedusingthetwo-cycleProtectionProgramcommand.
The64-bitnumberisprogrammed16bitsatatime.First,issuetheProtectionProgramSetup
command,0xC0.Thenextwritetothedevicewilllatchinaddressanddata,andprogramthe
specifiedlocation.TheallowableaddressesareshowninTable 6,“DeviceIdentificationCodes”on
page 20.SeeFigure18,“ProtectionRegisterProgrammingFlowchart”onpage 58.Attemptsto
addressProtectionProgramcommandsoutsidethedefinedprotectionregisteraddressspaceshould
notbeattempted.Attemptingtoprogramtoapreviouslylockedprotectionregistersegmentwill
resultinaStatusRegistererror(ProgramErrorbitSR[4]andLockErrorbitSR[1]willbesetto1).
5.5.3 LockingtheProtectionRegister
Theuser-programmablesegmentoftheprotectionregisterislockablebyprogrammingbit1ofthe
PR-LOCKlocationto0.SeeFigure6,“ProtectionRegisterMapping”onpage 31.Bit0ofthis
locationisprogrammedto0attheIntelfactorytoprotecttheuniquedevicenumber.Thisbitisset
usingtheProtectionProgramcommandtoprogram0xFFFDtothePR-LOCKlocation.Afterthese
bitshavebeenprogrammed,nofurtherchangescanbemadetothevaluesstoredintheprotection
register.ProtectionProgramcommandstoalockedsectionwillresultinaStatusRegistererror
(ProgramErrorbitSR[4]andLockErrorbitSR[1]willbesetto1).Protectionregisterlockout
stateisnotreversible.
5.6 VPPProgramandEraseVoltages
TheC3deviceprovidesin-systemprogramminganderaseinthe1.65 V–3.6 Vrange.Forfast
productionprogramming,12Vprogrammingcanbeused.RefertoFigure7,“ExamplePower
SupplyConfigurations”onpage 32.
Figure6.ProtectionRegisterMapping
0x88
0x85
64-bitSegment
(User-Programmable)
0x84
0x81
0x80 PRLockRegister0
64-bitSegment
(IntelFactory-Programmed)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128-BitProtectionRegister0
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Datasheet 31
5.6.1 ProgramProtection
Inadditiontotheflexibleblocklocking,theVPPprogrammingvoltagecanbeheldlowforabsolute
hardwarewriteprotectionofallblocksintheflashdevice.WhenVPPisbeloworequaltoVPPLK,
anyProgramorEraseoperationwillresultinanerror,promptingthecorrespondingstatus-register
bit(SR[3])tobeset.
0645_06
NOTE:
1. AresistorcanbeusediftheVCCsupplycansinkadequatecurrentbasedonresistorvalue.SeeAP-657
DesigningwiththeAdvanced+BootBlockFlashMemoryArchitecturefordetails.
Figure7.ExamplePowerSupplyConfigurations
V
CC
V
PP
12VFastProgramming
AbsoluteWriteProtectionWithV
PP
≤
V
PPLK
SystemSupply
12VSupply
10
≤
K
Ω
V
CC
V
PP
SystemSupply
12VSupply
LowVoltageand12VFastProgramming
V
CC
V
PP
SystemSupply
Prot#
(LogicSignal)
V
CC
V
PP
SystemSupply
Low-VoltageProgramming
Low-VoltageProgramming
AbsoluteWriteProtectionviaLogicSignal
(Note1)
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32 Datasheet
6.0 PowerConsumption
IntelFlashdeviceshaveatieredapproachtopowersavingsthatcansignificantlyreduceoverall
systempowerconsumption.TheAutomaticPowerSavings(APS)featurereducespower
consumptionwhenthedeviceisselectedbutidle.IfCE#isdeasserted,theflashentersitsstandby
mode,wherecurrentconsumptionisevenlower.IfRP#isdeasserted,theflashenterdeeppower-
downmodeforultra-lowcurrentconsumption.Thecombinationofthesefeaturescanminimize
memorypowerconsumption,andtherefore,overallsystempowerconsumption.
6.1 ActivePower(Program/Erase/Read)
WithCE#atalogic-lowlevelandRP#atalogic-highlevel,thedeviceisintheactivemode.Refer
totheDCCharacteristictablesforICCcurrentvalues.Activepoweristhelargestcontributorto
overallsystempowerconsumption.Minimizingtheactivecurrentcouldhaveaprofoundeffecton
systempowerconsumption,especiallyforbattery-operateddevices.
6.2 AutomaticPowerSavings(APS)
AutomaticPowerSavingsprovideslow-poweroperationduringreadmode.Afterdataisreadfrom
thememoryarrayandtheaddresslinesareidle,APScircuitryplacesthedeviceinamodewhere
typicalcurrentiscomparabletoICCS.Theflashstaysinthisstaticstatewithoutputsvaliduntila
newlocationisread.
6.3 StandbyPower
WhenCE#isatalogic-highlevel(VIH),theflashmemoryisinstandbymode,whichdisables
muchofthedevice’scircuitryandsubstantiallyreducespowerconsumption.Outputsareplacedin
ahigh-impedancestateindependentofthestatusoftheOE#signal.IfCE#transitionstoalogic-
highlevelduringEraseorProgramoperations,thedevicewillcontinuetoperformtheoperation
andconsumecorrespondingactivepoweruntiltheoperationiscompleted.
Systemengineersshouldanalyzethebreakdownofstandbytimeversusactivetime,andquantify
therespectivepowerconsumptionineachmodefortheirspecificapplication.Thisapproachwill
provideamoreaccuratemeasureofapplication-specificpowerandenergyrequirements.
6.4 DeepPower-DownMode
Thedeeppower-downmodeisactivatedwhenRP# = VIL.Duringreadmodes,RP#goinglowde-
selectsthememoryandplacestheoutputsinahigh-impedancestate.Recoveryfromdeeppower-
downrequiresaminimumtimeoftPHQVforReadoperations,andtPHWL/tPHELforWrite
operations.
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Datasheet 33
Duringprogramorerasemodes,RP#transitioninglowwillabortthein-progressoperation.The
memorycontentsoftheaddressbeingprogrammedortheblockbeingerasedarenolongervalidas
thedataintegrityhasbeencompromisedbytheabort.Duringdeeppower-down,allinternal
circuitsareswitchedtoalow-powersavingsmode(RP#transitioningtoVILorturningoffpower
tothedeviceclearsthestatusregister).
6.5 PowerandResetConsiderations
6.5.1 Power-Up/DownCharacteristics
Inordertopreventanyconditionthatmayresultinaspuriouswriteoreraseoperation,itis
recommendedtopower-upVCCandVCCQtogether.Conversely,VCCandVCCQmustpower-
downtogether.
Itisalsorecommendedtopower-upVPPwithorafterVCChasreachedVCCmin.Conversely,VPP
mustpowerdownwithorslightlybeforeVCC.
IfVCCQand/orVPParenotconnectedtotheVCCsupply,thenVCCshouldattainVCCminbefore
applyingVCCQandVPP.Deviceinputsshouldnotbedrivenbeforesupplyvoltagereaches
VCCmin.
PowersupplytransitionsshouldonlyoccurwhenRP#islow.
6.5.2 RP#ConnectedtoSystemReset
TheuseofRP#duringsystemresetisimportantwithautomatedprogram/erasedevicessincethe
systemexpectstoreadfromtheflashmemorywhenitcomesoutofreset.IfaCPUresetoccurs
withoutaflashmemoryreset,properCPUinitializationwillnotoccurbecausetheflashmemory
maybeprovidingstatusinformationinsteadofarraydata.IntelrecommendsconnectingRP#tothe
systemCPURESET#signaltoallowproperCPU/flashinitializationfollowingsystemreset.
SystemdesignersmustguardagainstspuriouswriteswhenVCCvoltagesareaboveVLKO.Because
bothWE#andCE#mustbelowforacommandwrite,drivingeithersignaltoVIHwillinhibit
writestothedevice.TheCUIarchitectureprovidesadditionalprotectionsincealterationof
memorycontentscanonlyoccuraftersuccessfulcompletionofthetwo-stepcommandsequences.
ThedeviceisalsodisableduntilRP#isbroughttoVIH,regardlessofthestateofitscontrolinputs.
Byholdingthedeviceinresetduringpower-up/down,invalidbusconditionsduringpower-upcan
bemasked,providingyetanotherlevelofmemoryprotection.
6.5.3 VCC,VPPandRP#Transitions
TheCUIlatchescommandsasissuedbysystemsoftwareandisnotalteredbyVPPorCE#
transitionsorWSMactions.Itsdefaultstateuponpower-up,afterexitfromresetmodeorafter
VCCtransitionsaboveVLKO(Lockoutvoltage),isread-arraymode.
AfteranyprogramorBlock-Eraseoperationiscomplete(evenafterVPPtransitionsdownto
VPPLK),theCUImustberesettoread-arraymodeviatheReadArraycommandifaccesstothe
flash-memoryarrayisdesired.
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6.6 PowerSupplyDecoupling
Flashmemorypower-switchingcharacteristicsrequirecarefuldevicedecoupling.System
designersshouldconsiderthefollowingthreesupplycurrentissues:
•Standbycurrentlevels(ICCS)
•Readcurrentlevels(ICCR)
•TransientpeaksproducedbyfallingandrisingedgesofCE#.
Transientcurrentmagnitudesdependonthedeviceoutputs’capacitiveandinductiveloading.Two-
linecontrolandproperdecouplingcapacitorselectionwillsuppressthesetransientvoltagepeaks.
Eachflashdeviceshouldhavea0.1µFceramiccapacitorconnectedbetweeneachVCCandGND,
andbetweenitsVPPandVSS.Thesehigh-frequency,inherentlylow-inductancecapacitorsshould
beplacedascloseaspossibletothepackageleads.
7.0 ThermalandDCCharacteristics
7.1 AbsoluteMaximumRatings
Warning: Stressingthedevicebeyondthe“AbsoluteMaximumRatings”maycausepermanentdamage.
Thesearestressratingsonly.Operationbeyondthe“OperatingConditions”isnotrecommended,
andextendedexposurebeyondthe“OperatingConditions”mayaffectdevicereliability.
.
NOTICE:Specificationsaresubjecttochangewithoutnotice.VerifywithyourlocalIntelSalesofficethatyouhave
thelatestdatasheetbeforefinalizingadesign.
Parameter MaximumRating Notes
ExtendedOperatingTemperature
DuringRead –40°Cto+85°C
DuringBlockEraseandProgram –40°Cto+85°C
TemperatureunderBias –40°Cto+85°C
StorageTemperature –65°Cto+125°C
VoltageOnAnyPin(exceptVCCandVPP)withRespecttoGND –0.5 Vto+3.7 V 1
VPPVoltage(forBlockEraseandProgram)withRespecttoGND –0.5 Vto+13.5 V 1,2,3
VCCandVCCQ
SupplyVoltagewithRespecttoGND –0.2Vto+3.6V
OutputShortCircuitCurrent 100mA 4
NOTES:
1. MinimumDCvoltageis–0.5 Voninput/outputpins.Duringtransitions,thislevelmay
undershootto–2.0 Vforperiods<20ns.MaximumDCvoltageoninput/outputpinsisVCC
+0.5 Vwhich,duringtransitions,mayovershoottoVCC+2.0 Vforperiods<20ns.
2. MaximumDCvoltageonVPPmayovershootto+14.0 Vforperiods<20ns.
3. VPPProgramvoltageisnormally1.65 V–3.6 V.Connectiontoa11.4 V–12.6 Vsupplycanbe
doneforamaximumof1000cyclesonthemainblocksand2500cyclesontheparameter
blocksduringprogram/erase.VPPmaybeconnectedto12 Vforatotalof80hoursmaximum.
4. Outputshortedfornomorethanonesecond.Nomorethanoneoutputshortedatatime.
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7.2 OperatingConditions
7.3 DCCurrentCharacteristics
Table10.TemperatureandVoltageOperatingConditions
Symbol Parameter Notes Min Max Units
TAOperatingTemperature –40 +85 °C
VCC1 VCCSupplyVoltage 1,22.73.6Volts
VCC2 1,23.03.6
VCCQ1
I/OSupplyVoltage
12.73.6
VoltsVCCQ2 1.65 2.5
VCCQ3 1.8 2.5
VPP1 SupplyVoltage 1 1.65 3.6 Volts
VPP2 1,3 11.4 12.6 Volts
Cycling BlockEraseCycling 3 100,000 Cycles
NOTES:
1. VCCandVCCQmustsharethesamesupplywhentheyareintheVCC1range.
2. VCCMax=3.3Vfor0.25µm32-Mbitdevices.
3. ApplyingVPP = 11.4 V–12.6 Vduringaprogram/erasecanonlybedoneforamaximumof1000cycleson
themainblocksand2500cyclesontheparameterblocks.VPPmaybeconnectedto12 Vforatotalof
80hoursmaximum.
Table11.DCCurrentCharacteristics(Sheet1of3)
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit Test
Conditions
VCCQ 2.7V–3.6V1.65V–2.5V1.8V–2.5V
Note Typ Max Typ Max Typ Max
ILI InputLoadCurrent 1,2 ±1 ±1 ±1µA
VCC=
VCCMax
VCCQ=
VCCQMax
VIN=VCCQ
orGND
ILO OutputLeakage
Current 1,2 ±10 ±10 ±10 µA
VCC=
VCCMax
VCCQ=
VCCQMax
VIN=VCCQ
orGND
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ICCS
VCC
StandbyCurrent
for0.13and0.18
MicronProduct 1 7 15 20 50 150 250 µA VCC=
VCCMax
CE#=RP#
=VCCQ
orduring
Program/
Erase
Suspend
WP#=
VCCQor
GND
VCC
StandbyCurrent
for0.25Micron
Product 1 10 25 20 50 150 250 µA
ICCD
VCCPower-Down
Currentfor0.13and
0.18MicronProduct 1,2 7 15 7 20 7 20 µA VCC=
VCCMax
VCCQ=
VCCQMax
VIN=VCCQ
orGND
RP#=GND
±0.2V
VCCPower-Down
Currentfor0.25
Product 1,2 7 25 7 25 7 25 µA
ICCR
VCCReadCurrentfor
0.13and0.18Micron
Product 1,2,3 9 18 8 15 9 15 mA VCC=
VCCMax
VCCQ=
VCCQMax
OE#=VIH,
CE#=VIL
f=5MHz,
IOUT=0mA
Inputs=VIL
orVIH
VCCReadCurrentfor
0.25MicronProduct 1,2,3 10 18 8 15 9 15 mA
IPPD VPPDeepPower-
DownCurrent 1 0.2 5 0.2 5 0.2 5 µA RP#=GND
±0.2V
VPP
≤VCC
ICCW VCCProgramCurrent 1,4
18 55 18 55 18 55 mA VPP=VPP1,
Programin
Progress
82210301030mA
VPP
=VPP2
(12v)
Programin
Progress
ICCE VCCEraseCurrent 1,4
16 45 21 45 21 45 mA VPP=VPP1,
Erasein
Progress
81516451645mA
VPP=VPP2
(12v),
Erasein
Progress
ICCES/
ICCWS
VCCEraseSuspend
Currentfor0.13and
0.18MicronProduct 1,4,5
7 15 50 200 50 200 µA CE#=VIH,
Erase
Suspendin
Progress
VCCEraseSuspend
Currentfor0.25
MicronProduct 10 25 50 200 50 200 µA
Table11.DCCurrentCharacteristics(Sheet2of3)
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit Test
Conditions
VCCQ 2.7V–3.6V 1.65V–2.5V1.8V–2.5V
Note Typ Max Typ Max Typ Max
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IPPR VPPReadCurrent 1,4 2±15 2 ±15 2 ±15 µA VPP
≤VCC
50 200 50 200 50 200 µA VPP
>VCC
IPPW VPPProgramCurrent 1,4
0.05 0.1 0.05 0.1 0.05 0.1 mA VPP=VPP1,
Programin
Progress
8228 22 8 22mA
VPP
=VPP2
(12v)
Programin
Progress
IPPE VPP
EraseCurrent 1,4
0.05 0.1 0.05 0.1 0.05 0.1 mA VPP=VPP1,
Erasein
Progress
82216451645mA
VPP=VPP2
(12v),
Erasein
Progress
IPPES/
IPPWS VCCEraseSuspend
Current 1,4
0.2 5 0.2 5 0.2 5 µA
VPP=VPP1,
Programor
Erase
Suspendin
Progress
50 200 50 200 50 200 µA
VPP=VPP2
(12v),
Programor
Erase
Suspendin
Progress
NOTES:
1. AllcurrentsareinRMSunlessotherwisenoted.TypicalvaluesatnominalVCC,TA=+25°C.
2. ThetestconditionsVCCMax,VCCQMax,VCCMin,andVCCQMinrefertothemaximumorminimumVCCor
VCCQvoltagelistedatthetopofeachcolumn.VCCMax=3.3Vfor0.25µm32-Mbitdevices.
3. AutomaticPowerSavings(APS)reducesICCRtoapproximatelystandbylevelsinstaticoperation(CMOS
inputs).
4. Sampled,not100%tested.
5. ICCESorICCWSisspecifiedwithdevicede-selected.Ifdeviceisreadwhileinerasesuspend,currentdraw
issumofICCESandICCR.Ifthedeviceisreadwhileinprogramsuspend,currentdrawisthesumofICCWS
andICCR.
Table11.DCCurrentCharacteristics(Sheet3of3)
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit Test
Conditions
VCCQ 2.7V–3.6V1.65V–2.5V1.8V–2.5V
Note Typ Max Typ Max Typ Max
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7.4 DCVoltageCharacteristics
Table12.DCVoltageCharacteristics
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit TestConditionsVCCQ 2.7V–3.6V1.65V–2.5V1.8V–2.5V
Note Min Max Min Max Min Max
VIL InputLow
Voltage –0.4 VCC*
0.22 V –0.4 0.4 –0.4 0.4 V
VIH InputHigh
Voltage 2.0 VCCQ
+0.3V VCCQ–
0.4V VCCQ
+0.3V VCCQ–
0.4V VCCQ
+0.3V V
VOL OutputLow
Voltage –0.1 0.1 -0.1 0.1 -0.1 0.1 V VCC=VCCMin
VCCQ=VCCQMin
IOL=100µA
VOH OutputHigh
Voltage VCCQ
–0.1V VCCQ–
0.1V VCCQ–
0.1V V
VCC=VCCMin
VCCQ=VCCQMin
IOH=–100µA
VPPLK VPPLock-
OutVoltage 1 1.0 1.0 1.0 V CompleteWrite
Protection
VPP1 VPPduring
Program/
Erase
Operations
1 1.65 3.6 1.65 3.6 1.65 3.6 V
VPP2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 V
VLKO
VCC
Prog/
Erase
Lock
Voltage 1.5 1.5 1.5 V
VLKO2
VCCQ
Prog/
Erase
Lock
Voltage 1.2 1.2 1.2 V
NOTES:
1. EraseandProgramareinhibitedwhenVPP<VPPLKandnotguaranteedoutsidethevalidVPPrangesofVPP1andVPP2.
2. ApplyingVPP = 11.4 V–12.6 Vduringprogram/erasecanonlybedoneforamaximumof1000cyclesonthemainblocksand
2500cyclesontheparameterblocks.VPPmaybeconnectedto12 Vforatotalof80hoursmaximum.
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Datasheet 39
8.0 ACCharacteristics
8.1 ACReadCharacteristics
Table13.ReadOperations—8MbitDensity
#SymParameter
Density 8Mbit
Unit
Product 90ns 110ns
VCC 3.0V–3.6V2.7V–3.6V3.0V–3.6V2.7V–3.6V
Note Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 3,4 80 90 100 110 ns
R2 tAVQV AddresstoOutputDelay 3,4 80 90 100 110 ns
R3 tELQV CE#toOutputDelay 1,3,4 80 90 100 110 ns
R4 tGLQV OE#toOutputDelay 1,3,4 30 30 30 30 ns
R5 tPHQV RP#toOutputDelay 3,4 150 150 150 150 ns
R6 tELQX CE#toOutputinLowZ2,3,40 0 00ns
R7 tGLQX OE#toOutputinLowZ2,3,40 0 00ns
R8 tEHQZ CE#toOutputinHighZ 2,3,4 20 20 20 20 ns
R9 tGHQZ OE#toOutputinHighZ 2,3,4 20 20 20 20 ns
R10 tOH
OutputHoldfrom
Address,CE#,orOE#
Change,Whichever
OccursFirst 2,3,4 0 0 0 0 ns
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure8,“ReadOperationWaveform”onpage 43.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsandmaximumallowableinput
slewrate.
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Table14.ReadOperations—16MbitDensity
#Sym
Para-
mete
r
Density 16Mbit
Unit Notes
Product 70ns 80ns 90ns 110ns
VCC 2.7V–3.6V2.7V–3.6V3.0V–3.6V2.7V–3.6V3.0V–3.6V 2.7V–3.6V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 70 80 80 90 100 110 ns 3,4
R2 tAVQ
VAddressto
OutputDelay 70 80 80 90 100 110 ns 3,4
R3 tELQ
VCE#toOutput
Delay 70 80 80 90 100 110 ns 1,3,4
R4 tGLQ
VOE#toOutput
Delay 20 20 30 30 30 30 ns 1,3,4
R5 tPHQ
VRP#toOutput
Delay 150 150 150 150 150 150 ns 3,4
R6 tELQ
XCE#toOutputin
LowZ000000
ns 2,3,4
R7 tGLQ
XOE#toOutputin
LowZ000000
ns 2,3,4
R8 tEHQ
ZCE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R9 tGHQ
ZOE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R10 tOH
OutputHoldfrom
Address,CE#,or
OE#Change,
Whichever
OccursFirst
000000
ns 2,3,4
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure8,“ReadOperationWaveform”onpage 43.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsandmaximumallowableinput
slewrate.
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Table15.ReadOperations—32MbitDensity
#Sym
Para-
meter
Density 32Mbit
Unit Notes
Product 70ns 90ns 100ns 110ns
VCC 2.7V–3.6V2.7V–3.6V3.0V–3.3V2.7V–3.3V3.0V–3.3V2.7V–3.3V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 70 90 90 100 100 110 ns 3,4
R2 tAVQ
VAddresstoOutput
Delay 70 90 90 100 100 110 ns 3,4
R3 tELQ
VCE#toOutput
Delay 70 90 90 100 100 110 ns 1,3,4
R4 tGLQ
VOE#toOutput
Delay 20 20 30 30 30 30 ns 1,3,4
R5 tPHQ
VRP#toOutput
Delay 150 150 150 150 150 150 ns 3,4
R6 tELQ
XCE#toOutputin
LowZ000000
ns 2,3,4
R7 tGLQ
XOE#toOutputin
LowZ000000
ns 2,3,4
R8 tEHQ
ZCE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R9 tGHQ
ZOE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R10 tOH
OutputHoldfrom
Address,CE#,or
OE#Change,
Whichever
OccursFirst
000000
ns 2,3,4
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure8,“ReadOperationWaveform”onpage 43.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsandmaximumallowable
inputslewrate.
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Table16.ReadOperations
—64MbitDensity
#Sym Parameter
Density 64Mbit
Unit
Product 70ns 80ns
VCC 2.7V–3.6V2.7V–3.6V
Note Min Max Min Max
R1 tAVAV ReadCycleTime 3,4 70 80 ns
R2 tAVQV AddresstoOutputDelay 3,4 70 80 ns
R3 tELQV CE#toOutputDelay 1,3,4 70 80 ns
R4 tGLQV OE#toOutputDelay 1,3,4 20 20 ns
R5 tPHQV RP#toOutputDelay 3,4 150 150 ns
R6 tELQX CE#toOutputinLowZ2,3,400ns
R7 tGLQX OE#toOutputinLowZ2,3,400ns
R8 tEHQZ CE#toOutputinHighZ 2,3,4 20 20 ns
R9 tGHQZ OE#toOutputinHighZ 2,3,4 20 20 ns
R10 tOH OutputHoldfromAddress,CE#,orOE#
Change,WhicheverOccursFirst 2,3,4 0 0 ns
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure8,“ReadOperationWaveform”onpage 43.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsand
maximumallowableinputslewrate.
Figure8.ReadOperationWaveform
R5
R10
R7
R6
R9R4
R8R3
R1
R2 R1
A
ddress[A]
CE#[E]
OE#[G]
WE#[W]
Data[D/Q]
RST#[P]
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8.2 ACWriteCharacteristics
Table17.WriteOperations—8MbitDensity
#Sym Parameter
Density 8Mbit
Unit
Product 90ns 110ns
VCC
3.0V–3.6V80 100
2.7V–3.6V90110
Note Min Min Min Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)GoingLow 4,5 150 150 150 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)GoingLow 4,5 0 0 0 0 ns
W3 tWLWH/
tELEH WE#(CE#)PulseWidth 4,5 50 60 70 70 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 50 50 60 60 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)GoingHigh 2,4,5 50 60 70 70 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#(CE#)High 4,5 0 0 0 0 ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 2,4,5 30 30 30 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 200 200 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4 0 0 0 0 ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)GoingHigh 3,4 0 0 0 0 ns
W13 tQVBL WP#
HoldfromValidSRD 3,4 0 0 0 0 ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 30 30 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#orWE#goinghigh(whichever
goeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.Similarly,writepulsewidthhigh(tWPH)isdefinedfromCE#or
WE#goinghigh(whichevergoeshighfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 7,“CommandBusOperations”onpage 24forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsandmaximumallowableinput
slewrate.
5. SeeFigure9,“WriteOperationsWaveform”onpage 48.
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Table18.WriteOperations—16MbitDensity
#SymParameter
Density 16Mbit
Unit
Product 70ns 80ns 90ns 110ns
VCC
3.0V–3.6V 80 100
2.7V–3.6V7080 90 110
Note Min Min Min Min Min Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)Going
Low 4,5 150 150 150 150 150 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)GoingLow 4,5 0 0 0 0 0 0 ns
W3 tWLWH/
tELEH WE#(CE#)PulseWidth 1,4,5 45 50 50 60 70 70 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 40 40 50 50 60 60 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)GoingHigh 2,4,5 50 50 50 60 70 70 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#(CE#)
High 4,5 0 0 0 0 0 0 ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 0 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)GoingHigh 3,4 0 0 0 0 0 0 ns
W13 tQVBL WP#
HoldfromValidSRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 30 30 30 30 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#orWE#goinghigh
(whichevergoeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.Similarly,writepulsewidthhigh(tWPH)isdefined
fromCE#orWE#goinghigh(whichevergoeshighfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 7,“CommandBusOperations”onpage 24forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsandmaximumallowableinput
slewrate.
5. SeeFigure9,“WriteOperationsWaveform”onpage 48.
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Table19.WriteOperations—32MbitDensity
#Sym Parameter
Density 32Mbit
Unit
Product 70ns 90ns 100ns 110ns
VCC
3.0V–3.6V690 100
2.7V–3.6V 70 90 100 110
Note Min Min Min Min Min Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)
GoingLow 4,5 150 150 150 150 150 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)
GoingLow 4,5000000ns
W3 tWLWH
/
tELEH WE#(CE#)PulseWidth 1,4,5 45 60 60 70 70 70 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 40 40 50 60 60 60 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)Going
High 2,4,5 50 60 60 70 70 70 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#
(CE#)High 4,5000000ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)
High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)
High 2,4,5 0 0 0 0 0 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4000000ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)Going
High 3,4000000ns
W13 tQVBL WP#
HoldfromValidSRD 3,4000000ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 30 30 30 30 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#orWE#goinghigh(whichever
goeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.Similarly,writepulsewidthhigh(tWPH)isdefinedfromCE#or
WE#goinghigh(whichevergoeshighfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 7,“CommandBusOperations”onpage 24forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsandmaximumallowableinput
slewrate.
5. SeeFigure9,“WriteOperationsWaveform”onpage 48.
6. VCCMax=3.3Vfor32-Mbit0.25Micronproduct.
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Table20.WriteOperations—64MbitDensity
#Sym Parameter
Density 64Mbit
UnitProduct 80ns
VCC 2.7V–3.6VNote Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)GoingLow 4,5 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)GoingLow 4,5 0 ns
W3 tWLWH/
tELEH WE#(CE#)PulseWidth 1,4,5 60 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 40 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)GoingHigh 2,4,5 60 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#(CE#)High 4,5 0 ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)High 2,4,5 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)High 2,4,5 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 1,4,5 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4 0 ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)GoingHigh 3,4 0 ns
W13 tQVBL WP#
HoldfromValidSRD 3,4 0 ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#or
WE#goinghigh(whichevergoeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.
Similarly,writepulsewidthhigh(tWPH)isdefinedfromCE#orWE#goinghigh(whichevergoes
highfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 7,“CommandBusOperations”onpage 24forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure11,“ACInput/OutputReferenceWaveform”onpage 50fortimingmeasurementsand
maximumallowableinputslewrate.
5. SeeFigure9,“WriteOperationsWaveform”onpage 48.
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 47
8.3 EraseandProgramTimings
Table21.EraseandProgramTimings
Figure9.WriteOperationsWaveform
Symbol Parameter VPP 1.65V–3.6V11.4V–12.6VUnit
Note Typ Max Typ Max
tBWPB 4-KWParameterBlock
WordProgramTime 1,2,3 0.10 0.30 0.03 0.12 s
tBWMB 32-KWMainBlock
WordProgramTime 1,2,3 0.8 2.4 0.24 1 s
tWHQV1
/tEHQV1
WordProgramTimefor0.13
and0.18MicronProduct 1,2,3 12 200 8 185 µs
WordProgramTimefor0.25
MicronProduct 1,2,3 22 200 8 185 µs
tWHQV2/tEHQV2 4-KWParameterBlock
EraseTime 1,2,30.5 4 0.4 4 s
tWHQV3/tEHQV3 32-KWMainBlock
EraseTime 1,2,31 5 0.6 5 s
tWHRH1/tEHRH1 ProgramSuspendLatency 1,3 5 10 5 10 µs
tWHRH2/tEHRH2 EraseSuspendLatency 1,3 5 20 5 20 µs
NOTES:
1. TypicalvaluesmeasuredatTA= +25°Candnominalvoltages.
2. Excludesexternalsystem-leveloverhead.
3. Sampled,butnot100%tested.
W10
W1
W7W4
W9W9
W3W3
W2
W6
W8W5
A
ddress[A]
CE#[E]
WE#[W]
OE#[G]
Data[D/Q]
RP#[P]
Vpp[V]
Intel£Advanced+BootBlockFlashMemory(C3)
48 Datasheet
8.4 ResetSpecifications
Table22.ResetSpecifications
Symbol Parameter Notes VCC2.7V–3.6VUnit
Min Max
tPLPH RP#LowtoResetduringRead
(IfRP#istiedtoVCC,thisspecificationisnot
applicable) 1,2 100 ns
tPLRH1 RP#LowtoResetduringBlockErase 3 22 µs
tPLRH2 RP#LowtoResetduringProgram 3 12 µs
NOTES:
1. IftPLPHis<100nsthedevicemaystillresetbutthisisnotguaranteed.
2. IfRP#isassertedwhileaBlockEraseor
WordProgramoperationisnotexecuting,theresetwillcomplete
within100ns.
3. Sampled,butnot100%tested.
Figure10.ResetOperationsWaveforms
IH
V
IL
V
RP#(P)
PLPH
t
IH
V
IL
V
RP#(P)
PLPH
t
(A)ResetduringReadMode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B)ResetduringProgramorBlockErase,<
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP#(P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C)ResetProgramorBlockErase,>
PLPH
tPLRH
t
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 49
8.5 ACI/OTestConditions
NOTE: Inputtimingbegins,andoutputtimingends,atVCCQ/2.Inputriseandfalltimes(10%to90%)<5ns.
WorstcasespeedconditionsarewhenVCC=VCCMin.
NOTE: SeeTable17forcomponentvalues.
8.6 DeviceCapacitance
TA=25°C,f=1MHz
Figure11.ACInput/OutputReferenceWaveform
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test
Points
Input Output
Figure12.TransientEquivalentTestingLoadCircuit
Device
UnderTest
V
CCQ
C
L
R
2
R
1
Out
Table23.TestConfigurationComponentValuesforWorstCaseSpeedConditions
TestConfiguration CL(pF) R1(kΩ)R
2(kΩ)
VCCQMinStandardTest 50 25 25
NOTE: CLincludesjigcapacitance.
Symbol Parameter§Typ Max Unit Condition
CIN InputCapacitance 6 8 pF VIN=0.0 V
COUT OutputCapacitance 8 12 pF VOUT=0.0 V
§Sampled,not100%tested.
Intel£Advanced+BootBlockFlashMemory(C3)
50 Datasheet
AppendixAWriteStateMachineStates
Thistableshowsthecommandstatetransitionsbasedonincomingcommands.
CommandInput(andNextState)
CurrentState SR.7 Data
When
Read ReadArray
(FFH) Program
Setup(10/
40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0) ReadStatus
(70H) Clear
Status
(50H)
ReadArray “1” Array ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
ReadStatus “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
ReadConfig. “1” Config ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
ReadQuery “1” CFI ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
LockSetup “1” Status LockCommandError Lock(Done) Lock
Cmd.Error Lock
(Done) LockCmd.Error
LockCmd.Error “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
LockOper.(Done) “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
Prot.Prog.Setup “1” Status ProtectionRegisterProgram
Prot.Prog.
(NotDone) “0” Status ProtectionRegisterProgram(NotDone)
Prot.Prog.(Done) “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
Prog.Setup “1” Status Program
Program(NotDone) “0” Status Program(NotDone) Prog.Sus.
Status Program(NotDone)
Prog.Susp.Status “1” Status Prog.Sus.
ReadArray ProgramSuspend
ReadArray Prog.(Not
Done) Prog.Sus.Rd.
Array Program
(NotDone) Prog.Sus.
Status Prog.Sus.
Rd.Array
Prog.Susp.Read
Array “1” Array Prog.Sus.
ReadArray ProgramSuspend
ReadArray Prog.(Not
Done) Prog.Sus.Rd.
Array Program
(NotDone) Prog.Sus.
Status Prog.Sus.
Rd.Array
Prog.Susp.Read
Config “1” Config Prog.Sus.
ReadArray ProgramSuspend
ReadArray Prog.(Not
Done) Prog.Sus.Rd.
Array Program
(NotDone) Prog.Sus.
Status Prog.Sus.
Rd.Array
Prog.Susp.Read
Query “1” CFI Prog.Sus.
ReadArray ProgramSuspend
ReadArray Prog.(Not
Done) Prog.Sus.Rd.
Array Program
(NotDone) Prog.Sus.
Status Prog.Sus.
Rd.Array
Program(Done) “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadStatus ReadArray
EraseSetup “1” Status EraseCommandError Erase
(NotDone) EraseCmd.
Error Erase
(NotDone) EraseCommandError
EraseCmd.Error “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadStatus ReadArray
Erase(NotDone) “0” Status Erase(NotDone) EraseSus.
Status Erase(NotDone)
Ers.Susp.Status “1” Status EraseSus.
ReadArray Prog.Setup Ers.Sus.
Rd.Array Erase Ers.Sus.Rd.
Array Erase EraseSus.
Status Ers.Sus.
Rd.Array
EraseSusp.Array “1” Array EraseSus.
ReadArray Prog.Setup Ers.Sus.
Rd.Array Erase Ers.Sus.Rd.
Array Erase EraseSus.
Status Ers.Sus.
Rd.Array
Ers.Susp.Read
Config “1” Config EraseSus.
ReadArray Prog.Setup Ers.Sus.
Rd.Array Erase Ers.Sus.Rd.
Array Erase EraseSus.
Status Ers.Sus.
Rd.Array
Ers.Susp.Read
Query “1” CFI EraseSus.
ReadArray Prog.Setup Ers.Sus.
Rd.Array Erase Ers.Sus.Rd.
Array Erase EraseSus.
Status Ers.Sus.
Rd.Array
Erase(Done) “1” Status ReadArray Prog.Setup Ers.Setup ReadArray ReadSts. ReadArray
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 51
CommandInput(andNextState)
CurrentState ReadConfig
(90H) ReadQuery
(98H) LockSetup
(60H) Prot.Prog.
Setup(C0H) LockConfirm
(01H) LockDown
Confirm
(2FH) UnlockConfirm
(D0H)
ReadArray ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
ReadStatus ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
ReadConfig. ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
ReadQuery ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
LockSetup LockingCommandError LockOperation(Done)
LockCmd.Error ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
LockOper.
(Done) ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
Prot.Prog.Setup ProtectionRegisterProgram
Prot.Prog.
(NotDone) ProtectionRegisterProgram(NotDone)
Prot.Prog.
(Done) ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
Prog.Setup Program
Program
(NotDone) Program(NotDone)
Prog.Susp.
Status Prog.Susp.
ReadConfig. Prog.Susp.
ReadQuery ProgramSuspendReadArray Program
(NotDone)
Prog.Susp.
ReadArray Prog.Susp.
ReadConfig. Prog.Susp.
ReadQuery ProgramSuspendReadArray Program
(NotDone)
Prog.Susp.
ReadConfig. Prog.Susp.
ReadConfig. Prog.Susp.
ReadQuery ProgramSuspendReadArray Program
(NotDone)
Prog.Susp.
ReadQuery. Prog.Susp.
ReadConfig. Prog.Susp.
ReadQuery ProgramSuspendReadArray Program
(NotDone)
Program
(Done) ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
Erase
Setup EraseCommandError Erase
(NotDone)
EraseCmd.
Error ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
Erase
(NotDone) Erase(NotDone)
EraseSusp.
Status Ers.Susp.Read
Config. EraseSuspend
ReadQuery LockSetup EraseSuspendReadArray Erase
(NotDone)
EraseSuspend
Array Ers.Susp.Read
Config. EraseSuspend
ReadQuery LockSetup EraseSuspendReadArray Erase
(NotDone)
ErasSus.Read
Config EraseSuspend
ReadConfig. EraseSuspend
ReadQuery LockSetup EraseSuspendReadArray Erase
(NotDone)
ErasSus.Read
Query EraseSuspend
ReadConfig. EraseSuspend
ReadQuery LockSetup EraseSuspendReadArray Erase
(NotDone)
Ers.(Done) ReadConfig. ReadQuery LockSetup Prot.Prog.Setup ReadArray
Intel£Advanced+BootBlockFlashMemory(C3)
52 Datasheet
AppendixBFlowCharts
Figure13.WordProgramFlowchart
Program
Suspend
Loop
Start
Write0x40,
WordAddress
WriteData,
WordAddress
ReadStatus
Register
SR[7]=
FullStatus
Check
(ifdesired)
Program
Complete
Suspend?
1
0
No
Yes
WORDPROGRAMPROCEDURE
RepeatforsubsequentWordProgramoperations.
FullStatusRegistercheckcanbedoneaftereachprogram,or
afterasequenceofprogramoperations.
Write0xFFafterthelastoperationtosettotheReadArray
state.
Comments
Bus
Operation Command
Data=0x40
Addr= Locationtoprogram
Write Program
Setup
Data= Datatoprogram
Addr= Locationtoprogram
Write Data
Statusregisterdata:ToggleCE#or
OE#toupdateStatusRegister
Read None
CheckSR[7]
1=WSMReady
0=WSMBusy
Idle None
(Setup)
(Confirm)
FULLSTATUSCHECKPROCEDURE
ReadStatus
Register
Program
Successful
SR[3]=
SR[1]=
0
0
SR[4]=
0
1
1
1VPPRange
Error
Device
ProtectError
Program
Error
SR[3]MUSTbeclearedbeforetheWriteStateMachinewill
allowfurtherprogramattempts.
Ifanerrorisdetected,cleartheStatusRegisterbefore
continuingoperations-onlytheClearStausRegister
commandclearstheStatusRegistererrorbits.
Idle
Idle
Bus
Operation
None
None
Command
CheckSR[3]:
1=V
PPError
CheckSR[4]:
1=DataProgramError
Comments
Idle None CheckSR[1]:
1= Blocklocked;operationaborted
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 53
Figure14.ProgramSuspend/ResumeFlowchart
ReadStatus
Register
SR[7]=
SR[2]=
ReadArray
Data
Program
Completed
Done
Reading
Program
Resumed
ReadArray
Data
0
No
0
Yes
1
1
PROGRAMSUSPEND/RESUMEPROCEDURE
Write Program
Resume Data=0xD0
Addr=Anyaddress
Bus
Operation Command Comments
Write Program
Suspend Data=0xB0
Addr=Anyaddress
Idle None CheckSR[7]:
1=WSMready
0=WSMbusy
Idle None CheckSR[2]:
1= Programsuspended
0= Programcompleted
Write Read
Array Data=0xFF
Addr=Anyaddress
Read None Readarraydatafromblockotherthan
theonebeingprogrammed
Read None
Statusregisterdata
ToggleCE#orOE#toupdateStatus
register
Addr=Anyaddress
Write0xFF
(ReadArray)
Write0xD0
AnyAddress
(ProgramResume)
Write0xFF
(Read
Array)
Write Read
Status Data=0x70
Addr=Anyaddress
Start
Write0xB0
AnyAddress
(ProgramSuspend)
Write0x70
AnyAddress
(ReadStatus)
Intel£Advanced+BootBlockFlashMemory(C3)
54 Datasheet
Figure15.EraseSuspend/ResumeFlowchart
Erase
Completed
ReadArray
Data
0
0
1
1
Start
ReadStatus
Register
SR[7]=
SR[6]=
Erase
Resumed
Done
Reading
Write
Write
Idle
Idle
Write
Erase
Suspend
ReadArray
orProgram
None
None
Program
Resume
Data=0xB0
Addr=Anyaddress
Data= 0xFFor0x40
Addr=Anyaddress
CheckSR[7]:
1=WSMready
0=WSMbusy
CheckSR[6]:
1=Erasesuspended
0=Erasecompleted
Data=0xD0
Addr=Anyaddress
Bus
Operation Command Comments
Read None StatusRegisterdata.ToggleCE#or
OE#toupdateStatusregister;
Addr=AnyAddress
Reador
Write None Readarrayorprogramdatafrom/to
blockotherthantheonebeingerased
ERASESUSPEND/RESUMEPROCEDURE
Write0x70,
AnyAddress (ReadStatus)
Write0xB0,
AnyAddress (EraseSuspend)
Write0xD0,
AnyAddress
(EraseResume) Write0xFF (ReadArray)
Write Read
Status Data=0x70
Addr=Anyaddress
ReadArray
Data
Write0xFF
0
(ReadArray)
1
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 55
Figure16.BlockEraseFlowchart
Start
FULLERASESTATUSCHECKPROCEDURE
Repeatforsubsequentblockerasures.
FullStatusregistercheckcanbedoneaftereachblockerase
orafterasequenceofblockerasures.
Write0xFFafterthelastoperationtoenterreadarraymode.
SR[1,3]mustbeclearedbeforetheWriteStateMachinewill
allowfurthereraseattempts.
OnlytheClearStatusRegistercommandclearsSR[1,3,4,5].
Ifanerrorisdetected,cleartheStatusregisterbefore
attemptinganeraseretryorothererrorrecovery.
No
Suspend
Erase
1
0
0
0
1
1,1
1
1
0Yes
Suspend
Erase
Loop
0
Write0x20,
BlockAddress
Write0xD0,
BlockAddress
ReadStatus
Register
SR[7]=
FullErase
StatusCheck
(ifdesired)
BlockErase
Complete
ReadStatus
Register
BlockErase
Successful
SR[1]=BlockLocked
Error
BLOCKERASEPROCEDURE
Bus
Operation Command Comments
Write Block
Erase
Setup
Data=0x20
Addr=Blocktobeerased(BA)
Write Erase
Confirm Data=0xD0
Addr=Blocktobeerased(BA)
Read None StatusRegisterdata.ToggleCE#or
OE#toupdateStatusregisterdata
Idle None CheckSR[7]:
1=WSMready
0=WSMbusy
Bus
Operation Command Comments
SR[3]=V
PP
Range
Error
SR[4,5]=Command
SequenceError
SR[5]=BlockErase
Error
Idle None CheckSR[3]:
1=V
PP
RangeError
Idle None CheckSR[4,5]:
Both1=CommandSequenceError
Idle None CheckSR[5]:
1=BlockEraseError
Idle None CheckSR[1]:
1= Attemptederaseoflockedblock;
eraseaborted.
(BlockErase)
(EraseConfirm)
Intel£Advanced+BootBlockFlashMemory(C3)
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Figure17.LockingOperationsFlowchart
No
Start
Write0x60,
BlockAddress
Write0x90
ReadBlock
LockStatus
Locking
Change?
LockChange
Complete
Writeeither
0x01/0xD0/0x2F,
BlockAddress
Write0xFF
AnyAddress
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Idle
(Optional)
Write
Lock
Setup
Lock,
Unlock,or
Lock-Down
Confirm
Read
DeviceID
BlockLock
Status
None
Read
Array
Data=0x60
Addr=AnyAddress
Data=0x01(BlockLock)
0xD0(BlockUnlock)
0x2F(Lock-DownBlock)
Addr=Blocktolock/unlock/lock-down
Data=0x90
Addr=AnyAddress
BlockLockstatusdata
Addr=Blockaddress+offset2
ConfirmlockingchangeonD[1,0] .
Data=0xFF
Addr=Anyaddress
Bus
Operation Command Comments
LOCKINGOPERATIONSPROCEDURE
(LockConfirm)
(ReadDeviceID)
(ReadArray)
Optional
(LockSetup)
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 57
Figure18.ProtectionRegisterProgrammingFlowchart
FULLSTATUSCHECKPROCEDURE
ProgramProtectionRegisteroperationaddressesmustbe
withintheProtectionRegisteraddressspace.Addresses
outsidethisspacewillreturnanerror.
Repeatforsubsequentprogrammingoperations.
FullStatusRegistercheckcanbedoneaftereachprogram,or
afterasequenceofprogramoperations.
Write0xFFafterthelastoperationtosetReadArraystate.
SR[3]mustbeclearedbeforetheWriteStateMachinewill
allowfurtherprogramattempts.
OnlytheClearStausRegistercommandclearsSR[1,3,4].
Ifanerrorisdetected,cleartheStatusregisterbefore
attemptingaprogramretryorothererrorrecovery.
1
0
1
1
PROTECTIONREGISTERPROGRAMMINGPROCEDURE
Start
Write0xC0,
PRAddress
WritePR
Address&Data
ReadStatus
Register
SR[7]=
FullStatus
Check
(ifdesired)
Program
Complete
ReadStatus
RegisterData
Program
Successful
SR[3],SR[4]= V
PP
RangeError
ProgramError
RegisterLocked;
ProgramAborted
Idle
Idle
Bus
Operation
None
None
Command
CheckSR[1],SR[3],SR[4]:
0,1,1=V
PP
RangeError
CheckSR[1],SR[3],SR[4]:
0,0,1= ProgrammingError
Comments
Write
Write
Idle
Program
PRSetup
Protection
Program
None
Data=0xC0
Addr=FirstLocationtoProgram
Data=DatatoProgram
Addr=LocationtoProgram
CheckSR[7]:
1=WSMReady
0=WSMBusy
Bus
Operation Command Comments
Read None StatusRegisterData.ToggleCE#or
OE#toUpdateStatusRegisterData
Idle None CheckSR[1],SR[3],SR[4]:
1,0,1= Blocklocked;operationaborted
(ProgramSetup)
(ConfirmData)
0
0
SR[3],SR[4]=
0
SR[3],SR[4]=
1
Intel£Advanced+BootBlockFlashMemory(C3)
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AppendixCCommonFlashInterface
Thisappendixdefinesthedatastructureor“database”returnedbytheCommonFlashInterface
(CFI)Querycommand.Systemsoftwareshouldparsethisstructuretogaincriticalinformation
suchasblocksize,density,x8/x16,andelectricalspecifications.Oncethisinformationhasbeen
obtained,thesoftwarewillknowwhichcommandsetstousetoenableflashwrites,blockerases,
andotherwisecontroltheflashcomponent.TheQueryispartofanoverallspecificationfor
multiplecommandsetandcontrolinterfacedescriptionscalledCommonFlashInterface,orCFI.
C.1 QueryStructureOutput
TheQuerydatabaseallowssystemsoftwaretoobtaininformationforcontrollingtheflashdevice.
Thissectiondescribesthedevice’sCFI-compliantinterfacethatallowsaccesstoQuerydata.
Querydataarepresentedonthelowest-orderdataoutputs(DQ0-DQ7)only.Thenumericaloffset
valueistheaddressrelativetothemaximumbuswidthsupportedbythedevice.Onthisfamilyof
devices,theQuerytabledevicestartingaddressisa0x10,whichisawordaddressforx16devices.
Foraword-wide(x16)device,thefirsttwoQuery-structurebytes,ASCII“Q”and“R,”appearon
thelowbyteatwordaddresses0x10and0x11.ThisCFI-compliantdeviceoutputs0x00dataon
upperbytes.ThedeviceoutputsASCII“Q”inthelowbyte(DQ0-DQ7)and0x00inthehighbyte
(DQ8-DQ15).
AtQueryaddressescontainingtwoormorebytesofinformation,theleastsignificantdatabyteis
presentedattheloweraddress,andthemostsignificantdatabyteispresentedatthehigheraddress.
Inallofthefollowingtables,addressesanddataarerepresentedinhexadecimalnotation,sothe
“h”suffixhasbeendropped.Inaddition,sincetheupperbyteofword-widedevicesisalways
“0x00,”theleading“00”hasbeendroppedfromthetablenotationandonlythelowerbytevalueis
shown.Anyx16deviceoutputscanbeassumedtohave0x00ontheupperbyteinthismode.
Table24.SummaryofQueryStructureOutputasaFunctionofDeviceandMode
Device HexOffset HexCode ASCIIValue
DeviceAddresses
00010: 51 "Q"
00011: 52 "R"
00012: 59 "Y"
Table25.ExampleofQueryStructureOutputofx16Devices(Sheet1of2)
WordAddressing:
Offset HexCode Value
A[X-0] DQ[16:0]
0x00010 0051 "Q"
0x00011 0052 "R"
0x00012 0059 "Y"
0x00013 P_IDLO PrVendor
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Datasheet 59
C.2 QueryStructureOverview
TheQuerycommandcausestheflashcomponenttodisplaytheCommonFlashInterface(CFI)
Querystructureor“database.”Thestructuresub-sectionsandaddresslocationsaresummarized
below.
C.3 BlockStatusRegister
TheBlockStatusRegisterindicateswhetheraneraseoperationcompletedsuccessfullyorwhether
agivenblockislockedorcanbeaccessedforflashprogram/eraseoperations.
BlockEraseStatus(BSR[1])allowssystemsoftwaretodeterminethesuccessofthelastblock
eraseoperation.BSR[1]canbeusedjustafterpower-uptoverifythattheVCCsupplywasnot
accidentallyremovedduringaneraseoperation.
0x00014 P_IDHI ID#
0x00015 PLO PrVendor
0x00016 PHI TblAdr
0x00017 A_IDLO AltVendor
0x00018 A_IDHI ID#
... ... ...
Table25.ExampleofQueryStructureOutputofx16Devices(Sheet2of2)
Table26.QueryStructure
Offset Sub-SectionName Description1
0x00000 ManufacturerCode
0x00001 DeviceCode
0x(BA+2)2BlockStatusregister Block-specificinformation
0x00004-0xF Reserved Reservedforvendor-specificinformation
0x00010 CFIqueryidentification
string CommandsetIDandvendordataoffset
0x0001B Systeminterface
information Devicetiming&voltageinformation
0x00027 Devicegeometrydefinition Flashdevicelayout
P3PrimaryIntel-specific
ExtendedQueryTable Vendor-definedadditionalinformationspecifictothePrimary
VendorAlgorithm
NOTES:
1. RefertotheQueryStructureOutputsectionandoffset0x28forthedetaileddefinitionofoffsetaddressasa
functionofdevicebuswidthandmode.
2. BA=BlockAddressbeginninglocation(i.e.,0x08000isblock1’sbeginninglocationwhentheblocksizeis
32K-word).
3. Offset15defines“P”whichpointstothePrimaryIntel-specificExtendedQueryTable.
Intel£Advanced+BootBlockFlashMemory(C3)
60 Datasheet
NOTES:
1. BA=BlockAddressbeginninglocation(i.e.,0x08000isblock1’sbeginninglocationwhentheblocksizeis
32K-word).
C.4 CFIQueryIdentificationString
TheIdentificationStringprovidesverificationthatthecomponentsupportstheCommonFlash
Interfacespecification.Italsoindicatesthespecificationversionandsupportedvendor-specified
commandset(s).
Table28.CFIIdentification
Table29.SystemInterfaceInformation
Table27.BlockStatusRegister
Offset Length Description Add. Value
0x(BA+2)11
BlockLockStatusRegister BA+2 --00or--01
BSR[0]Blocklockstatus
0=Unlocked
1=Locked BA+2 (bit0):0or1
BSR[1]Blocklock-downstatus
0=Notlockeddown
1=Lockeddown BA+2 (bit1):0or1
BSR[7:2]:
Reservedforfutureuse BA+2 (bit2-7):0
Offset Length Description Add. HexCode Value
0x10 3 Query-uniqueASCIIstring“QRY“ 10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
0x13 2 PrimaryvendorcommandsetandcontrolinterfaceIDcode
16-bitIDcodeforvendor-specifiedalgorithms 13:
14: --03
--00
0x15 2 ExtendedQueryTableprimaryalgorithmaddress 15:
16: --35
--00
0x17 2 AlternatevendorcommandsetandcontrolinterfaceIDcode
0x0000meansnosecondvendor-specifiedalgorithmexists 17:
18: --00
--00
0x19 2 SecondaryalgorithmExtendedQueryTableaddress
0x0000meansnoneexists 19:
1A: --00
--00
Offset Length Description Add. HexCode Value
0x1B 1 VCClogicsupplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1B: --27 2.7V
0x1C 1 VCClogicsupplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7BCDvolts 1C: --36 3.6V
0x1D 1 VPP[programming]supplyminimumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1D: --B4 11.4V
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C.5 DeviceGeometryDefinition
Table30.DeviceGeometryDefinition
0x1E 1 VPP[programming]supplymaximumprogram/erasevoltage
bits0–3BCD100mV
bits4–7HEXvolts 1E: --C6 12.6V
0x1F 1 “n”suchthattypicalsinglewordprogramtime-out=2nµs 1F: --05 32µs
0x20 1 “n”suchthattypicalmax.bufferwritetime-out=2nµs 20: --00 NA
0x21 1 “n”suchthattypicalblockerasetime-out=2nms 21: --0A 1s
0x22 1 “n”suchthattypicalfullchiperasetime-out=2nms 22: --00 NA
0x23 1 “n”suchthatmaximumwordprogramtime-out=2ntimestypical 23: --04 512µs
0x24 1 “n”suchthatmaximumbufferwritetime-out=2ntimestypical 24: --00 NA
0x25 1 “n”suchthatmaximumblockerasetime-out=2ntimestypical 25: --03 8s
0x26 1 “n”suchthatmaximumchiperasetime-out=2ntimestypical 26: --00 NA
Offset Length Description Add. Hex
Code Value
0x27 1 “n”suchthatdevicesize=2ninnumberofbytes 27 SeeTable31
0x28 2 Flashdeviceinterface: x8async
28:00,29:00 x16async
28:01,29:00 x8/x16async
28:02,29:00 28:
29: --01
--00 x16
0x2A 2 “n”suchthatmaximumnumberofbytesinwritebuffer=2n2A:
2B: --00
--00 0
0x2C 1
Numberoferaseblockregionswithindevice:
1.x=0meansnoeraseblocking;thedeviceerasesin“bulk”
2.xspecifiesthenumberofdeviceorpartitionregions
withoneormorecontiguoussame-sizeeraseblocks.
3.Symmetricallyblockedpartitionshaveoneblockingregion
4.Partitionsize=(totalblocks)x(individualblocksize)
2C: --02 2
0x2D 4
EraseBlockRegion1Information
bits0–15=y,y+1=numberofidentical-sizeeraseblocks
bits16–31=z,regioneraseblock(s)sizearezx256bytes
2D:
2E:
2F:
30:
SeeTable31
0x2D 14
EraseBlockRegion2Information
bits0–15=y,y+1=numberofidentical-sizeeraseblocks
bits16–31=z,regioneraseblock(s)sizearezx256bytes
31:
32:
33:
34:
SeeTable31
Offset Length Description Add. HexCode Value
Intel£Advanced+BootBlockFlashMemory(C3)
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C.6 Intel-SpecificExtendedQueryTable
Certainflashfeaturesandcommandsareoptional.TheIntel-SpecificExtendedQuerytable
specifiesthisandothersimilartypesofinformation.
Table31.DeviceGeometryDetails
Address 16Mbit 32Mbit 64Mbit
-B -T -B -T -B -T
0x27 --15 -15 --16 -16 --17 --17
0x28 --01 --01 --01 --01 --01 --01
0x29 --00 --00 --00 -00 -00 -00
0x2A --00 --00 --00 -00 -00 -00
0x2B --00 --00 --00 -00 -00 -00
0x2C --02 --02 --02 --02 --02 --02
0x2D --07 --1E --07 --3E --07 --7E
0x2E --00 --00 --00 -00 -00 -00
0x2F --20 --00 --20 -00 --20 --00
0x30 --00 --01 --00 --01 --00 --01
0x31 --1E --07 --3E --07 --7E --07
0x32 --00 --00 --00 -00 -00 -00
0x33 --00 --20 --00 --20 --00 --20
0x34 --00 --01 --00 --01 --00 --01
Table32.Primary-VendorSpecificExtendedQuery(Sheet1of2)
Offset1
P=0x15 Length Description
(OptionalFlashFeaturesandCommands) Address HexCode Value
0x(P+0)
0x(P+1)
0x(P+2) 3Primaryextendedquerytable
UniqueASCIIstring“PRI” 35:
36:
37:
--50
--52
--49
“P”
“R”
“I”
0x(P+3) 1 Majorversionnumber,ASCII 38: --31 “1”
0x(P+4) 1 Minorversionnumber,ASCII 39: --30 “0”
0x(P+5)
0x(P+6)
0x(P+7)
0x(P+8) 4
Optionalfeatureandcommandsupport(1=yes,
0=no)
bits9–31arereserved;undefinedbitsare“0.”Ifbit
31is“1”thenanother31bitfieldofoptional
featuresfollowsattheendofthebit-30field.
3A:
3B:
3C:
3D:
--66
--00
--00
--00
bit0Chiperasesupported
bit1Suspenderasesupported
bit2Suspendprogramsupported
bit3Legacylock/unlocksupported
bit4Queuederasesupported
bit5Instantindividualblocklockingsupported
bit6Protectionbitssupported
bit7Pagemodereadsupported
bit8Synchronousreadsupported
bit0=0
bit1=1
bit2=1
bit3=0
bit4=0
bit5=1
bit6=1
bit7=0
bit8=0
No
Yes
Yes
No
No
Yes
Yes
No
No
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 63
0x(P+9) 1
Supportedfunctionsaftersuspend:ReadArray,
Status,Query
Othersupportedoperationsare:
bits1–7reserved;undefinedbitsare“0”
3E: --01
bit0Programsupportedaftererasesuspend bit0=1Yes
0x(P+A)
0x(P+B) 2Blockstatusregistermask
bits2–15areReserved;undefinedbitsare“0”
bit0BlockLock-BitStatusRegisteractive
bit1BlockLock-DownBitStatusactive
3F: --03
40: --00
bit0=1Yes
bit1=1Yes
0x(P+C) 1 VCClogicsupplyhighestperformanceprogram/
erasevoltage
bits0–3BCDvaluein100mV
bits4–7BCDvalueinvolts 41: --33 3.3V
0x(P+D) 1 VPPoptimumprogram/erasesupplyvoltage
bits0–3BCDvaluein100mV
bits4–7HEXvalueinvolts 42: --C0 12.0V
NOTES:
1. ThevariablePisapointerwhichisdefinedatCFIoffset0x15.
Table32.Primary-VendorSpecificExtendedQuery(Sheet2of2)
Offset1
P=0x15 Length Description
(OptionalFlashFeaturesandCommands) Address HexCode Value
Table33.ProtectionRegisterInformation
Offset1
P=0x35 Length Description
(OptionalFlashFeaturesandCommands) Address Hex
Code Value
0x(P+E) 1 NumberofProtectionregisterfieldsinJEDECIDspace.
“00h,”indicatesthat256protectionbytesareavailable 43: --01 01
0x(P+F)
0x(P+10)
(0xP+11)
4
44:
45:
46:
--80
--00
--03
80h
00h
8byte
ProtectionField1:ProtectionDescription
0x(P+12)
Thisfielddescribesuser-availableOneTimeProgrammable(OTP)
Protectionregisterbytes.Somearepre-programmedwithdevice-
uniqueserialnumbers.Othersareuserprogrammable.Bits0–15
pointtotheProtectionregisterLockbyte,thesection’sfirstbyte.
Thefollowingbytesarefactorypre-programmedanduser-
programmable.
bits0–7=Lock/bytesJEDEC-planephysicallowaddress
bits8–15=Lock/bytesJEDEC-planephysicalhighaddress
bits16–23=“n”suchthat2n=factorypre-programmedbytes
bits24–31=“n”suchthat2n=userprogrammablebytes
47: --03 8byte
0x(P+13) Reservedforfutureuse 48:
NOTES:
1. ThevariablePisapointerwhichisdefinedatCFIoffset0x15.
Intel£Advanced+BootBlockFlashMemory(C3)
64 Datasheet
AppendixDMechanicalSpecifications
Figure19.µBGA*andVFBGAPackageDrawing&Dimensions
BottomView-Bumpsideup
e
b
S1
BallA1
Corner
TopView-BumpSidedown
BallA1
Corner
E
D
SideView
A
A2
A
1
Seating
Y
A
B
C
D
E
F
S2
Plan
123
4
5678
A
B
C
D
E
F
123
4
5678
Note:Drawingnottoscale
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
PackageHeight A 1.000 0.0394
BallHeight A1 0.150 0.0059
PackageBodyThickness A2 0.665 0.0262
Ball(Lead)Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
PackageBodyLength8M(.25) D 7.810 7.910 8.010
PackageBodyLength16M(.25/.18/.13)32M(.25/.18/.13) D 7.186 7.286 7.386 0.2829 0.2868 0.2908
PackageBodyLength64M(.18) D 7.600 7.700 7.800 0.2992 0.3031 0.3071
PackageBodyWidth8M(.25) E 6.400 6.500 6.600 0.2520 0.2559 0.2598
PackageBodyWidth16M(.25/.18/.13)32M(.18/.13) E 6.864 6.964 7.064 0.2702 0.2742 0.2781
PackageBodyWidth32M(.25) E 10.750 10.850 10.860 0.4232 0.4272 0.4276
PackageBodyWidth64M(.18) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
Ball(Lead)Count8M,16M N 46 46
Ball(Lead)Count32M N 47 47
Ball(Lead)Count64M N 48 48
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongD8M(.25) S1 1.230 1.330 1.430 0.0484 0.0524 0.0563
CornertoBallA1DistanceAlongD16M(.25/.18/.13)32M(.18/.13) S1 0.918 1.018 1.118 0.0361 0.0401 0.0440
CornertoBallA1DistanceAlongD64M(.18) S1 1.125 1.225 1.325 0.0443 0.0482 0.0522
CornertoBallA1DistanceAlongE8M(.25) S2 1.275 1.375 1.475 0.0502 0.0541 0.0581
CornertoBallA1DistanceAlongE16M(.25/.18/.13)32M(.18/.13)
S2 1.507 1.607 1.707 0.0593 0.0633 0.0672
CornertoBallA1DistanceAlongE32M(.25) S2 3.450 3.550 3.650 0.1358 0.1398 0.1437
CornertoBallA1DistanceAlongE64M(.18) S2 2.525 2.625 2.725 0.0994 0.1033 0.1073
R0
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 65
1. OnedimpleonpackagedenotesPin1.
2. Iftwodimples,thenthelargerdimpledenotesPin1.
3. Pin1willalwaysbeintheupperleftcornerofthepackage,inreferencetotheproductmark.
4. Pin1willalwayssupersedeabovepinonenotes.
Figure20.TSOPPackageDrawing&Dimensions
Dimensions
A5568-02
A
0
L
DetailA
Y
D
C
Z
Pin1
E
D
1
b
DetailB
SeeDetailA
e
SeeDetailB
A
1
A
2
Seating
Plane
SeeNotes1,2,3and4
Family:ThinSmallOut-LinePackage
Symbol Millimeters Inches
Min Nom Max Notes Min Nom Max Notes
PackageHeight A 1.200 0.047
Standoff A1 0.050 0.002
PackageBodyThickness A2 0.950 1.000 1.050 0.037 0.039 0.041
LeadWidth b 0.150 0.200 0.300 0.006 0.008 0.012
LeadThickness c 0.100 0.150 0.200 0.004 0.006 0.008
PlasticBodyLength D1 18.200 18.400 18.600 0.717 0.724 0.732
PackageBodyWidth E 11.800 12.000 12.200 0.465 0.472 0.480
LeadPitch e 0.500 0.0197
TerminalDimension D 19.800 20.000 20.200 0.780 0.787 0.795
LeadTipLength L 0.500 0.600 0.700 0.020 0.024 0.028
LeadCount N 48 48
LeadTipAngle Ø 0° 3° 5° 0° 3° 5°
SeatingPlaneCoplanarity Y 0.100 0.004
LeadtoPackageOffset Z 0.150 0.250 0.350 0.006 0.010 0.014
Intel£Advanced+BootBlockFlashMemory(C3)
66 Datasheet
Figure21.EasyBGAPackageDrawing&Dimension
Millimeters Inches
Symbol Min Nom Max Notes Min Nom Max
PackageHeight A 1.200 0.0472
BallHeight A10.250 0.0098
PackageBodyThickness A20.780 0.0307
Ball(Lead)Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
PackageBodyWidth D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976
PackageBodyLength E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157
Pitch [e] 1.000 0.0394
Ball(Lead)Count N 64 64
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongDS
11.400 1.500 1.600 1 0.0551 0.0591 0.0630
CornertoBallA1DistanceAlongE S22.900 3.000 3.100 1 0.1142 0.1181 0.1220
DimensionsTable
Note:(1)Packagedimensionsareforreferenceonly.Thesedimensionsareestimatesbased
ondiesize,andaresub
j
ecttochan
g
e.
E
Seating
Plane
S1
S2
e
TopView -Ballsidedown Bottom View -BallSideUp
Y
A
A1
D
BallA1
Corner
A2
Note:Drawingnottoscale
A
B
C
D
E
F
G
H
8765432187654321
A
B
C
D
E
F
G
H
b
BallA1
Corner
SideView
Intel£Advanced+BootBlockFlashMemory(C3)
Datasheet 67
AppendixEAdditionalInformation
OrderNumber Document/Tool
297938 3VoltAdvanced+BootBlockFlashMemorySpecificationUpdate
292216 AP-658DesigningforUpgradetotheAdvanced+BootBlockFlashMemory
292215 AP-657DesigningwiththeAdvanced+BootBlockFlashMemory
Architecture
ContactyourIntel
Representative Intel®FlashDataIntegrator(FDI)SoftwareDeveloper’sKit
297874 IFDIInteractive:PlaywithIntel®FlashDataIntegratoronYourPC
NOTES:
1. PleasecalltheIntelLiteratureCenterat(800)548-4725torequestInteldocumentation.International
customersshouldcontacttheirlocalIntelordistributionsalesoffice.
2. VisitIntel’sWorldWideWebhomepageat‘http://www.intel.com/design/flash’fortechnical
documentationandtools.
Intel£Advanced+BootBlockFlashMemory(C3)
68 Datasheet
AppendixFOrderingInformation
Figure22.ComponentOrderingInformation
VALIDCOMBINATIONS(AllExtendedTemperature)
48-LeadTSOP 48-BallµBGA*CSP 48-BallVFBGA EasyBGA
Extended
64Mbit TE28F640C3TC80
TE28F640C3BC80 GE28F640C3TC80
GE28F640C3BC80 RC28F640C3TC80
RC28F640C3BC80
Extended
32Mbit
TE28F320C3TD70
TE28F320C3BD70
TE28F320C3TC70
TE28F320C3BC70
TE28F320C3TC90
TE28F320C3BC90
TE28F320C3TA100
TE28F320C3BA100
TE28F320C3TA110
TE28F320C3BA110
GT28F320C3TA100
GT28F320C3BA100
GT28F320C3TA110
GT28F320C3BA110
GE28F320C3TD70
GE28F320C3BD70
GE28F320C3TC70
GE28F320C3BC70
GE28F320C3TC90
GE28F320C3BC90
RC28F320C3TD70
RC28F320C3BD70
RC28F320C3TD90
RC28F320C3BD90
RC28F320C3TC90
RC28F320C3BC90
RC28F320C3TA100
RC28F320C3BA100
RC28F320C3TA110
RC28F320C3BA110
Extended
16Mbit
TE28F160C3TD70
TE28F160C3BD70
TE28F160C3TC70
TE28F160C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F160C3TC90
TE28F160C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F160C3TA110
TE28F160C3BA110
GT28F160C3TA90
GT28F160C3BA90
GT28F160C3TA110
GT28F160C3BA110
GE28F160C3TD70
GE28F160C3BD70
GE28F160C3TC70
GE28F160C3BC70
GE28F160C3TC80
GE28F160C3BC80
GE28F160C3TC90
GE28F160C3BC90
RC28F160C3TD70
RC28F160C3BD70
RC28F160C3TC70
RC28F160C3BC70
RC28F160C3TC80
RC28F160C3BC80
RC28F160C3TC90
RC28F160C3BC90
RC28F160C3TA90
RC28F160C3BA90
RC28F160C3TA110
RC28F160C3BA110
Extended
8Mbit
TE28F800C3TA90
TE28F800C3BA90
TE28F800C3TA110
TE28F800C3BA110
GE28F800C3TA70
GE28F800C3BA70
GE28F800C3TA90
GE28F800C3BA90
RC28F800C3TA90
RC28F800C3BA90
RC28F800C3TA110
RC28F800C3BA110
NOTE: Thesecondlineofthe48-ballµBGApackagetopsidemarkspecifiesassemblycodes.Forsamples
only,thefirstcharactersignifieseither“E”forengineeringsamplesor“S”forsilicondaisychain
samples.Allotherassemblycodeswithoutan“E”or“S”asthefirstcharacterareproductionunits.
Lithography
A=0.25µm
C=0.18µm
D=0.13µm
Package
TE=48-LeadTSOP
GT=48-BallµBGA*CSP
GE=VFBGACSP
RC=EasyBGA
AccessSpeed(ns)
(70,80,90,100,110)
ProductFamily
C3=3VoltAdvanced+BootBloc
k
VCC=2.7V–3.6V
VPP=2.7V–3.6Vor
11.4V–12.6V
DeviceDensity
640=x16(64Mbit)
320=x16(32Mbit)
160=x16(16Mbit)
800=x16(8Mbit)
T=TopParameterBoot
B=BottomParameterBoot
T E 2 8 F 3 2 0 C 3 T C 7 0
Productlinedesignator
forallIntel®Flashproducts